commit 9eabb9110094d92e112d1027e2f05133fa4ae602 · tjh.dev/kernel

tjh.dev / kernel

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

Merge branch 'drm-fixes-3.15' of git://people.freedesktop.org/~deathsimple/linux into drm-fixes

this is the next pull quested for stashed up radeon fixes for 3.15. As discussed support for Mullins was separated out and will get it's own pull request. Remaining highlights are:
1. Some more patches to better handle PLL limits.
2. Making use of the PFLIP additional to the VBLANK interrupt, otherwise we sometimes miss page flip events.
3. Fix for the UVD command stream parser.
4. Fix for bootup UVD clocks on RV7xx systems.
5. Adding missing error check on dpcd reads.
6. Fixes number of banks calculation on SI.

* 'drm-fixes-3.15' of git://people.freedesktop.org/~deathsimple/linux:
drm/radeon: lower the ref * post PLL maximum
drm/radeon: check that we have a clock before PLL setup
drm/radeon: drm/radeon: add missing radeon_semaphore_free to error path
drm/radeon: Fix num_banks calculation for SI
drm/radeon/dp: check for errors in dpcd reads
drm/radeon: avoid high jitter with small frac divs
drm/radeon: check buffer relocation offset
drm/radeon: use pflip irq on R600+ v2
drm/radeon/uvd: use lower clocks on old UVD to boot v2

Dave Airlie 11 years ago 9eabb911 3cf0b031

+238 -56

16 changed files

expand all

unified split

drivers

gpu

drm

radeon

atombios_crtc.c

atombios_dp.c

cik.c

cik_sdma.c

cikd.h

evergreen.c

evergreen_dma.c

r600.c

r600_dma.c

radeon.h

radeon_display.c

radeon_uvd.c

rv770_dma.c

si.c

si_dma.c

uvd_v1_0.c

+34 -15

drivers/gpu/drm/radeon/atombios_crtc.c

··· 1177 1177 1178 1178 /* Set NUM_BANKS. */ 1179 1179 if (rdev->family >= CHIP_TAHITI) { 1180 - unsigned tileb, index, num_banks, tile_split_bytes; 1180 + unsigned index, num_banks; 1181 1181 1182 - /* Calculate the macrotile mode index. */ 1183 - tile_split_bytes = 64 << tile_split; 1184 - tileb = 8 * 8 * target_fb->bits_per_pixel / 8; 1185 - tileb = min(tile_split_bytes, tileb); 1182 + if (rdev->family >= CHIP_BONAIRE) { 1183 + unsigned tileb, tile_split_bytes; 1186 1184 1187 - for (index = 0; tileb > 64; index++) { 1188 - tileb >>= 1; 1189 - } 1185 + /* Calculate the macrotile mode index. */ 1186 + tile_split_bytes = 64 << tile_split; 1187 + tileb = 8 * 8 * target_fb->bits_per_pixel / 8; 1188 + tileb = min(tile_split_bytes, tileb); 1190 1189 1191 - if (index >= 16) { 1192 - DRM_ERROR("Wrong screen bpp (%u) or tile split (%u)\n", 1193 - target_fb->bits_per_pixel, tile_split); 1194 - return -EINVAL; 1195 - } 1190 + for (index = 0; tileb > 64; index++) 1191 + tileb >>= 1; 1196 1192 1197 - if (rdev->family >= CHIP_BONAIRE) 1193 + if (index >= 16) { 1194 + DRM_ERROR("Wrong screen bpp (%u) or tile split (%u)\n", 1195 + target_fb->bits_per_pixel, tile_split); 1196 + return -EINVAL; 1197 + } 1198 + 1198 1199 num_banks = (rdev->config.cik.macrotile_mode_array[index] >> 6) & 0x3; 1199 - else 1200 + } else { 1201 + switch (target_fb->bits_per_pixel) { 1202 + case 8: 1203 + index = 10; 1204 + break; 1205 + case 16: 1206 + index = SI_TILE_MODE_COLOR_2D_SCANOUT_16BPP; 1207 + break; 1208 + default: 1209 + case 32: 1210 + index = SI_TILE_MODE_COLOR_2D_SCANOUT_32BPP; 1211 + break; 1212 + } 1213 + 1200 1214 num_banks = (rdev->config.si.tile_mode_array[index] >> 20) & 0x3; 1215 + } 1216 + 1201 1217 fb_format |= EVERGREEN_GRPH_NUM_BANKS(num_banks); 1202 1218 } else { 1203 1219 /* NI and older. */ ··· 1900 1884 if (radeon_encoder->active_device & 1901 1885 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) 1902 1886 is_tvcv = true; 1887 + 1888 + if (!radeon_crtc->adjusted_clock) 1889 + return -EINVAL; 1903 1890 1904 1891 atombios_crtc_set_pll(crtc, adjusted_mode); 1905 1892

+25 -19

drivers/gpu/drm/radeon/atombios_dp.c

··· 366 366 if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) 367 367 return; 368 368 369 - if (drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_SINK_OUI, buf, 3)) 369 + if (drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_SINK_OUI, buf, 3) == 3) 370 370 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n", 371 371 buf[0], buf[1], buf[2]); 372 372 373 - if (drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_BRANCH_OUI, buf, 3)) 373 + if (drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_BRANCH_OUI, buf, 3) == 3) 374 374 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n", 375 375 buf[0], buf[1], buf[2]); 376 376 } ··· 419 419 420 420 if (dp_bridge != ENCODER_OBJECT_ID_NONE) { 421 421 /* DP bridge chips */ 422 - drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux, 423 - DP_EDP_CONFIGURATION_CAP, &tmp); 424 - if (tmp & 1) 425 - panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE; 426 - else if ((dp_bridge == ENCODER_OBJECT_ID_NUTMEG) || 427 - (dp_bridge == ENCODER_OBJECT_ID_TRAVIS)) 428 - panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE; 429 - else 430 - panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; 422 + if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux, 423 + DP_EDP_CONFIGURATION_CAP, &tmp) == 1) { 424 + if (tmp & 1) 425 + panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE; 426 + else if ((dp_bridge == ENCODER_OBJECT_ID_NUTMEG) || 427 + (dp_bridge == ENCODER_OBJECT_ID_TRAVIS)) 428 + panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE; 429 + else 430 + panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; 431 + } 431 432 } else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 432 433 /* eDP */ 433 - drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux, 434 - DP_EDP_CONFIGURATION_CAP, &tmp); 435 - if (tmp & 1) 436 - panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE; 434 + if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux, 435 + DP_EDP_CONFIGURATION_CAP, &tmp) == 1) { 436 + if (tmp & 1) 437 + panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE; 438 + } 437 439 } 438 440 439 441 return panel_mode; ··· 811 809 else 812 810 dp_info.enc_id |= ATOM_DP_CONFIG_LINK_A; 813 811 814 - drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux, DP_MAX_LANE_COUNT, &tmp); 815 - if (ASIC_IS_DCE5(rdev) && (tmp & DP_TPS3_SUPPORTED)) 816 - dp_info.tp3_supported = true; 817 - else 812 + if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux, DP_MAX_LANE_COUNT, &tmp) 813 + == 1) { 814 + if (ASIC_IS_DCE5(rdev) && (tmp & DP_TPS3_SUPPORTED)) 815 + dp_info.tp3_supported = true; 816 + else 817 + dp_info.tp3_supported = false; 818 + } else { 818 819 dp_info.tp3_supported = false; 820 + } 819 821 820 822 memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE); 821 823 dp_info.rdev = rdev;

+77

drivers/gpu/drm/radeon/cik.c

··· 3702 3702 r = radeon_fence_emit(rdev, fence, ring->idx); 3703 3703 if (r) { 3704 3704 radeon_ring_unlock_undo(rdev, ring); 3705 + radeon_semaphore_free(rdev, &sem, NULL); 3705 3706 return r; 3706 3707 } 3707 3708 ··· 6694 6693 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); 6695 6694 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); 6696 6695 } 6696 + /* pflip */ 6697 + if (rdev->num_crtc >= 2) { 6698 + WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); 6699 + WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); 6700 + } 6701 + if (rdev->num_crtc >= 4) { 6702 + WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); 6703 + WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); 6704 + } 6705 + if (rdev->num_crtc >= 6) { 6706 + WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); 6707 + WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); 6708 + } 6697 6709 6698 6710 /* dac hotplug */ 6699 6711 WREG32(DAC_AUTODETECT_INT_CONTROL, 0); ··· 7063 7049 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6); 7064 7050 } 7065 7051 7052 + if (rdev->num_crtc >= 2) { 7053 + WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 7054 + GRPH_PFLIP_INT_MASK); 7055 + WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 7056 + GRPH_PFLIP_INT_MASK); 7057 + } 7058 + if (rdev->num_crtc >= 4) { 7059 + WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 7060 + GRPH_PFLIP_INT_MASK); 7061 + WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 7062 + GRPH_PFLIP_INT_MASK); 7063 + } 7064 + if (rdev->num_crtc >= 6) { 7065 + WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 7066 + GRPH_PFLIP_INT_MASK); 7067 + WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 7068 + GRPH_PFLIP_INT_MASK); 7069 + } 7070 + 7066 7071 WREG32(DC_HPD1_INT_CONTROL, hpd1); 7067 7072 WREG32(DC_HPD2_INT_CONTROL, hpd2); 7068 7073 WREG32(DC_HPD3_INT_CONTROL, hpd3); ··· 7118 7085 rdev->irq.stat_regs.cik.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5); 7119 7086 rdev->irq.stat_regs.cik.disp_int_cont6 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE6); 7120 7087 7088 + rdev->irq.stat_regs.cik.d1grph_int = RREG32(GRPH_INT_STATUS + 7089 + EVERGREEN_CRTC0_REGISTER_OFFSET); 7090 + rdev->irq.stat_regs.cik.d2grph_int = RREG32(GRPH_INT_STATUS + 7091 + EVERGREEN_CRTC1_REGISTER_OFFSET); 7092 + if (rdev->num_crtc >= 4) { 7093 + rdev->irq.stat_regs.cik.d3grph_int = RREG32(GRPH_INT_STATUS + 7094 + EVERGREEN_CRTC2_REGISTER_OFFSET); 7095 + rdev->irq.stat_regs.cik.d4grph_int = RREG32(GRPH_INT_STATUS + 7096 + EVERGREEN_CRTC3_REGISTER_OFFSET); 7097 + } 7098 + if (rdev->num_crtc >= 6) { 7099 + rdev->irq.stat_regs.cik.d5grph_int = RREG32(GRPH_INT_STATUS + 7100 + EVERGREEN_CRTC4_REGISTER_OFFSET); 7101 + rdev->irq.stat_regs.cik.d6grph_int = RREG32(GRPH_INT_STATUS + 7102 + EVERGREEN_CRTC5_REGISTER_OFFSET); 7103 + } 7104 + 7105 + if (rdev->irq.stat_regs.cik.d1grph_int & GRPH_PFLIP_INT_OCCURRED) 7106 + WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, 7107 + GRPH_PFLIP_INT_CLEAR); 7108 + if (rdev->irq.stat_regs.cik.d2grph_int & GRPH_PFLIP_INT_OCCURRED) 7109 + WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, 7110 + GRPH_PFLIP_INT_CLEAR); 7121 7111 if (rdev->irq.stat_regs.cik.disp_int & LB_D1_VBLANK_INTERRUPT) 7122 7112 WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK); 7123 7113 if (rdev->irq.stat_regs.cik.disp_int & LB_D1_VLINE_INTERRUPT) ··· 7151 7095 WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK); 7152 7096 7153 7097 if (rdev->num_crtc >= 4) { 7098 + if (rdev->irq.stat_regs.cik.d3grph_int & GRPH_PFLIP_INT_OCCURRED) 7099 + WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, 7100 + GRPH_PFLIP_INT_CLEAR); 7101 + if (rdev->irq.stat_regs.cik.d4grph_int & GRPH_PFLIP_INT_OCCURRED) 7102 + WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, 7103 + GRPH_PFLIP_INT_CLEAR); 7154 7104 if (rdev->irq.stat_regs.cik.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) 7155 7105 WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK); 7156 7106 if (rdev->irq.stat_regs.cik.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) ··· 7168 7106 } 7169 7107 7170 7108 if (rdev->num_crtc >= 6) { 7109 + if (rdev->irq.stat_regs.cik.d5grph_int & GRPH_PFLIP_INT_OCCURRED) 7110 + WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, 7111 + GRPH_PFLIP_INT_CLEAR); 7112 + if (rdev->irq.stat_regs.cik.d6grph_int & GRPH_PFLIP_INT_OCCURRED) 7113 + WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, 7114 + GRPH_PFLIP_INT_CLEAR); 7171 7115 if (rdev->irq.stat_regs.cik.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) 7172 7116 WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK); 7173 7117 if (rdev->irq.stat_regs.cik.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) ··· 7524 7456 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 7525 7457 break; 7526 7458 } 7459 + break; 7460 + case 8: /* D1 page flip */ 7461 + case 10: /* D2 page flip */ 7462 + case 12: /* D3 page flip */ 7463 + case 14: /* D4 page flip */ 7464 + case 16: /* D5 page flip */ 7465 + case 18: /* D6 page flip */ 7466 + DRM_DEBUG("IH: D%d flip\n", ((src_id - 8) >> 1) + 1); 7467 + radeon_crtc_handle_flip(rdev, (src_id - 8) >> 1); 7527 7468 break; 7528 7469 case 42: /* HPD hotplug */ 7529 7470 switch (src_data) {

drivers/gpu/drm/radeon/cik_sdma.c

··· 562 562 r = radeon_fence_emit(rdev, fence, ring->idx); 563 563 if (r) { 564 564 radeon_ring_unlock_undo(rdev, ring); 565 + radeon_semaphore_free(rdev, &sem, NULL); 565 566 return r; 566 567 } 567 568

drivers/gpu/drm/radeon/cikd.h

··· 888 888 # define DC_HPD6_RX_INTERRUPT (1 << 18) 889 889 #define DISP_INTERRUPT_STATUS_CONTINUE6 0x6780 890 890 891 + /* 0x6858, 0x7458, 0x10058, 0x10c58, 0x11858, 0x12458 */ 892 + #define GRPH_INT_STATUS 0x6858 893 + # define GRPH_PFLIP_INT_OCCURRED (1 << 0) 894 + # define GRPH_PFLIP_INT_CLEAR (1 << 8) 895 + /* 0x685c, 0x745c, 0x1005c, 0x10c5c, 0x1185c, 0x1245c */ 896 + #define GRPH_INT_CONTROL 0x685c 897 + # define GRPH_PFLIP_INT_MASK (1 << 0) 898 + # define GRPH_PFLIP_INT_TYPE (1 << 8) 899 + 891 900 #define DAC_AUTODETECT_INT_CONTROL 0x67c8 892 901 893 902 #define DC_HPD1_INT_STATUS 0x601c

+21 -7

drivers/gpu/drm/radeon/evergreen.c

··· 4371 4371 u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0; 4372 4372 u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6; 4373 4373 u32 grbm_int_cntl = 0; 4374 - u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0; 4375 4374 u32 afmt1 = 0, afmt2 = 0, afmt3 = 0, afmt4 = 0, afmt5 = 0, afmt6 = 0; 4376 4375 u32 dma_cntl, dma_cntl1 = 0; 4377 4376 u32 thermal_int = 0; ··· 4553 4554 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6); 4554 4555 } 4555 4556 4556 - WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1); 4557 - WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2); 4557 + WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 4558 + GRPH_PFLIP_INT_MASK); 4559 + WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 4560 + GRPH_PFLIP_INT_MASK); 4558 4561 if (rdev->num_crtc >= 4) { 4559 - WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3); 4560 - WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4); 4562 + WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 4563 + GRPH_PFLIP_INT_MASK); 4564 + WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 4565 + GRPH_PFLIP_INT_MASK); 4561 4566 } 4562 4567 if (rdev->num_crtc >= 6) { 4563 - WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5); 4564 - WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6); 4568 + WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 4569 + GRPH_PFLIP_INT_MASK); 4570 + WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 4571 + GRPH_PFLIP_INT_MASK); 4565 4572 } 4566 4573 4567 4574 WREG32(DC_HPD1_INT_CONTROL, hpd1); ··· 4955 4950 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 4956 4951 break; 4957 4952 } 4953 + break; 4954 + case 8: /* D1 page flip */ 4955 + case 10: /* D2 page flip */ 4956 + case 12: /* D3 page flip */ 4957 + case 14: /* D4 page flip */ 4958 + case 16: /* D5 page flip */ 4959 + case 18: /* D6 page flip */ 4960 + DRM_DEBUG("IH: D%d flip\n", ((src_id - 8) >> 1) + 1); 4961 + radeon_crtc_handle_flip(rdev, (src_id - 8) >> 1); 4958 4962 break; 4959 4963 case 42: /* HPD hotplug */ 4960 4964 switch (src_data) {

drivers/gpu/drm/radeon/evergreen_dma.c

··· 151 151 r = radeon_fence_emit(rdev, fence, ring->idx); 152 152 if (r) { 153 153 radeon_ring_unlock_undo(rdev, ring); 154 + radeon_semaphore_free(rdev, &sem, NULL); 154 155 return r; 155 156 } 156 157

+11 -3

drivers/gpu/drm/radeon/r600.c

··· 2839 2839 r = radeon_fence_emit(rdev, fence, ring->idx); 2840 2840 if (r) { 2841 2841 radeon_ring_unlock_undo(rdev, ring); 2842 + radeon_semaphore_free(rdev, &sem, NULL); 2842 2843 return r; 2843 2844 } 2844 2845 ··· 3506 3505 u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0; 3507 3506 u32 grbm_int_cntl = 0; 3508 3507 u32 hdmi0, hdmi1; 3509 - u32 d1grph = 0, d2grph = 0; 3510 3508 u32 dma_cntl; 3511 3509 u32 thermal_int = 0; 3512 3510 ··· 3614 3614 WREG32(CP_INT_CNTL, cp_int_cntl); 3615 3615 WREG32(DMA_CNTL, dma_cntl); 3616 3616 WREG32(DxMODE_INT_MASK, mode_int); 3617 - WREG32(D1GRPH_INTERRUPT_CONTROL, d1grph); 3618 - WREG32(D2GRPH_INTERRUPT_CONTROL, d2grph); 3617 + WREG32(D1GRPH_INTERRUPT_CONTROL, DxGRPH_PFLIP_INT_MASK); 3618 + WREG32(D2GRPH_INTERRUPT_CONTROL, DxGRPH_PFLIP_INT_MASK); 3619 3619 WREG32(GRBM_INT_CNTL, grbm_int_cntl); 3620 3620 if (ASIC_IS_DCE3(rdev)) { 3621 3621 WREG32(DC_HPD1_INT_CONTROL, hpd1); ··· 3917 3917 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 3918 3918 break; 3919 3919 } 3920 + break; 3921 + case 9: /* D1 pflip */ 3922 + DRM_DEBUG("IH: D1 flip\n"); 3923 + radeon_crtc_handle_flip(rdev, 0); 3924 + break; 3925 + case 11: /* D2 pflip */ 3926 + DRM_DEBUG("IH: D2 flip\n"); 3927 + radeon_crtc_handle_flip(rdev, 1); 3920 3928 break; 3921 3929 case 19: /* HPD/DAC hotplug */ 3922 3930 switch (src_data) {

drivers/gpu/drm/radeon/r600_dma.c

··· 489 489 r = radeon_fence_emit(rdev, fence, ring->idx); 490 490 if (r) { 491 491 radeon_ring_unlock_undo(rdev, ring); 492 + radeon_semaphore_free(rdev, &sem, NULL); 492 493 return r; 493 494 } 494 495

drivers/gpu/drm/radeon/radeon.h

··· 730 730 u32 disp_int_cont4; 731 731 u32 disp_int_cont5; 732 732 u32 disp_int_cont6; 733 + u32 d1grph_int; 734 + u32 d2grph_int; 735 + u32 d3grph_int; 736 + u32 d4grph_int; 737 + u32 d5grph_int; 738 + u32 d6grph_int; 733 739 }; 734 740 735 741 union radeon_irq_stat_regs {

+17 -3

drivers/gpu/drm/radeon/radeon_display.c

··· 284 284 u32 update_pending; 285 285 int vpos, hpos; 286 286 287 + /* can happen during initialization */ 288 + if (radeon_crtc == NULL) 289 + return; 290 + 287 291 spin_lock_irqsave(&rdev->ddev->event_lock, flags); 288 292 work = radeon_crtc->unpin_work; 289 293 if (work == NULL || ··· 830 826 831 827 /* make sure nominator is large enough */ 832 828 if (*nom < nom_min) { 833 - tmp = (nom_min + *nom - 1) / *nom; 829 + tmp = DIV_ROUND_UP(nom_min, *nom); 834 830 *nom *= tmp; 835 831 *den *= tmp; 836 832 } 837 833 838 834 /* make sure the denominator is large enough */ 839 835 if (*den < den_min) { 840 - tmp = (den_min + *den - 1) / *den; 836 + tmp = DIV_ROUND_UP(den_min, *den); 841 837 *nom *= tmp; 842 838 *den *= tmp; 843 839 } ··· 862 858 unsigned *fb_div, unsigned *ref_div) 863 859 { 864 860 /* limit reference * post divider to a maximum */ 865 - ref_div_max = min(210 / post_div, ref_div_max); 861 + ref_div_max = min(128 / post_div, ref_div_max); 866 862 867 863 /* get matching reference and feedback divider */ 868 864 *ref_div = min(max(DIV_ROUND_CLOSEST(den, post_div), 1u), ref_div_max); ··· 996 992 /* reduce the numbers to a simpler ratio once more */ 997 993 /* this also makes sure that the reference divider is large enough */ 998 994 avivo_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min); 995 + 996 + /* avoid high jitter with small fractional dividers */ 997 + if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && (fb_div % 10)) { 998 + fb_div_min = max(fb_div_min, (9 - (fb_div % 10)) * 20 + 60); 999 + if (fb_div < fb_div_min) { 1000 + unsigned tmp = DIV_ROUND_UP(fb_div_min, fb_div); 1001 + fb_div *= tmp; 1002 + ref_div *= tmp; 1003 + } 1004 + } 999 1005 1000 1006 /* and finally save the result */ 1001 1007 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {

drivers/gpu/drm/radeon/radeon_uvd.c

··· 465 465 cmd = radeon_get_ib_value(p, p->idx) >> 1; 466 466 467 467 if (cmd < 0x4) { 468 + if (end <= start) { 469 + DRM_ERROR("invalid reloc offset %X!\n", offset); 470 + return -EINVAL; 471 + } 468 472 if ((end - start) < buf_sizes[cmd]) { 469 473 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd, 470 474 (unsigned)(end - start), buf_sizes[cmd]);

drivers/gpu/drm/radeon/rv770_dma.c

··· 86 86 r = radeon_fence_emit(rdev, fence, ring->idx); 87 87 if (r) { 88 88 radeon_ring_unlock_undo(rdev, ring); 89 + radeon_semaphore_free(rdev, &sem, NULL); 89 90 return r; 90 91 } 91 92

+21 -7

drivers/gpu/drm/radeon/si.c

··· 5780 5780 u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0; 5781 5781 u32 hpd1 = 0, hpd2 = 0, hpd3 = 0, hpd4 = 0, hpd5 = 0, hpd6 = 0; 5782 5782 u32 grbm_int_cntl = 0; 5783 - u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0; 5784 5783 u32 dma_cntl, dma_cntl1; 5785 5784 u32 thermal_int = 0; 5786 5785 ··· 5918 5919 } 5919 5920 5920 5921 if (rdev->num_crtc >= 2) { 5921 - WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1); 5922 - WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2); 5922 + WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 5923 + GRPH_PFLIP_INT_MASK); 5924 + WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 5925 + GRPH_PFLIP_INT_MASK); 5923 5926 } 5924 5927 if (rdev->num_crtc >= 4) { 5925 - WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3); 5926 - WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4); 5928 + WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 5929 + GRPH_PFLIP_INT_MASK); 5930 + WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 5931 + GRPH_PFLIP_INT_MASK); 5927 5932 } 5928 5933 if (rdev->num_crtc >= 6) { 5929 - WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5); 5930 - WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6); 5934 + WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 5935 + GRPH_PFLIP_INT_MASK); 5936 + WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 5937 + GRPH_PFLIP_INT_MASK); 5931 5938 } 5932 5939 5933 5940 if (!ASIC_IS_NODCE(rdev)) { ··· 6296 6291 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 6297 6292 break; 6298 6293 } 6294 + break; 6295 + case 8: /* D1 page flip */ 6296 + case 10: /* D2 page flip */ 6297 + case 12: /* D3 page flip */ 6298 + case 14: /* D4 page flip */ 6299 + case 16: /* D5 page flip */ 6300 + case 18: /* D6 page flip */ 6301 + DRM_DEBUG("IH: D%d flip\n", ((src_id - 8) >> 1) + 1); 6302 + radeon_crtc_handle_flip(rdev, (src_id - 8) >> 1); 6299 6303 break; 6300 6304 case 42: /* HPD hotplug */ 6301 6305 switch (src_data) {

drivers/gpu/drm/radeon/si_dma.c

··· 213 213 r = radeon_fence_emit(rdev, fence, ring->idx); 214 214 if (r) { 215 215 radeon_ring_unlock_undo(rdev, ring); 216 + radeon_semaphore_free(rdev, &sem, NULL); 216 217 return r; 217 218 } 218 219

+8 -2

drivers/gpu/drm/radeon/uvd_v1_0.c

··· 83 83 int r; 84 84 85 85 /* raise clocks while booting up the VCPU */ 86 - radeon_set_uvd_clocks(rdev, 53300, 40000); 86 + if (rdev->family < CHIP_RV740) 87 + radeon_set_uvd_clocks(rdev, 10000, 10000); 88 + else 89 + radeon_set_uvd_clocks(rdev, 53300, 40000); 87 90 88 91 r = uvd_v1_0_start(rdev); 89 92 if (r) ··· 410 407 struct radeon_fence *fence = NULL; 411 408 int r; 412 409 413 - r = radeon_set_uvd_clocks(rdev, 53300, 40000); 410 + if (rdev->family < CHIP_RV740) 411 + r = radeon_set_uvd_clocks(rdev, 10000, 10000); 412 + else 413 + r = radeon_set_uvd_clocks(rdev, 53300, 40000); 414 414 if (r) { 415 415 DRM_ERROR("radeon: failed to raise UVD clocks (%d).\n", r); 416 416 return r;