Merge tag 'xtensa-for-next-20160731' of git://github.com/jcmvbkbc/linux-xtensa into for_next

+144 -25

Documentation/xtensa/mmu.txt

··· 3 3 The code in the initialize_mmu macro sets up MMUv3 memory mapping 4 4 identically to MMUv2 fixed memory mapping. Depending on 5 5 CONFIG_INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX symbol this code is 6 - located in one of the following address ranges: 7 - 8 - 0xF0000000..0xFFFFFFFF (will keep same address in MMU v2 layout; 9 - typically ROM) 10 - 0x00000000..0x07FFFFFF (system RAM; this code is actually linked 11 - at 0xD0000000..0xD7FFFFFF [cached] 12 - or 0xD8000000..0xDFFFFFFF [uncached]; 13 - in any case, initially runs elsewhere 14 - than linked, so have to be careful) 6 + located in addresses it was linked for (symbol undefined), or not 7 + (symbol defined), so it needs to be position-independent. 15 8 16 9 The code has the following assumptions: 17 10 This code fragment is run only on an MMU v3. ··· 21 28 PA = physical address (two upper nibbles of it); 22 29 pc = physical range that contains this code; 23 30 24 - After step 2, we jump to virtual address in 0x40000000..0x5fffffff 25 - that corresponds to next instruction to execute in this code. 26 - After step 4, we jump to intended (linked) address of this code. 31 + After step 2, we jump to virtual address in the range 0x40000000..0x5fffffff 32 + or 0x00000000..0x1fffffff, depending on whether the kernel was loaded below 33 + 0x40000000 or above. That address corresponds to next instruction to execute 34 + in this code. After step 4, we jump to intended (linked) address of this code. 35 + The scheme below assumes that the kernel is loaded below 0x40000000. 27 36 28 - Step 0 Step1 Step 2 Step3 Step 4 Step5 29 - ============ ===== ============ ===== ============ ===== 30 - VA PA PA VA PA PA VA PA PA 31 - ------ -- -- ------ -- -- ------ -- -- 32 - E0..FF -> E0 -> E0 E0..FF -> E0 F0..FF -> F0 -> F0 33 - C0..DF -> C0 -> C0 C0..DF -> C0 E0..EF -> F0 -> F0 34 - A0..BF -> A0 -> A0 A0..BF -> A0 D8..DF -> 00 -> 00 35 - 80..9F -> 80 -> 80 80..9F -> 80 D0..D7 -> 00 -> 00 36 - 60..7F -> 60 -> 60 60..7F -> 60 37 - 40..5F -> 40 40..5F -> pc -> pc 40..5F -> pc 38 - 20..3F -> 20 -> 20 20..3F -> 20 39 - 00..1F -> 00 -> 00 00..1F -> 00 37 + Step0 Step1 Step2 Step3 Step4 Step5 38 + ===== ===== ===== ===== ===== ===== 39 + VA PA PA PA PA VA PA PA 40 + ------ -- -- -- -- ------ -- -- 41 + E0..FF -> E0 -> E0 -> E0 F0..FF -> F0 -> F0 42 + C0..DF -> C0 -> C0 -> C0 E0..EF -> F0 -> F0 43 + A0..BF -> A0 -> A0 -> A0 D8..DF -> 00 -> 00 44 + 80..9F -> 80 -> 80 -> 80 D0..D7 -> 00 -> 00 45 + 60..7F -> 60 -> 60 -> 60 46 + 40..5F -> 40 -> pc -> pc 40..5F -> pc 47 + 20..3F -> 20 -> 20 -> 20 48 + 00..1F -> 00 -> 00 -> 00 40 49 41 - The default location of IO peripherals is above 0xf0000000. This may change 50 + The default location of IO peripherals is above 0xf0000000. This may be changed 42 51 using a "ranges" property in a device tree simple-bus node. See ePAPR 1.1, §6.5 43 52 for details on the syntax and semantic of simple-bus nodes. The following 44 53 limitations apply: ··· 57 62 58 63 6. The IO area covers the entire 256MB segment of parent-bus-address; the 59 64 "ranges" triplet length field is ignored 65 + 66 + 67 + MMUv3 address space layouts. 68 + ============================ 69 + 70 + Default MMUv2-compatible layout. 71 + 72 + Symbol VADDR Size 73 + +------------------+ 74 + | Userspace | 0x00000000 TASK_SIZE 75 + +------------------+ 0x40000000 76 + +------------------+ 77 + | Page table | 0x80000000 78 + +------------------+ 0x80400000 79 + +------------------+ 80 + | KMAP area | PKMAP_BASE PTRS_PER_PTE * 81 + | | DCACHE_N_COLORS * 82 + | | PAGE_SIZE 83 + | | (4MB * DCACHE_N_COLORS) 84 + +------------------+ 85 + | Atomic KMAP area | FIXADDR_START KM_TYPE_NR * 86 + | | NR_CPUS * 87 + | | DCACHE_N_COLORS * 88 + | | PAGE_SIZE 89 + +------------------+ FIXADDR_TOP 0xbffff000 90 + +------------------+ 91 + | VMALLOC area | VMALLOC_START 0xc0000000 128MB - 64KB 92 + +------------------+ VMALLOC_END 93 + | Cache aliasing | TLBTEMP_BASE_1 0xc7ff0000 DCACHE_WAY_SIZE 94 + | remap area 1 | 95 + +------------------+ 96 + | Cache aliasing | TLBTEMP_BASE_2 DCACHE_WAY_SIZE 97 + | remap area 2 | 98 + +------------------+ 99 + +------------------+ 100 + | Cached KSEG | XCHAL_KSEG_CACHED_VADDR 0xd0000000 128MB 101 + +------------------+ 102 + | Uncached KSEG | XCHAL_KSEG_BYPASS_VADDR 0xd8000000 128MB 103 + +------------------+ 104 + | Cached KIO | XCHAL_KIO_CACHED_VADDR 0xe0000000 256MB 105 + +------------------+ 106 + | Uncached KIO | XCHAL_KIO_BYPASS_VADDR 0xf0000000 256MB 107 + +------------------+ 108 + 109 + 110 + 256MB cached + 256MB uncached layout. 111 + 112 + Symbol VADDR Size 113 + +------------------+ 114 + | Userspace | 0x00000000 TASK_SIZE 115 + +------------------+ 0x40000000 116 + +------------------+ 117 + | Page table | 0x80000000 118 + +------------------+ 0x80400000 119 + +------------------+ 120 + | KMAP area | PKMAP_BASE PTRS_PER_PTE * 121 + | | DCACHE_N_COLORS * 122 + | | PAGE_SIZE 123 + | | (4MB * DCACHE_N_COLORS) 124 + +------------------+ 125 + | Atomic KMAP area | FIXADDR_START KM_TYPE_NR * 126 + | | NR_CPUS * 127 + | | DCACHE_N_COLORS * 128 + | | PAGE_SIZE 129 + +------------------+ FIXADDR_TOP 0x9ffff000 130 + +------------------+ 131 + | VMALLOC area | VMALLOC_START 0xa0000000 128MB - 64KB 132 + +------------------+ VMALLOC_END 133 + | Cache aliasing | TLBTEMP_BASE_1 0xa7ff0000 DCACHE_WAY_SIZE 134 + | remap area 1 | 135 + +------------------+ 136 + | Cache aliasing | TLBTEMP_BASE_2 DCACHE_WAY_SIZE 137 + | remap area 2 | 138 + +------------------+ 139 + +------------------+ 140 + | Cached KSEG | XCHAL_KSEG_CACHED_VADDR 0xb0000000 256MB 141 + +------------------+ 142 + | Uncached KSEG | XCHAL_KSEG_BYPASS_VADDR 0xc0000000 256MB 143 + +------------------+ 144 + +------------------+ 145 + | Cached KIO | XCHAL_KIO_CACHED_VADDR 0xe0000000 256MB 146 + +------------------+ 147 + | Uncached KIO | XCHAL_KIO_BYPASS_VADDR 0xf0000000 256MB 148 + +------------------+ 149 + 150 + 151 + 512MB cached + 512MB uncached layout. 152 + 153 + Symbol VADDR Size 154 + +------------------+ 155 + | Userspace | 0x00000000 TASK_SIZE 156 + +------------------+ 0x40000000 157 + +------------------+ 158 + | Page table | 0x80000000 159 + +------------------+ 0x80400000 160 + +------------------+ 161 + | KMAP area | PKMAP_BASE PTRS_PER_PTE * 162 + | | DCACHE_N_COLORS * 163 + | | PAGE_SIZE 164 + | | (4MB * DCACHE_N_COLORS) 165 + +------------------+ 166 + | Atomic KMAP area | FIXADDR_START KM_TYPE_NR * 167 + | | NR_CPUS * 168 + | | DCACHE_N_COLORS * 169 + | | PAGE_SIZE 170 + +------------------+ FIXADDR_TOP 0x8ffff000 171 + +------------------+ 172 + | VMALLOC area | VMALLOC_START 0x90000000 128MB - 64KB 173 + +------------------+ VMALLOC_END 174 + | Cache aliasing | TLBTEMP_BASE_1 0x97ff0000 DCACHE_WAY_SIZE 175 + | remap area 1 | 176 + +------------------+ 177 + | Cache aliasing | TLBTEMP_BASE_2 DCACHE_WAY_SIZE 178 + | remap area 2 | 179 + +------------------+ 180 + +------------------+ 181 + | Cached KSEG | XCHAL_KSEG_CACHED_VADDR 0xa0000000 512MB 182 + +------------------+ 183 + | Uncached KSEG | XCHAL_KSEG_BYPASS_VADDR 0xc0000000 512MB 184 + +------------------+ 185 + | Cached KIO | XCHAL_KIO_CACHED_VADDR 0xe0000000 256MB 186 + +------------------+ 187 + | Uncached KIO | XCHAL_KIO_BYPASS_VADDR 0xf0000000 256MB 188 + +------------------+

+74 -16

arch/xtensa/Kconfig

··· 13 13 select GENERIC_IRQ_SHOW 14 14 select GENERIC_PCI_IOMAP 15 15 select GENERIC_SCHED_CLOCK 16 + select HAVE_DEBUG_KMEMLEAK 16 17 select HAVE_DMA_API_DEBUG 17 18 select HAVE_EXIT_THREAD 18 19 select HAVE_FUNCTION_TRACER 19 20 select HAVE_FUTEX_CMPXCHG if !MMU 20 21 select HAVE_HW_BREAKPOINT if PERF_EVENTS 21 22 select HAVE_IRQ_TIME_ACCOUNTING 23 + select HAVE_MEMBLOCK 22 24 select HAVE_OPROFILE 23 25 select HAVE_PERF_EVENTS 24 26 select IRQ_DOMAIN 25 27 select MODULES_USE_ELF_RELA 28 + select NO_BOOTMEM 26 29 select PERF_USE_VMALLOC 27 30 select VIRT_TO_BUS 28 31 help ··· 239 236 240 237 If in doubt, say Y. 241 238 239 + config KSEG_PADDR 240 + hex "Physical address of the KSEG mapping" 241 + depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX && MMU 242 + default 0x00000000 243 + help 244 + This is the physical address where KSEG is mapped. Please refer to 245 + the chosen KSEG layout help for the required address alignment. 246 + Unpacked kernel image (including vectors) must be located completely 247 + within KSEG. 248 + Physical memory below this address is not available to linux. 249 + 250 + If unsure, leave the default value here. 251 + 252 + config KERNEL_LOAD_ADDRESS 253 + hex "Kernel load address" 254 + default 0x00003000 255 + help 256 + This is the address where the kernel is loaded. 257 + It is virtual address for MMUv2 configurations and physical address 258 + for all other configurations. 259 + 260 + If unsure, leave the default value here. 261 + 262 + config VECTORS_OFFSET 263 + hex "Kernel vectors offset" 264 + default 0x00003000 265 + help 266 + This is the offset of the kernel image from the relocatable vectors 267 + base. 268 + 269 + If unsure, leave the default value here. 270 + 271 + choice 272 + prompt "KSEG layout" 273 + depends on MMU 274 + default XTENSA_KSEG_MMU_V2 275 + 276 + config XTENSA_KSEG_MMU_V2 277 + bool "MMUv2: 128MB cached + 128MB uncached" 278 + help 279 + MMUv2 compatible kernel memory map: TLB way 5 maps 128MB starting 280 + at KSEG_PADDR to 0xd0000000 with cache and to 0xd8000000 281 + without cache. 282 + KSEG_PADDR must be aligned to 128MB. 283 + 284 + config XTENSA_KSEG_256M 285 + bool "256MB cached + 256MB uncached" 286 + depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX 287 + help 288 + TLB way 6 maps 256MB starting at KSEG_PADDR to 0xb0000000 289 + with cache and to 0xc0000000 without cache. 290 + KSEG_PADDR must be aligned to 256MB. 291 + 292 + config XTENSA_KSEG_512M 293 + bool "512MB cached + 512MB uncached" 294 + depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX 295 + help 296 + TLB way 6 maps 512MB starting at KSEG_PADDR to 0xa0000000 297 + with cache and to 0xc0000000 without cache. 298 + KSEG_PADDR must be aligned to 256MB. 299 + 300 + endchoice 301 + 242 302 config HIGHMEM 243 303 bool "High Memory Support" 244 304 depends on MMU ··· 397 331 config XTENSA_PLATFORM_XTFPGA 398 332 bool "XTFPGA" 399 333 select ETHOC if ETHERNET 400 - select PLATFORM_WANT_DEFAULT_MEM 334 + select PLATFORM_WANT_DEFAULT_MEM if !MMU 401 335 select SERIAL_CONSOLE 402 336 select XTENSA_CALIBRATE_CCOUNT 403 337 help ··· 435 369 bool "Flattened Device Tree support" 436 370 select OF 437 371 select OF_EARLY_FLATTREE 372 + select OF_RESERVED_MEM 438 373 help 439 374 Include support for flattened device tree machine descriptions. 440 375 ··· 506 439 default 0x00000000 if MMU 507 440 default 0x60000000 if !MMU 508 441 help 509 - This is a fallback start address of the default memory area, it is 510 - used when no physical memory size is passed through DTB or through 511 - boot parameter from bootloader. 512 - 513 - In noMMU configuration the following parameters are derived from it: 514 - - kernel load address; 515 - - kernel entry point address; 516 - - relocatable vectors base address; 517 - - uBoot load address; 518 - - TASK_SIZE. 442 + This is the base address of the default memory area. 443 + Default memory area has platform-specific meaning, it may be used 444 + for e.g. early cache initialization. 519 445 520 446 If unsure, leave the default value here. 521 447 ··· 517 457 depends on PLATFORM_WANT_DEFAULT_MEM 518 458 default 0x04000000 519 459 help 520 - This is a fallback size of the default memory area, it is used when 521 - no physical memory size is passed through DTB or through boot 522 - parameter from bootloader. 523 - 524 - It's also used for TASK_SIZE calculation in noMMU configuration. 460 + This is the size of the default memory area. 461 + Default memory area has platform-specific meaning, it may be used 462 + for e.g. early cache initialization. 525 463 526 464 If unsure, leave the default value here. 527 465

+1 -1

arch/xtensa/boot/boot-elf/boot.lds.S

··· 23 23 *(.ResetVector.text) 24 24 } 25 25 26 - .image KERNELOFFSET: AT (LOAD_MEMORY_ADDRESS) 26 + .image KERNELOFFSET: AT (CONFIG_KERNEL_LOAD_ADDRESS) 27 27 { 28 28 _image_start = .; 29 29 *(image)

+6 -1

arch/xtensa/boot/boot-elf/bootstrap.S

··· 35 35 36 36 .align 4 37 37 RomInitAddr: 38 - .word LOAD_MEMORY_ADDRESS 38 + #if defined(CONFIG_INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX) && \ 39 + XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY 40 + .word CONFIG_KERNEL_LOAD_ADDRESS 41 + #else 42 + .word KERNELOFFSET 43 + #endif 39 44 RomBootParam: 40 45 .word _bootparam 41 46 _bootparam:

+1 -9

arch/xtensa/boot/boot-uboot/Makefile

··· 4 4 # for more details. 5 5 # 6 6 7 - ifdef CONFIG_MMU 8 - ifdef CONFIG_INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX 9 - UIMAGE_LOADADDR = 0x00003000 10 - else 11 - UIMAGE_LOADADDR = 0xd0003000 12 - endif 13 - else 14 - UIMAGE_LOADADDR = $(shell printf "0x%x" $$(( ${CONFIG_DEFAULT_MEM_START} + 0x3000 )) ) 15 - endif 7 + UIMAGE_LOADADDR = $(CONFIG_KERNEL_LOAD_ADDRESS) 16 8 UIMAGE_COMPRESSION = gzip 17 9 18 10 $(obj)/../uImage: vmlinux.bin.gz FORCE

+1 -1

arch/xtensa/include/asm/bitops.h

··· 48 48 * __ffs: Find first bit set in word. Return 0 for bit 0 49 49 */ 50 50 51 - static inline int __ffs(unsigned long x) 51 + static inline unsigned long __ffs(unsigned long x) 52 52 { 53 53 return 31 - __cntlz(x & -x); 54 54 }

+4 -7

arch/xtensa/include/asm/cacheasm.h

··· 69 69 .endm 70 70 71 71 72 - #if XCHAL_DCACHE_LINE_LOCKABLE 73 - 74 72 .macro ___unlock_dcache_all ar at 75 73 76 - #if XCHAL_DCACHE_SIZE 74 + #if XCHAL_DCACHE_LINE_LOCKABLE && XCHAL_DCACHE_SIZE 77 75 __loop_cache_all \ar \at diu XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH 78 76 #endif 79 77 80 78 .endm 81 79 82 - #endif 83 - 84 - #if XCHAL_ICACHE_LINE_LOCKABLE 85 80 86 81 .macro ___unlock_icache_all ar at 87 82 83 + #if XCHAL_ICACHE_LINE_LOCKABLE && XCHAL_ICACHE_SIZE 88 84 __loop_cache_all \ar \at iiu XCHAL_ICACHE_SIZE XCHAL_ICACHE_LINEWIDTH 85 + #endif 89 86 90 87 .endm 91 - #endif 88 + 92 89 93 90 .macro ___flush_invalidate_dcache_all ar at 94 91

+5

arch/xtensa/include/asm/fixmap.h

··· 59 59 */ 60 60 static __always_inline unsigned long fix_to_virt(const unsigned int idx) 61 61 { 62 + /* Check if this memory layout is broken because fixmap overlaps page 63 + * table. 64 + */ 65 + BUILD_BUG_ON(FIXADDR_START < 66 + XCHAL_PAGE_TABLE_VADDR + XCHAL_PAGE_TABLE_SIZE); 62 67 BUILD_BUG_ON(idx >= __end_of_fixed_addresses); 63 68 return __fix_to_virt(idx); 64 69 }

+5

arch/xtensa/include/asm/highmem.h

··· 68 68 69 69 static inline void *kmap(struct page *page) 70 70 { 71 + /* Check if this memory layout is broken because PKMAP overlaps 72 + * page table. 73 + */ 74 + BUILD_BUG_ON(PKMAP_BASE < 75 + XCHAL_PAGE_TABLE_VADDR + XCHAL_PAGE_TABLE_SIZE); 71 76 BUG_ON(in_interrupt()); 72 77 if (!PageHighMem(page)) 73 78 return page_address(page);

+30 -14

arch/xtensa/include/asm/initialize_mmu.h

··· 77 77 78 78 .align 4 79 79 1: movi a2, 0x10000000 80 - movi a3, 0x18000000 81 - add a2, a2, a0 82 - 9: bgeu a2, a3, 9b /* PC is out of the expected range */ 80 + 81 + #if CONFIG_KERNEL_LOAD_ADDRESS < 0x40000000ul 82 + #define TEMP_MAPPING_VADDR 0x40000000 83 + #else 84 + #define TEMP_MAPPING_VADDR 0x00000000 85 + #endif 83 86 84 87 /* Step 1: invalidate mapping at 0x40000000..0x5FFFFFFF. */ 85 88 86 - movi a2, 0x40000000 | XCHAL_SPANNING_WAY 89 + movi a2, TEMP_MAPPING_VADDR | XCHAL_SPANNING_WAY 87 90 idtlb a2 88 91 iitlb a2 89 92 isync ··· 98 95 srli a3, a0, 27 99 96 slli a3, a3, 27 100 97 addi a3, a3, CA_BYPASS 101 - addi a7, a2, -1 98 + addi a7, a2, 5 - XCHAL_SPANNING_WAY 102 99 wdtlb a3, a7 103 100 witlb a3, a7 104 101 isync 105 102 106 103 slli a4, a0, 5 107 104 srli a4, a4, 5 108 - addi a5, a2, -6 105 + addi a5, a2, -XCHAL_SPANNING_WAY 109 106 add a4, a4, a5 110 107 jx a4 111 108 ··· 119 116 add a5, a5, a4 120 117 bne a5, a2, 3b 121 118 122 - /* Step 4: Setup MMU with the old V2 mappings. */ 119 + /* Step 4: Setup MMU with the requested static mappings. */ 120 + 123 121 movi a6, 0x01000000 124 122 wsr a6, ITLBCFG 125 123 wsr a6, DTLBCFG 126 124 isync 127 125 128 - movi a5, 0xd0000005 129 - movi a4, CA_WRITEBACK 126 + movi a5, XCHAL_KSEG_CACHED_VADDR + XCHAL_KSEG_TLB_WAY 127 + movi a4, XCHAL_KSEG_PADDR + CA_WRITEBACK 130 128 wdtlb a4, a5 131 129 witlb a4, a5 132 130 133 - movi a5, 0xd8000005 134 - movi a4, CA_BYPASS 131 + movi a5, XCHAL_KSEG_BYPASS_VADDR + XCHAL_KSEG_TLB_WAY 132 + movi a4, XCHAL_KSEG_PADDR + CA_BYPASS 135 133 wdtlb a4, a5 136 134 witlb a4, a5 137 135 138 - movi a5, XCHAL_KIO_CACHED_VADDR + 6 136 + #ifdef CONFIG_XTENSA_KSEG_512M 137 + movi a5, XCHAL_KSEG_CACHED_VADDR + 0x10000000 + XCHAL_KSEG_TLB_WAY 138 + movi a4, XCHAL_KSEG_PADDR + 0x10000000 + CA_WRITEBACK 139 + wdtlb a4, a5 140 + witlb a4, a5 141 + 142 + movi a5, XCHAL_KSEG_BYPASS_VADDR + 0x10000000 + XCHAL_KSEG_TLB_WAY 143 + movi a4, XCHAL_KSEG_PADDR + 0x10000000 + CA_BYPASS 144 + wdtlb a4, a5 145 + witlb a4, a5 146 + #endif 147 + 148 + movi a5, XCHAL_KIO_CACHED_VADDR + XCHAL_KIO_TLB_WAY 139 149 movi a4, XCHAL_KIO_DEFAULT_PADDR + CA_WRITEBACK 140 150 wdtlb a4, a5 141 151 witlb a4, a5 142 152 143 - movi a5, XCHAL_KIO_BYPASS_VADDR + 6 153 + movi a5, XCHAL_KIO_BYPASS_VADDR + XCHAL_KIO_TLB_WAY 144 154 movi a4, XCHAL_KIO_DEFAULT_PADDR + CA_BYPASS 145 155 wdtlb a4, a5 146 156 witlb a4, a5 147 157 148 158 isync 149 159 150 - /* Jump to self, using MMU v2 mappings. */ 160 + /* Jump to self, using final mappings. */ 151 161 movi a4, 1f 152 162 jx a4 153 163

+74

arch/xtensa/include/asm/kmem_layout.h

··· 1 + /* 2 + * Kernel virtual memory layout definitions. 3 + * 4 + * This file is subject to the terms and conditions of the GNU General 5 + * Public License. See the file "COPYING" in the main directory of 6 + * this archive for more details. 7 + * 8 + * Copyright (C) 2016 Cadence Design Systems Inc. 9 + */ 10 + 11 + #ifndef _XTENSA_KMEM_LAYOUT_H 12 + #define _XTENSA_KMEM_LAYOUT_H 13 + 14 + #include <asm/types.h> 15 + 16 + #ifdef CONFIG_MMU 17 + 18 + /* 19 + * Fixed TLB translations in the processor. 20 + */ 21 + 22 + #define XCHAL_PAGE_TABLE_VADDR __XTENSA_UL_CONST(0x80000000) 23 + #define XCHAL_PAGE_TABLE_SIZE __XTENSA_UL_CONST(0x00400000) 24 + 25 + #if defined(CONFIG_XTENSA_KSEG_MMU_V2) 26 + 27 + #define XCHAL_KSEG_CACHED_VADDR __XTENSA_UL_CONST(0xd0000000) 28 + #define XCHAL_KSEG_BYPASS_VADDR __XTENSA_UL_CONST(0xd8000000) 29 + #define XCHAL_KSEG_SIZE __XTENSA_UL_CONST(0x08000000) 30 + #define XCHAL_KSEG_ALIGNMENT __XTENSA_UL_CONST(0x08000000) 31 + #define XCHAL_KSEG_TLB_WAY 5 32 + #define XCHAL_KIO_TLB_WAY 6 33 + 34 + #elif defined(CONFIG_XTENSA_KSEG_256M) 35 + 36 + #define XCHAL_KSEG_CACHED_VADDR __XTENSA_UL_CONST(0xb0000000) 37 + #define XCHAL_KSEG_BYPASS_VADDR __XTENSA_UL_CONST(0xc0000000) 38 + #define XCHAL_KSEG_SIZE __XTENSA_UL_CONST(0x10000000) 39 + #define XCHAL_KSEG_ALIGNMENT __XTENSA_UL_CONST(0x10000000) 40 + #define XCHAL_KSEG_TLB_WAY 6 41 + #define XCHAL_KIO_TLB_WAY 6 42 + 43 + #elif defined(CONFIG_XTENSA_KSEG_512M) 44 + 45 + #define XCHAL_KSEG_CACHED_VADDR __XTENSA_UL_CONST(0xa0000000) 46 + #define XCHAL_KSEG_BYPASS_VADDR __XTENSA_UL_CONST(0xc0000000) 47 + #define XCHAL_KSEG_SIZE __XTENSA_UL_CONST(0x20000000) 48 + #define XCHAL_KSEG_ALIGNMENT __XTENSA_UL_CONST(0x10000000) 49 + #define XCHAL_KSEG_TLB_WAY 6 50 + #define XCHAL_KIO_TLB_WAY 6 51 + 52 + #else 53 + #error Unsupported KSEG configuration 54 + #endif 55 + 56 + #ifdef CONFIG_KSEG_PADDR 57 + #define XCHAL_KSEG_PADDR __XTENSA_UL_CONST(CONFIG_KSEG_PADDR) 58 + #else 59 + #define XCHAL_KSEG_PADDR __XTENSA_UL_CONST(0x00000000) 60 + #endif 61 + 62 + #if XCHAL_KSEG_PADDR & (XCHAL_KSEG_ALIGNMENT - 1) 63 + #error XCHAL_KSEG_PADDR is not properly aligned to XCHAL_KSEG_ALIGNMENT 64 + #endif 65 + 66 + #else 67 + 68 + #define XCHAL_KSEG_CACHED_VADDR __XTENSA_UL_CONST(0xd0000000) 69 + #define XCHAL_KSEG_BYPASS_VADDR __XTENSA_UL_CONST(0xd8000000) 70 + #define XCHAL_KSEG_SIZE __XTENSA_UL_CONST(0x08000000) 71 + 72 + #endif 73 + 74 + #endif

+12 -15

arch/xtensa/include/asm/page.h

··· 15 15 #include <asm/types.h> 16 16 #include <asm/cache.h> 17 17 #include <platform/hardware.h> 18 - 19 - /* 20 - * Fixed TLB translations in the processor. 21 - */ 22 - 23 - #define XCHAL_KSEG_CACHED_VADDR __XTENSA_UL_CONST(0xd0000000) 24 - #define XCHAL_KSEG_BYPASS_VADDR __XTENSA_UL_CONST(0xd8000000) 25 - #define XCHAL_KSEG_PADDR __XTENSA_UL_CONST(0x00000000) 26 - #define XCHAL_KSEG_SIZE __XTENSA_UL_CONST(0x08000000) 18 + #include <asm/kmem_layout.h> 27 19 28 20 /* 29 21 * PAGE_SHIFT determines the page size ··· 27 35 28 36 #ifdef CONFIG_MMU 29 37 #define PAGE_OFFSET XCHAL_KSEG_CACHED_VADDR 30 - #define MAX_MEM_PFN XCHAL_KSEG_SIZE 38 + #define PHYS_OFFSET XCHAL_KSEG_PADDR 39 + #define MAX_LOW_PFN (PHYS_PFN(XCHAL_KSEG_PADDR) + \ 40 + PHYS_PFN(XCHAL_KSEG_SIZE)) 31 41 #else 32 - #define PAGE_OFFSET __XTENSA_UL_CONST(0) 33 - #define MAX_MEM_PFN (PLATFORM_DEFAULT_MEM_START + PLATFORM_DEFAULT_MEM_SIZE) 42 + #define PAGE_OFFSET PLATFORM_DEFAULT_MEM_START 43 + #define PHYS_OFFSET PLATFORM_DEFAULT_MEM_START 44 + #define MAX_LOW_PFN PHYS_PFN(0xfffffffful) 34 45 #endif 35 46 36 47 #define PGTABLE_START 0x80000000 ··· 162 167 * addresses. 163 168 */ 164 169 165 - #define ARCH_PFN_OFFSET (PLATFORM_DEFAULT_MEM_START >> PAGE_SHIFT) 170 + #define ARCH_PFN_OFFSET (PHYS_OFFSET >> PAGE_SHIFT) 166 171 167 - #define __pa(x) ((unsigned long) (x) - PAGE_OFFSET) 168 - #define __va(x) ((void *)((unsigned long) (x) + PAGE_OFFSET)) 172 + #define __pa(x) \ 173 + ((unsigned long) (x) - PAGE_OFFSET + PHYS_OFFSET) 174 + #define __va(x) \ 175 + ((void *)((unsigned long) (x) - PHYS_OFFSET + PAGE_OFFSET)) 169 176 #define pfn_valid(pfn) \ 170 177 ((pfn) >= ARCH_PFN_OFFSET && ((pfn) - ARCH_PFN_OFFSET) < max_mapnr) 171 178

+4 -3

arch/xtensa/include/asm/pgtable.h

··· 13 13 14 14 #include <asm-generic/pgtable-nopmd.h> 15 15 #include <asm/page.h> 16 + #include <asm/kmem_layout.h> 16 17 17 18 /* 18 19 * We only use two ring levels, user and kernel space. ··· 69 68 * Virtual memory area. We keep a distance to other memory regions to be 70 69 * on the safe side. We also use this area for cache aliasing. 71 70 */ 72 - #define VMALLOC_START 0xC0000000 73 - #define VMALLOC_END 0xC7FEFFFF 74 - #define TLBTEMP_BASE_1 0xC7FF0000 71 + #define VMALLOC_START (XCHAL_KSEG_CACHED_VADDR - 0x10000000) 72 + #define VMALLOC_END (VMALLOC_START + 0x07FEFFFF) 73 + #define TLBTEMP_BASE_1 (VMALLOC_END + 1) 75 74 #define TLBTEMP_BASE_2 (TLBTEMP_BASE_1 + DCACHE_WAY_SIZE) 76 75 #if 2 * DCACHE_WAY_SIZE > ICACHE_WAY_SIZE 77 76 #define TLBTEMP_SIZE (2 * DCACHE_WAY_SIZE)

+1 -1

arch/xtensa/include/asm/processor.h

··· 37 37 #ifdef CONFIG_MMU 38 38 #define TASK_SIZE __XTENSA_UL_CONST(0x40000000) 39 39 #else 40 - #define TASK_SIZE (PLATFORM_DEFAULT_MEM_START + PLATFORM_DEFAULT_MEM_SIZE) 40 + #define TASK_SIZE __XTENSA_UL_CONST(0xffffffff) 41 41 #endif 42 42 43 43 #define STACK_TOP TASK_SIZE

+1 -20

arch/xtensa/include/asm/sysmem.h

··· 11 11 #ifndef _XTENSA_SYSMEM_H 12 12 #define _XTENSA_SYSMEM_H 13 13 14 - #define SYSMEM_BANKS_MAX 31 14 + #include <linux/memblock.h> 15 15 16 - struct meminfo { 17 - unsigned long start; 18 - unsigned long end; 19 - }; 20 - 21 - /* 22 - * Bank array is sorted by .start. 23 - * Banks don't overlap and there's at least one page gap 24 - * between adjacent bank entries. 25 - */ 26 - struct sysmem_info { 27 - int nr_banks; 28 - struct meminfo bank[SYSMEM_BANKS_MAX]; 29 - }; 30 - 31 - extern struct sysmem_info sysmem; 32 - 33 - int add_sysmem_bank(unsigned long start, unsigned long end); 34 - int mem_reserve(unsigned long, unsigned long, int); 35 16 void bootmem_init(void); 36 17 void zones_init(void); 37 18

+24 -43

arch/xtensa/include/asm/vectors.h

··· 20 20 21 21 #include <variant/core.h> 22 22 #include <platform/hardware.h> 23 + #include <asm/kmem_layout.h> 23 24 24 25 #if XCHAL_HAVE_PTP_MMU 25 26 #define XCHAL_KIO_CACHED_VADDR 0xe0000000 ··· 48 47 49 48 #if defined(CONFIG_MMU) 50 49 51 - /* Will Become VECBASE */ 52 - #define VIRTUAL_MEMORY_ADDRESS 0xD0000000 53 - 50 + #if XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY 54 51 /* Image Virtual Start Address */ 55 - #define KERNELOFFSET 0xD0003000 56 - 57 - #if defined(XCHAL_HAVE_PTP_MMU) && XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY 58 - /* MMU v3 - XCHAL_HAVE_PTP_MMU == 1 */ 59 - #define LOAD_MEMORY_ADDRESS 0x00003000 52 + #define KERNELOFFSET (XCHAL_KSEG_CACHED_VADDR + \ 53 + CONFIG_KERNEL_LOAD_ADDRESS - \ 54 + XCHAL_KSEG_PADDR) 60 55 #else 61 - /* MMU V2 - XCHAL_HAVE_PTP_MMU == 0 */ 62 - #define LOAD_MEMORY_ADDRESS 0xD0003000 56 + #define KERNELOFFSET CONFIG_KERNEL_LOAD_ADDRESS 63 57 #endif 64 - 65 - #define RESET_VECTOR1_VADDR (VIRTUAL_MEMORY_ADDRESS + \ 66 - XCHAL_RESET_VECTOR1_PADDR) 67 58 68 59 #else /* !defined(CONFIG_MMU) */ 69 60 /* MMU Not being used - Virtual == Physical */ 70 61 71 - /* VECBASE */ 72 - #define VIRTUAL_MEMORY_ADDRESS (PLATFORM_DEFAULT_MEM_START + 0x2000) 62 + /* Location of the start of the kernel text, _start */ 63 + #define KERNELOFFSET CONFIG_KERNEL_LOAD_ADDRESS 73 64 74 - /* Location of the start of the kernel text, _start */ 75 - #define KERNELOFFSET (PLATFORM_DEFAULT_MEM_START + 0x3000) 76 - 77 - /* Loaded just above possibly live vectors */ 78 - #define LOAD_MEMORY_ADDRESS (PLATFORM_DEFAULT_MEM_START + 0x3000) 79 - 80 - #define RESET_VECTOR1_VADDR (XCHAL_RESET_VECTOR1_VADDR) 81 65 82 66 #endif /* CONFIG_MMU */ 83 67 84 - #define XC_VADDR(offset) (VIRTUAL_MEMORY_ADDRESS + offset) 85 - 86 - /* Used to set VECBASE register */ 87 - #define VECBASE_RESET_VADDR VIRTUAL_MEMORY_ADDRESS 68 + #define RESET_VECTOR1_VADDR (XCHAL_RESET_VECTOR1_VADDR) 69 + #define VECBASE_VADDR (KERNELOFFSET - CONFIG_VECTORS_OFFSET) 88 70 89 71 #if defined(XCHAL_HAVE_VECBASE) && XCHAL_HAVE_VECBASE 90 72 91 - #define USER_VECTOR_VADDR XC_VADDR(XCHAL_USER_VECOFS) 92 - #define KERNEL_VECTOR_VADDR XC_VADDR(XCHAL_KERNEL_VECOFS) 93 - #define DOUBLEEXC_VECTOR_VADDR XC_VADDR(XCHAL_DOUBLEEXC_VECOFS) 94 - #define WINDOW_VECTORS_VADDR XC_VADDR(XCHAL_WINDOW_OF4_VECOFS) 95 - #define INTLEVEL2_VECTOR_VADDR XC_VADDR(XCHAL_INTLEVEL2_VECOFS) 96 - #define INTLEVEL3_VECTOR_VADDR XC_VADDR(XCHAL_INTLEVEL3_VECOFS) 97 - #define INTLEVEL4_VECTOR_VADDR XC_VADDR(XCHAL_INTLEVEL4_VECOFS) 98 - #define INTLEVEL5_VECTOR_VADDR XC_VADDR(XCHAL_INTLEVEL5_VECOFS) 99 - #define INTLEVEL6_VECTOR_VADDR XC_VADDR(XCHAL_INTLEVEL6_VECOFS) 73 + #define VECTOR_VADDR(offset) (VECBASE_VADDR + offset) 100 74 101 - #define DEBUG_VECTOR_VADDR XC_VADDR(XCHAL_DEBUG_VECOFS) 102 - 103 - #define NMI_VECTOR_VADDR XC_VADDR(XCHAL_NMI_VECOFS) 104 - 105 - #define INTLEVEL7_VECTOR_VADDR XC_VADDR(XCHAL_INTLEVEL7_VECOFS) 75 + #define USER_VECTOR_VADDR VECTOR_VADDR(XCHAL_USER_VECOFS) 76 + #define KERNEL_VECTOR_VADDR VECTOR_VADDR(XCHAL_KERNEL_VECOFS) 77 + #define DOUBLEEXC_VECTOR_VADDR VECTOR_VADDR(XCHAL_DOUBLEEXC_VECOFS) 78 + #define WINDOW_VECTORS_VADDR VECTOR_VADDR(XCHAL_WINDOW_OF4_VECOFS) 79 + #define INTLEVEL2_VECTOR_VADDR VECTOR_VADDR(XCHAL_INTLEVEL2_VECOFS) 80 + #define INTLEVEL3_VECTOR_VADDR VECTOR_VADDR(XCHAL_INTLEVEL3_VECOFS) 81 + #define INTLEVEL4_VECTOR_VADDR VECTOR_VADDR(XCHAL_INTLEVEL4_VECOFS) 82 + #define INTLEVEL5_VECTOR_VADDR VECTOR_VADDR(XCHAL_INTLEVEL5_VECOFS) 83 + #define INTLEVEL6_VECTOR_VADDR VECTOR_VADDR(XCHAL_INTLEVEL6_VECOFS) 84 + #define INTLEVEL7_VECTOR_VADDR VECTOR_VADDR(XCHAL_INTLEVEL7_VECOFS) 85 + #define DEBUG_VECTOR_VADDR VECTOR_VADDR(XCHAL_DEBUG_VECOFS) 106 86 107 87 /* 108 88 * These XCHAL_* #defines from varian/core.h ··· 91 109 * constants are defined above and should be used. 92 110 */ 93 111 #undef XCHAL_VECBASE_RESET_VADDR 94 - #undef XCHAL_RESET_VECTOR0_VADDR 95 112 #undef XCHAL_USER_VECTOR_VADDR 96 113 #undef XCHAL_KERNEL_VECTOR_VADDR 97 114 #undef XCHAL_DOUBLEEXC_VECTOR_VADDR ··· 100 119 #undef XCHAL_INTLEVEL4_VECTOR_VADDR 101 120 #undef XCHAL_INTLEVEL5_VECTOR_VADDR 102 121 #undef XCHAL_INTLEVEL6_VECTOR_VADDR 103 - #undef XCHAL_DEBUG_VECTOR_VADDR 104 - #undef XCHAL_NMI_VECTOR_VADDR 105 122 #undef XCHAL_INTLEVEL7_VECTOR_VADDR 123 + #undef XCHAL_DEBUG_VECTOR_VADDR 106 124 107 125 #else 108 126 ··· 114 134 #define INTLEVEL4_VECTOR_VADDR XCHAL_INTLEVEL4_VECTOR_VADDR 115 135 #define INTLEVEL5_VECTOR_VADDR XCHAL_INTLEVEL5_VECTOR_VADDR 116 136 #define INTLEVEL6_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR 137 + #define INTLEVEL7_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR 117 138 #define DEBUG_VECTOR_VADDR XCHAL_DEBUG_VECTOR_VADDR 118 139 119 140 #endif

+2 -1

arch/xtensa/include/uapi/asm/types.h

··· 18 18 # define __XTENSA_UL_CONST(x) x 19 19 #else 20 20 # define __XTENSA_UL(x) ((unsigned long)(x)) 21 - # define __XTENSA_UL_CONST(x) x##UL 21 + # define ___XTENSA_UL_CONST(x) x##UL 22 + # define __XTENSA_UL_CONST(x) ___XTENSA_UL_CONST(x) 22 23 #endif 23 24 24 25 #ifndef __ASSEMBLY__

+14 -1

arch/xtensa/include/uapi/asm/unistd.h

··· 754 754 #define __NR_execveat 341 755 755 __SYSCALL(341, sys_execveat, 5) 756 756 757 - #define __NR_syscall_count 342 757 + #define __NR_userfaultfd 342 758 + __SYSCALL(342, sys_userfaultfd, 1) 759 + #define __NR_membarrier 343 760 + __SYSCALL(343, sys_membarrier, 2) 761 + #define __NR_mlock2 344 762 + __SYSCALL(344, sys_mlock2, 3) 763 + #define __NR_copy_file_range 345 764 + __SYSCALL(345, sys_copy_file_range, 6) 765 + #define __NR_preadv2 346 766 + __SYSCALL(346, sys_preadv2, 6) 767 + #define __NR_pwritev2 347 768 + __SYSCALL(347, sys_pwritev2, 6) 769 + 770 + #define __NR_syscall_count 348 758 771 759 772 /* 760 773 * sysxtensa syscall handler

+3 -2

arch/xtensa/kernel/entry.S

··· 1632 1632 * The messy computation for 'pteval' above really simplifies 1633 1633 * into the following: 1634 1634 * 1635 - * pteval = ((pmdval - PAGE_OFFSET) & PAGE_MASK) | PAGE_DIRECTORY 1635 + * pteval = ((pmdval - PAGE_OFFSET + PHYS_OFFSET) & PAGE_MASK) 1636 + * | PAGE_DIRECTORY 1636 1637 */ 1637 1638 1638 - movi a1, (-PAGE_OFFSET) & 0xffffffff 1639 + movi a1, (PHYS_OFFSET - PAGE_OFFSET) & 0xffffffff 1639 1640 add a0, a0, a1 # pmdval - PAGE_OFFSET 1640 1641 extui a1, a0, 0, PAGE_SHIFT # ... & PAGE_MASK 1641 1642 xor a0, a0, a1

+1 -1

arch/xtensa/kernel/head.S

··· 113 113 movi a0, 0 114 114 115 115 #if XCHAL_HAVE_VECBASE 116 - movi a2, VECBASE_RESET_VADDR 116 + movi a2, VECBASE_VADDR 117 117 wsr a2, vecbase 118 118 #endif 119 119

+21 -28

arch/xtensa/kernel/setup.c

··· 7 7 * 8 8 * Copyright (C) 1995 Linus Torvalds 9 9 * Copyright (C) 2001 - 2005 Tensilica Inc. 10 + * Copyright (C) 2014 - 2016 Cadence Design Systems Inc. 10 11 * 11 12 * Chris Zankel <chris@zankel.net> 12 13 * Joe Taylor <joe@tensilica.com, joetylr@yahoo.com> ··· 25 24 #include <linux/percpu.h> 26 25 #include <linux/clk-provider.h> 27 26 #include <linux/cpu.h> 27 + #include <linux/of.h> 28 28 #include <linux/of_fdt.h> 29 29 #include <linux/of_platform.h> 30 30 ··· 116 114 if (mi->type != MEMORY_TYPE_CONVENTIONAL) 117 115 return -1; 118 116 119 - return add_sysmem_bank(mi->start, mi->end); 117 + return memblock_add(mi->start, mi->end - mi->start); 120 118 } 121 119 122 120 __tagtable(BP_TAG_MEMORY, parse_tag_mem); ··· 190 188 } 191 189 192 190 #ifdef CONFIG_OF 193 - bool __initdata dt_memory_scan = false; 194 191 195 192 #if !XCHAL_HAVE_PTP_MMU || XCHAL_HAVE_SPANNING_WAY 196 193 unsigned long xtensa_kio_paddr = XCHAL_KIO_DEFAULT_PADDR; ··· 229 228 230 229 void __init early_init_dt_add_memory_arch(u64 base, u64 size) 231 230 { 232 - if (!dt_memory_scan) 233 - return; 234 - 235 231 size &= PAGE_MASK; 236 - add_sysmem_bank(base, base + size); 232 + memblock_add(base, size); 237 233 } 238 234 239 235 void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align) ··· 240 242 241 243 void __init early_init_devtree(void *params) 242 244 { 243 - if (sysmem.nr_banks == 0) 244 - dt_memory_scan = true; 245 - 246 245 early_init_dt_scan(params); 247 246 of_scan_flat_dt(xtensa_dt_io_area, NULL); 248 247 ··· 272 277 #ifdef CONFIG_OF 273 278 early_init_devtree(dtb_start); 274 279 #endif 275 - 276 - if (sysmem.nr_banks == 0) { 277 - add_sysmem_bank(PLATFORM_DEFAULT_MEM_START, 278 - PLATFORM_DEFAULT_MEM_START + 279 - PLATFORM_DEFAULT_MEM_SIZE); 280 - } 281 280 282 281 #ifdef CONFIG_CMDLINE_BOOL 283 282 if (!command_line[0]) ··· 442 453 early_initcall(check_s32c1i); 443 454 #endif /* CONFIG_S32C1I_SELFTEST */ 444 455 456 + static inline int mem_reserve(unsigned long start, unsigned long end) 457 + { 458 + return memblock_reserve(start, end - start); 459 + } 445 460 446 461 void __init setup_arch(char **cmdline_p) 447 462 { ··· 457 464 #ifdef CONFIG_BLK_DEV_INITRD 458 465 if (initrd_start < initrd_end) { 459 466 initrd_is_mapped = mem_reserve(__pa(initrd_start), 460 - __pa(initrd_end), 0) == 0; 467 + __pa(initrd_end)) == 0; 461 468 initrd_below_start_ok = 1; 462 469 } else { 463 470 initrd_start = 0; 464 471 } 465 472 #endif 466 473 467 - mem_reserve(__pa(&_stext),__pa(&_end), 1); 474 + mem_reserve(__pa(&_stext), __pa(&_end)); 468 475 469 476 mem_reserve(__pa(&_WindowVectors_text_start), 470 - __pa(&_WindowVectors_text_end), 0); 477 + __pa(&_WindowVectors_text_end)); 471 478 472 479 mem_reserve(__pa(&_DebugInterruptVector_literal_start), 473 - __pa(&_DebugInterruptVector_text_end), 0); 480 + __pa(&_DebugInterruptVector_text_end)); 474 481 475 482 mem_reserve(__pa(&_KernelExceptionVector_literal_start), 476 - __pa(&_KernelExceptionVector_text_end), 0); 483 + __pa(&_KernelExceptionVector_text_end)); 477 484 478 485 mem_reserve(__pa(&_UserExceptionVector_literal_start), 479 - __pa(&_UserExceptionVector_text_end), 0); 486 + __pa(&_UserExceptionVector_text_end)); 480 487 481 488 mem_reserve(__pa(&_DoubleExceptionVector_literal_start), 482 - __pa(&_DoubleExceptionVector_text_end), 0); 489 + __pa(&_DoubleExceptionVector_text_end)); 483 490 484 491 #if XCHAL_EXCM_LEVEL >= 2 485 492 mem_reserve(__pa(&_Level2InterruptVector_text_start), 486 - __pa(&_Level2InterruptVector_text_end), 0); 493 + __pa(&_Level2InterruptVector_text_end)); 487 494 #endif 488 495 #if XCHAL_EXCM_LEVEL >= 3 489 496 mem_reserve(__pa(&_Level3InterruptVector_text_start), 490 - __pa(&_Level3InterruptVector_text_end), 0); 497 + __pa(&_Level3InterruptVector_text_end)); 491 498 #endif 492 499 #if XCHAL_EXCM_LEVEL >= 4 493 500 mem_reserve(__pa(&_Level4InterruptVector_text_start), 494 - __pa(&_Level4InterruptVector_text_end), 0); 501 + __pa(&_Level4InterruptVector_text_end)); 495 502 #endif 496 503 #if XCHAL_EXCM_LEVEL >= 5 497 504 mem_reserve(__pa(&_Level5InterruptVector_text_start), 498 - __pa(&_Level5InterruptVector_text_end), 0); 505 + __pa(&_Level5InterruptVector_text_end)); 499 506 #endif 500 507 #if XCHAL_EXCM_LEVEL >= 6 501 508 mem_reserve(__pa(&_Level6InterruptVector_text_start), 502 - __pa(&_Level6InterruptVector_text_end), 0); 509 + __pa(&_Level6InterruptVector_text_end)); 503 510 #endif 504 511 505 512 #ifdef CONFIG_SMP 506 513 mem_reserve(__pa(&_SecondaryResetVector_text_start), 507 - __pa(&_SecondaryResetVector_text_end), 0); 514 + __pa(&_SecondaryResetVector_text_end)); 508 515 #endif 509 516 parse_early_param(); 510 517 bootmem_init();

-4

arch/xtensa/kernel/vmlinux.lds.S

··· 30 30 jiffies = jiffies_64; 31 31 #endif 32 32 33 - #ifndef KERNELOFFSET 34 - #define KERNELOFFSET 0xd0003000 35 - #endif 36 - 37 33 /* Note: In the following macros, it would be nice to specify only the 38 34 vector name and section kind and construct "sym" and "section" using 39 35 CPP concatenation, but that does not work reliably. Concatenating a

+19 -260

arch/xtensa/mm/init.c

··· 8 8 * for more details. 9 9 * 10 10 * Copyright (C) 2001 - 2005 Tensilica Inc. 11 - * Copyright (C) 2014 Cadence Design Systems Inc. 11 + * Copyright (C) 2014 - 2016 Cadence Design Systems Inc. 12 12 * 13 13 * Chris Zankel <chris@zankel.net> 14 14 * Joe Taylor <joe@tensilica.com, joetylr@yahoo.com> ··· 25 25 #include <linux/mman.h> 26 26 #include <linux/nodemask.h> 27 27 #include <linux/mm.h> 28 + #include <linux/of_fdt.h> 28 29 29 30 #include <asm/bootparam.h> 30 31 #include <asm/page.h> 31 32 #include <asm/sections.h> 32 33 #include <asm/sysmem.h> 33 - 34 - struct sysmem_info sysmem __initdata; 35 - 36 - static void __init sysmem_dump(void) 37 - { 38 - unsigned i; 39 - 40 - pr_debug("Sysmem:\n"); 41 - for (i = 0; i < sysmem.nr_banks; ++i) 42 - pr_debug(" 0x%08lx - 0x%08lx (%ldK)\n", 43 - sysmem.bank[i].start, sysmem.bank[i].end, 44 - (sysmem.bank[i].end - sysmem.bank[i].start) >> 10); 45 - } 46 - 47 - /* 48 - * Find bank with maximal .start such that bank.start <= start 49 - */ 50 - static inline struct meminfo * __init find_bank(unsigned long start) 51 - { 52 - unsigned i; 53 - struct meminfo *it = NULL; 54 - 55 - for (i = 0; i < sysmem.nr_banks; ++i) 56 - if (sysmem.bank[i].start <= start) 57 - it = sysmem.bank + i; 58 - else 59 - break; 60 - return it; 61 - } 62 - 63 - /* 64 - * Move all memory banks starting at 'from' to a new place at 'to', 65 - * adjust nr_banks accordingly. 66 - * Both 'from' and 'to' must be inside the sysmem.bank. 67 - * 68 - * Returns: 0 (success), -ENOMEM (not enough space in the sysmem.bank). 69 - */ 70 - static int __init move_banks(struct meminfo *to, struct meminfo *from) 71 - { 72 - unsigned n = sysmem.nr_banks - (from - sysmem.bank); 73 - 74 - if (to > from && to - from + sysmem.nr_banks > SYSMEM_BANKS_MAX) 75 - return -ENOMEM; 76 - if (to != from) 77 - memmove(to, from, n * sizeof(struct meminfo)); 78 - sysmem.nr_banks += to - from; 79 - return 0; 80 - } 81 - 82 - /* 83 - * Add new bank to sysmem. Resulting sysmem is the union of bytes of the 84 - * original sysmem and the new bank. 85 - * 86 - * Returns: 0 (success), < 0 (error) 87 - */ 88 - int __init add_sysmem_bank(unsigned long start, unsigned long end) 89 - { 90 - unsigned i; 91 - struct meminfo *it = NULL; 92 - unsigned long sz; 93 - unsigned long bank_sz = 0; 94 - 95 - if (start == end || 96 - (start < end) != (PAGE_ALIGN(start) < (end & PAGE_MASK))) { 97 - pr_warn("Ignoring small memory bank 0x%08lx size: %ld bytes\n", 98 - start, end - start); 99 - return -EINVAL; 100 - } 101 - 102 - start = PAGE_ALIGN(start); 103 - end &= PAGE_MASK; 104 - sz = end - start; 105 - 106 - it = find_bank(start); 107 - 108 - if (it) 109 - bank_sz = it->end - it->start; 110 - 111 - if (it && bank_sz >= start - it->start) { 112 - if (end - it->start > bank_sz) 113 - it->end = end; 114 - else 115 - return 0; 116 - } else { 117 - if (!it) 118 - it = sysmem.bank; 119 - else 120 - ++it; 121 - 122 - if (it - sysmem.bank < sysmem.nr_banks && 123 - it->start - start <= sz) { 124 - it->start = start; 125 - if (it->end - it->start < sz) 126 - it->end = end; 127 - else 128 - return 0; 129 - } else { 130 - if (move_banks(it + 1, it) < 0) { 131 - pr_warn("Ignoring memory bank 0x%08lx size %ld bytes\n", 132 - start, end - start); 133 - return -EINVAL; 134 - } 135 - it->start = start; 136 - it->end = end; 137 - return 0; 138 - } 139 - } 140 - sz = it->end - it->start; 141 - for (i = it + 1 - sysmem.bank; i < sysmem.nr_banks; ++i) 142 - if (sysmem.bank[i].start - it->start <= sz) { 143 - if (sz < sysmem.bank[i].end - it->start) 144 - it->end = sysmem.bank[i].end; 145 - } else { 146 - break; 147 - } 148 - 149 - move_banks(it + 1, sysmem.bank + i); 150 - return 0; 151 - } 152 - 153 - /* 154 - * mem_reserve(start, end, must_exist) 155 - * 156 - * Reserve some memory from the memory pool. 157 - * If must_exist is set and a part of the region being reserved does not exist 158 - * memory map is not altered. 159 - * 160 - * Parameters: 161 - * start Start of region, 162 - * end End of region, 163 - * must_exist Must exist in memory pool. 164 - * 165 - * Returns: 166 - * 0 (success) 167 - * < 0 (error) 168 - */ 169 - 170 - int __init mem_reserve(unsigned long start, unsigned long end, int must_exist) 171 - { 172 - struct meminfo *it; 173 - struct meminfo *rm = NULL; 174 - unsigned long sz; 175 - unsigned long bank_sz = 0; 176 - 177 - start = start & PAGE_MASK; 178 - end = PAGE_ALIGN(end); 179 - sz = end - start; 180 - if (!sz) 181 - return -EINVAL; 182 - 183 - it = find_bank(start); 184 - 185 - if (it) 186 - bank_sz = it->end - it->start; 187 - 188 - if ((!it || end - it->start > bank_sz) && must_exist) { 189 - pr_warn("mem_reserve: [0x%0lx, 0x%0lx) not in any region!\n", 190 - start, end); 191 - return -EINVAL; 192 - } 193 - 194 - if (it && start - it->start <= bank_sz) { 195 - if (start == it->start) { 196 - if (end - it->start < bank_sz) { 197 - it->start = end; 198 - return 0; 199 - } else { 200 - rm = it; 201 - } 202 - } else { 203 - it->end = start; 204 - if (end - it->start < bank_sz) 205 - return add_sysmem_bank(end, 206 - it->start + bank_sz); 207 - ++it; 208 - } 209 - } 210 - 211 - if (!it) 212 - it = sysmem.bank; 213 - 214 - for (; it < sysmem.bank + sysmem.nr_banks; ++it) { 215 - if (it->end - start <= sz) { 216 - if (!rm) 217 - rm = it; 218 - } else { 219 - if (it->start - start < sz) 220 - it->start = end; 221 - break; 222 - } 223 - } 224 - 225 - if (rm) 226 - move_banks(rm, it); 227 - 228 - return 0; 229 - } 230 - 231 34 232 35 /* 233 36 * Initialize the bootmem system and give it all low memory we have available. ··· 38 235 39 236 void __init bootmem_init(void) 40 237 { 41 - unsigned long pfn; 42 - unsigned long bootmap_start, bootmap_size; 43 - int i; 44 - 45 - /* Reserve all memory below PLATFORM_DEFAULT_MEM_START, as memory 238 + /* Reserve all memory below PHYS_OFFSET, as memory 46 239 * accounting doesn't work for pages below that address. 47 240 * 48 - * If PLATFORM_DEFAULT_MEM_START is zero reserve page at address 0: 241 + * If PHYS_OFFSET is zero reserve page at address 0: 49 242 * successfull allocations should never return NULL. 50 243 */ 51 - if (PLATFORM_DEFAULT_MEM_START) 52 - mem_reserve(0, PLATFORM_DEFAULT_MEM_START, 0); 244 + if (PHYS_OFFSET) 245 + memblock_reserve(0, PHYS_OFFSET); 53 246 else 54 - mem_reserve(0, 1, 0); 247 + memblock_reserve(0, 1); 55 248 56 - sysmem_dump(); 57 - max_low_pfn = max_pfn = 0; 58 - min_low_pfn = ~0; 249 + early_init_fdt_scan_reserved_mem(); 59 250 60 - for (i=0; i < sysmem.nr_banks; i++) { 61 - pfn = PAGE_ALIGN(sysmem.bank[i].start) >> PAGE_SHIFT; 62 - if (pfn < min_low_pfn) 63 - min_low_pfn = pfn; 64 - pfn = PAGE_ALIGN(sysmem.bank[i].end - 1) >> PAGE_SHIFT; 65 - if (pfn > max_pfn) 66 - max_pfn = pfn; 67 - } 68 - 69 - if (min_low_pfn > max_pfn) 251 + if (!memblock_phys_mem_size()) 70 252 panic("No memory found!\n"); 71 253 72 - max_low_pfn = max_pfn < MAX_MEM_PFN >> PAGE_SHIFT ? 73 - max_pfn : MAX_MEM_PFN >> PAGE_SHIFT; 254 + min_low_pfn = PFN_UP(memblock_start_of_DRAM()); 255 + min_low_pfn = max(min_low_pfn, PFN_UP(PHYS_OFFSET)); 256 + max_pfn = PFN_DOWN(memblock_end_of_DRAM()); 257 + max_low_pfn = min(max_pfn, MAX_LOW_PFN); 74 258 75 - /* Find an area to use for the bootmem bitmap. */ 259 + memblock_set_current_limit(PFN_PHYS(max_low_pfn)); 76 260 77 - bootmap_size = bootmem_bootmap_pages(max_low_pfn - min_low_pfn); 78 - bootmap_size <<= PAGE_SHIFT; 79 - bootmap_start = ~0; 80 - 81 - for (i=0; i<sysmem.nr_banks; i++) 82 - if (sysmem.bank[i].end - sysmem.bank[i].start >= bootmap_size) { 83 - bootmap_start = sysmem.bank[i].start; 84 - break; 85 - } 86 - 87 - if (bootmap_start == ~0UL) 88 - panic("Cannot find %ld bytes for bootmap\n", bootmap_size); 89 - 90 - /* Reserve the bootmem bitmap area */ 91 - 92 - mem_reserve(bootmap_start, bootmap_start + bootmap_size, 1); 93 - bootmap_size = init_bootmem_node(NODE_DATA(0), 94 - bootmap_start >> PAGE_SHIFT, 95 - min_low_pfn, 96 - max_low_pfn); 97 - 98 - /* Add all remaining memory pieces into the bootmem map */ 99 - 100 - for (i = 0; i < sysmem.nr_banks; i++) { 101 - if (sysmem.bank[i].start >> PAGE_SHIFT < max_low_pfn) { 102 - unsigned long end = min(max_low_pfn << PAGE_SHIFT, 103 - sysmem.bank[i].end); 104 - free_bootmem(sysmem.bank[i].start, 105 - end - sysmem.bank[i].start); 106 - } 107 - } 108 - 261 + memblock_dump_all(); 109 262 } 110 263 111 264 ··· 103 344 " fixmap : 0x%08lx - 0x%08lx (%5lu kB)\n" 104 345 #endif 105 346 #ifdef CONFIG_MMU 106 - " vmalloc : 0x%08x - 0x%08x (%5u MB)\n" 347 + " vmalloc : 0x%08lx - 0x%08lx (%5lu MB)\n" 107 348 #endif 108 349 " lowmem : 0x%08lx - 0x%08lx (%5lu MB)\n", 109 350 #ifdef CONFIG_HIGHMEM ··· 154 395 switch (*p) { 155 396 case '@': 156 397 start_at = memparse(p + 1, &p); 157 - add_sysmem_bank(start_at, start_at + mem_size); 398 + memblock_add(start_at, mem_size); 158 399 break; 159 400 160 401 case '$': 161 402 start_at = memparse(p + 1, &p); 162 - mem_reserve(start_at, start_at + mem_size, 0); 403 + memblock_reserve(start_at, mem_size); 163 404 break; 164 405 165 406 case 0: 166 - mem_reserve(mem_size, 0, 0); 407 + memblock_reserve(mem_size, -mem_size); 167 408 break; 168 409 169 410 default: