Merge tag 'i2c-for-6.5-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux

Pull i2c fixes from Wolfram Sang:
"Usual set of driver fixes. A bit more than usual because I was
unavailable for a while"

* tag 'i2c-for-6.5-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux:
i2c: bcm-iproc: Fix bcm_iproc_i2c_isr deadlock issue
i2c: Update documentation to use .probe() again
i2c: sun6i-p2wi: Fix an error message in probe()
i2c: hisi: Only handle the interrupt of the driver's transfer
i2c: tegra: Fix i2c-tegra DMA config option processing
i2c: tegra: Fix failure during probe deferral cleanup
i2c: designware: Handle invalid SMBus block data response length value
i2c: designware: Correct length byte validation logic
i2c: imx-lpi2c: return -EINVAL when i2c peripheral clk doesn't work

+1 -1
Documentation/i2c/writing-clients.rst
··· 46 46 }, 47 47 48 48 .id_table = foo_idtable, 49 - .probe_new = foo_probe, 49 + .probe = foo_probe, 50 50 .remove = foo_remove, 51 51 /* if device autodetection is needed: */ 52 52 .class = I2C_CLASS_SOMETHING,
+7 -4
drivers/i2c/busses/i2c-bcm-iproc.c
··· 233 233 u32 offset) 234 234 { 235 235 u32 val; 236 + unsigned long flags; 236 237 237 238 if (iproc_i2c->idm_base) { 238 - spin_lock(&iproc_i2c->idm_lock); 239 + spin_lock_irqsave(&iproc_i2c->idm_lock, flags); 239 240 writel(iproc_i2c->ape_addr_mask, 240 241 iproc_i2c->idm_base + IDM_CTRL_DIRECT_OFFSET); 241 242 val = readl(iproc_i2c->base + offset); 242 - spin_unlock(&iproc_i2c->idm_lock); 243 + spin_unlock_irqrestore(&iproc_i2c->idm_lock, flags); 243 244 } else { 244 245 val = readl(iproc_i2c->base + offset); 245 246 } ··· 251 250 static inline void iproc_i2c_wr_reg(struct bcm_iproc_i2c_dev *iproc_i2c, 252 251 u32 offset, u32 val) 253 252 { 253 + unsigned long flags; 254 + 254 255 if (iproc_i2c->idm_base) { 255 - spin_lock(&iproc_i2c->idm_lock); 256 + spin_lock_irqsave(&iproc_i2c->idm_lock, flags); 256 257 writel(iproc_i2c->ape_addr_mask, 257 258 iproc_i2c->idm_base + IDM_CTRL_DIRECT_OFFSET); 258 259 writel(val, iproc_i2c->base + offset); 259 - spin_unlock(&iproc_i2c->idm_lock); 260 + spin_unlock_irqrestore(&iproc_i2c->idm_lock, flags); 260 261 } else { 261 262 writel(val, iproc_i2c->base + offset); 262 263 }
+14 -2
drivers/i2c/busses/i2c-designware-master.c
··· 588 588 u32 flags = msgs[dev->msg_read_idx].flags; 589 589 590 590 regmap_read(dev->map, DW_IC_DATA_CMD, &tmp); 591 + tmp &= DW_IC_DATA_CMD_DAT; 591 592 /* Ensure length byte is a valid value */ 592 - if (flags & I2C_M_RECV_LEN && 593 - (tmp & DW_IC_DATA_CMD_DAT) <= I2C_SMBUS_BLOCK_MAX && tmp > 0) { 593 + if (flags & I2C_M_RECV_LEN) { 594 + /* 595 + * if IC_EMPTYFIFO_HOLD_MASTER_EN is set, which cannot be 596 + * detected from the registers, the controller can be 597 + * disabled if the STOP bit is set. But it is only set 598 + * after receiving block data response length in 599 + * I2C_FUNC_SMBUS_BLOCK_DATA case. That needs to read 600 + * another byte with STOP bit set when the block data 601 + * response length is invalid to complete the transaction. 602 + */ 603 + if (!tmp || tmp > I2C_SMBUS_BLOCK_MAX) 604 + tmp = 1; 605 + 594 606 len = i2c_dw_recv_len(dev, tmp); 595 607 } 596 608 *buf++ = tmp;
+8
drivers/i2c/busses/i2c-hisi.c
··· 330 330 struct hisi_i2c_controller *ctlr = context; 331 331 u32 int_stat; 332 332 333 + /* 334 + * Don't handle the interrupt if cltr->completion is NULL. We may 335 + * reach here because the interrupt is spurious or the transfer is 336 + * started by another port (e.g. firmware) rather than us. 337 + */ 338 + if (!ctlr->completion) 339 + return IRQ_NONE; 340 + 333 341 int_stat = readl(ctlr->iobase + HISI_I2C_INT_MSTAT); 334 342 hisi_i2c_clear_int(ctlr, int_stat); 335 343 if (!(int_stat & HISI_I2C_INT_ALL))
+3
drivers/i2c/busses/i2c-imx-lpi2c.c
··· 209 209 lpi2c_imx_set_mode(lpi2c_imx); 210 210 211 211 clk_rate = clk_get_rate(lpi2c_imx->clks[0].clk); 212 + if (!clk_rate) 213 + return -EINVAL; 214 + 212 215 if (lpi2c_imx->mode == HS || lpi2c_imx->mode == ULTRA_FAST) 213 216 filt = 0; 214 217 else
+2 -1
drivers/i2c/busses/i2c-sun6i-p2wi.c
··· 250 250 251 251 p2wi->rstc = devm_reset_control_get_exclusive(dev, NULL); 252 252 if (IS_ERR(p2wi->rstc)) { 253 - dev_err(dev, "failed to retrieve reset controller: %d\n", ret); 253 + dev_err(dev, "failed to retrieve reset controller: %pe\n", 254 + p2wi->rstc); 254 255 return PTR_ERR(p2wi->rstc); 255 256 } 256 257
+2 -1
drivers/i2c/busses/i2c-tegra.c
··· 442 442 if (IS_VI(i2c_dev)) 443 443 return 0; 444 444 445 - if (!i2c_dev->hw->has_apb_dma) { 445 + if (i2c_dev->hw->has_apb_dma) { 446 446 if (!IS_ENABLED(CONFIG_TEGRA20_APB_DMA)) { 447 447 dev_dbg(i2c_dev->dev, "APB DMA support not enabled\n"); 448 448 return 0; ··· 460 460 i2c_dev->dma_chan = dma_request_chan(i2c_dev->dev, "tx"); 461 461 if (IS_ERR(i2c_dev->dma_chan)) { 462 462 err = PTR_ERR(i2c_dev->dma_chan); 463 + i2c_dev->dma_chan = NULL; 463 464 goto err_out; 464 465 } 465 466