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Merge tag 'riscv-cache-for-v6.11' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/drivers
RISC-V cache drivers for v6.11
StarFive:
A new driver for the cache controller on the jh8100, which didn't
implement Zicbom and thus needs an implementation of non-standard cache
management operations.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
* tag 'riscv-cache-for-v6.11' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux:
MAINTAINERS: add microchip soc binding directory to microchip soc driver entry
MAINTAINERS: add cache binding directory to cache driver entry
cache: Add StarFive StarLink cache management
dt-bindings: cache: Add docs for StarFive Starlink cache controller
Link: https://lore.kernel.org/r/20240707-whoever-undesired-c5f6e96ae403@spud
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+210
-2
+66
Documentation/devicetree/bindings/cache/starfive,jh8100-starlink-cache.yaml
+66
Documentation/devicetree/bindings/cache/starfive,jh8100-starlink-cache.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/cache/starfive,jh8100-starlink-cache.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: StarFive StarLink Cache Controller
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maintainers:
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- Joshua Yeong <joshua.yeong@starfivetech.com>
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description:
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StarFive's StarLink Cache Controller manages the L3 cache shared between
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clusters of CPU cores. The cache driver enables RISC-V non-standard cache
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management as an alternative to instructions in the RISC-V Zicbom extension.
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allOf:
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- $ref: /schemas/cache-controller.yaml#
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# We need a select here so we don't match all nodes with 'cache'
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select:
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properties:
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compatible:
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contains:
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enum:
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- starfive,jh8100-starlink-cache
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+
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required:
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- compatible
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+
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properties:
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compatible:
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items:
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- const: starfive,jh8100-starlink-cache
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- const: cache
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+
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reg:
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maxItems: 1
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+
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unevaluatedProperties: false
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+
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required:
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- compatible
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- reg
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- cache-block-size
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- cache-level
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- cache-sets
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- cache-size
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- cache-unified
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+
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examples:
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- |
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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cache-controller@15000000 {
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compatible = "starfive,jh8100-starlink-cache", "cache";
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reg = <0x0 0x15000000 0x0 0x278>;
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cache-block-size = <64>;
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cache-level = <3>;
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cache-sets = <8192>;
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cache-size = <0x400000>;
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cache-unified;
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};
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};
+2
MAINTAINERS
+2
MAINTAINERS
···
14852
14852
M: Conor Dooley <conor@kernel.org>
14853
14853
S: Supported
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T: git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/
14855
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F: Documentation/devicetree/bindings/soc/microchip/
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14856
F: drivers/soc/microchip/
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14857
14857
14858
MICROCHIP SPI DRIVER
···
21288
21287
L: linux-riscv@lists.infradead.org
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S: Maintained
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T: git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/
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F: Documentation/devicetree/bindings/cache/
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F: drivers/cache
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21293
STARFIRE/DURALAN NETWORK DRIVER
+9
drivers/cache/Kconfig
+9
drivers/cache/Kconfig
···
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help
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Support for the composable cache controller on SiFive platforms.
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config STARFIVE_STARLINK_CACHE
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bool "StarFive StarLink Cache controller"
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depends on RISCV
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depends on ARCH_STARFIVE
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select RISCV_DMA_NONCOHERENT
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select RISCV_NONSTANDARD_CACHE_OPS
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help
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Support for the StarLink cache controller IP from StarFive.
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+
17
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endmenu
+3
-2
drivers/cache/Makefile
+3
-2
drivers/cache/Makefile
···
1
1
# SPDX-License-Identifier: GPL-2.0
2
2
3
-
obj-$(CONFIG_AX45MP_L2_CACHE) += ax45mp_cache.o
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-
obj-$(CONFIG_SIFIVE_CCACHE) += sifive_ccache.o
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obj-$(CONFIG_AX45MP_L2_CACHE) += ax45mp_cache.o
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obj-$(CONFIG_SIFIVE_CCACHE) += sifive_ccache.o
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obj-$(CONFIG_STARFIVE_STARLINK_CACHE) += starfive_starlink_cache.o
+130
drivers/cache/starfive_starlink_cache.c
+130
drivers/cache/starfive_starlink_cache.c
···
1
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Cache Management Operations for StarFive's Starlink cache controller
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*
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* Copyright (C) 2024 Shanghai StarFive Technology Co., Ltd.
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*
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* Author: Joshua Yeong <joshua.yeong@starfivetech.com>
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*/
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#include <linux/bitfield.h>
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#include <linux/cacheflush.h>
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#include <linux/iopoll.h>
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#include <linux/of_address.h>
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+
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#include <asm/dma-noncoherent.h>
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+
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#define STARLINK_CACHE_FLUSH_START_ADDR 0x0
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#define STARLINK_CACHE_FLUSH_END_ADDR 0x8
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#define STARLINK_CACHE_FLUSH_CTL 0x10
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#define STARLINK_CACHE_ALIGN 0x40
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+
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#define STARLINK_CACHE_ADDRESS_RANGE_MASK GENMASK(39, 0)
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#define STARLINK_CACHE_FLUSH_CTL_MODE_MASK GENMASK(2, 1)
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#define STARLINK_CACHE_FLUSH_CTL_ENABLE_MASK BIT(0)
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+
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#define STARLINK_CACHE_FLUSH_CTL_CLEAN_INVALIDATE 0
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#define STARLINK_CACHE_FLUSH_CTL_MAKE_INVALIDATE 1
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#define STARLINK_CACHE_FLUSH_CTL_CLEAN_SHARED 2
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#define STARLINK_CACHE_FLUSH_POLL_DELAY_US 1
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#define STARLINK_CACHE_FLUSH_TIMEOUT_US 5000000
31
+
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static void __iomem *starlink_cache_base;
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+
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static void starlink_cache_flush_complete(void)
35
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{
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volatile void __iomem *ctl = starlink_cache_base + STARLINK_CACHE_FLUSH_CTL;
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u64 v;
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int ret;
39
+
40
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ret = readq_poll_timeout_atomic(ctl, v, !(v & STARLINK_CACHE_FLUSH_CTL_ENABLE_MASK),
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STARLINK_CACHE_FLUSH_POLL_DELAY_US,
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STARLINK_CACHE_FLUSH_TIMEOUT_US);
43
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if (ret)
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WARN(1, "StarFive Starlink cache flush operation timeout\n");
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}
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+
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static void starlink_cache_dma_cache_wback(phys_addr_t paddr, unsigned long size)
48
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{
49
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writeq(FIELD_PREP(STARLINK_CACHE_ADDRESS_RANGE_MASK, paddr),
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starlink_cache_base + STARLINK_CACHE_FLUSH_START_ADDR);
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writeq(FIELD_PREP(STARLINK_CACHE_ADDRESS_RANGE_MASK, paddr + size),
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starlink_cache_base + STARLINK_CACHE_FLUSH_END_ADDR);
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+
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mb();
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writeq(FIELD_PREP(STARLINK_CACHE_FLUSH_CTL_MODE_MASK,
56
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STARLINK_CACHE_FLUSH_CTL_CLEAN_SHARED),
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starlink_cache_base + STARLINK_CACHE_FLUSH_CTL);
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+
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starlink_cache_flush_complete();
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}
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+
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static void starlink_cache_dma_cache_invalidate(phys_addr_t paddr, unsigned long size)
63
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{
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writeq(FIELD_PREP(STARLINK_CACHE_ADDRESS_RANGE_MASK, paddr),
65
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starlink_cache_base + STARLINK_CACHE_FLUSH_START_ADDR);
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writeq(FIELD_PREP(STARLINK_CACHE_ADDRESS_RANGE_MASK, paddr + size),
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starlink_cache_base + STARLINK_CACHE_FLUSH_END_ADDR);
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+
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mb();
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writeq(FIELD_PREP(STARLINK_CACHE_FLUSH_CTL_MODE_MASK,
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STARLINK_CACHE_FLUSH_CTL_MAKE_INVALIDATE),
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starlink_cache_base + STARLINK_CACHE_FLUSH_CTL);
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+
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starlink_cache_flush_complete();
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}
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+
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static void starlink_cache_dma_cache_wback_inv(phys_addr_t paddr, unsigned long size)
78
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{
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writeq(FIELD_PREP(STARLINK_CACHE_ADDRESS_RANGE_MASK, paddr),
80
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starlink_cache_base + STARLINK_CACHE_FLUSH_START_ADDR);
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writeq(FIELD_PREP(STARLINK_CACHE_ADDRESS_RANGE_MASK, paddr + size),
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starlink_cache_base + STARLINK_CACHE_FLUSH_END_ADDR);
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+
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mb();
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writeq(FIELD_PREP(STARLINK_CACHE_FLUSH_CTL_MODE_MASK,
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STARLINK_CACHE_FLUSH_CTL_CLEAN_INVALIDATE),
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starlink_cache_base + STARLINK_CACHE_FLUSH_CTL);
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+
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starlink_cache_flush_complete();
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}
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+
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static const struct riscv_nonstd_cache_ops starlink_cache_ops = {
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.wback = &starlink_cache_dma_cache_wback,
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.inv = &starlink_cache_dma_cache_invalidate,
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.wback_inv = &starlink_cache_dma_cache_wback_inv,
96
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};
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+
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static const struct of_device_id starlink_cache_ids[] = {
99
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{ .compatible = "starfive,jh8100-starlink-cache" },
100
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{ /* sentinel */ }
101
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};
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+
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static int __init starlink_cache_init(void)
104
+
{
105
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struct device_node *np;
106
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u32 block_size;
107
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int ret;
108
+
109
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np = of_find_matching_node(NULL, starlink_cache_ids);
110
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if (!of_device_is_available(np))
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return -ENODEV;
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+
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ret = of_property_read_u32(np, "cache-block-size", &block_size);
114
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if (ret)
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+
return ret;
116
+
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+
if (block_size % STARLINK_CACHE_ALIGN)
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return -EINVAL;
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+
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starlink_cache_base = of_iomap(np, 0);
121
+
if (!starlink_cache_base)
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return -ENOMEM;
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+
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riscv_cbom_block_size = block_size;
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+
riscv_noncoherent_supported();
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riscv_noncoherent_register_cache_ops(&starlink_cache_ops);
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+
128
+
return 0;
129
+
}
130
+
arch_initcall(starlink_cache_init);