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ARM: dts: sunxi: Add missing watchdog clocks

The watchdog has a clock on all our SoCs, but it wasn't always listed.
Add it to the devicetree where it's missing.

Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>

Maxime Ripard 9e1975f0 89d1e514

+11
+1
arch/arm/boot/dts/sun4i-a10.dtsi
··· 816 816 compatible = "allwinner,sun4i-a10-wdt"; 817 817 reg = <0x01c20c90 0x10>; 818 818 interrupts = <24>; 819 + clocks = <&osc24M>; 819 820 }; 820 821 821 822 rtc: rtc@1c20d00 {
+1
arch/arm/boot/dts/sun5i.dtsi
··· 601 601 compatible = "allwinner,sun4i-a10-wdt"; 602 602 reg = <0x01c20c90 0x10>; 603 603 interrupts = <24>; 604 + clocks = <&osc24M>; 604 605 }; 605 606 606 607 ir0: ir@1c21800 {
+1
arch/arm/boot/dts/sun6i-a31.dtsi
··· 745 745 compatible = "allwinner,sun6i-a31-wdt"; 746 746 reg = <0x01c20ca0 0x20>; 747 747 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 748 + clocks = <&osc24M>; 748 749 }; 749 750 750 751 spdif: spdif@1c21000 {
+1
arch/arm/boot/dts/sun7i-a20.dtsi
··· 1141 1141 compatible = "allwinner,sun4i-a10-wdt"; 1142 1142 reg = <0x01c20c90 0x10>; 1143 1143 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 1144 + clocks = <&osc24M>; 1144 1145 }; 1145 1146 1146 1147 rtc: rtc@1c20d00 {
+1
arch/arm/boot/dts/sun8i-a23-a33.dtsi
··· 452 452 compatible = "allwinner,sun6i-a31-wdt"; 453 453 reg = <0x01c20ca0 0x20>; 454 454 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 455 + clocks = <&osc24M>; 455 456 }; 456 457 457 458 pwm: pwm@1c21400 {
+1
arch/arm/boot/dts/sun8i-r40.dtsi
··· 405 405 compatible = "allwinner,sun4i-a10-wdt"; 406 406 reg = <0x01c20c90 0x10>; 407 407 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 408 + clocks = <&osc24M>; 408 409 }; 409 410 410 411 uart0: serial@1c28000 {
+1
arch/arm/boot/dts/sun8i-v3s.dtsi
··· 339 339 compatible = "allwinner,sun6i-a31-wdt"; 340 340 reg = <0x01c20ca0 0x20>; 341 341 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 342 + clocks = <&osc24M>; 342 343 }; 343 344 344 345 lradc: lradc@1c22800 {
+1
arch/arm/boot/dts/sunxi-h3-h5.dtsi
··· 574 574 compatible = "allwinner,sun6i-a31-wdt"; 575 575 reg = <0x01c20ca0 0x20>; 576 576 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 577 + clocks = <&osc24M>; 577 578 }; 578 579 579 580 spdif: spdif@1c21000 {
+1
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
··· 1169 1169 "allwinner,sun6i-a31-wdt"; 1170 1170 reg = <0x01c20ca0 0x20>; 1171 1171 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 1172 + clocks = <&osc24M>; 1172 1173 }; 1173 1174 }; 1174 1175 };
+2
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
··· 217 217 "allwinner,sun6i-a31-wdt"; 218 218 reg = <0x030090a0 0x20>; 219 219 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 220 + clocks = <&osc24M>; 220 221 /* Broken on some H6 boards */ 221 222 status = "disabled"; 222 223 }; ··· 728 727 "allwinner,sun6i-a31-wdt"; 729 728 reg = <0x07020400 0x20>; 730 729 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 730 + clocks = <&osc24M>; 731 731 }; 732 732 733 733 r_intc: interrupt-controller@7021000 {