Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

Merge branch 'renesas/cleanup' into next/dt

Dependency for renesas/dt

+4 -2687
-6
Documentation/devicetree/bindings/arm/shmobile.txt
··· 39 39 compatible = "renesas,armadillo800eva" 40 40 - BOCK-W 41 41 compatible = "renesas,bockw", "renesas,r8a7778" 42 - - BOCK-W - Reference Device Tree Implementation 43 - compatible = "renesas,bockw-reference", "renesas,r8a7778" 44 42 - Genmai (RTK772100BC00000BR) 45 43 compatible = "renesas,genmai", "renesas,r7s72100" 46 44 - Gose ··· 55 57 compatible = "renesas,lager", "renesas,r8a7790" 56 58 - Marzen 57 59 compatible = "renesas,marzen", "renesas,r8a7779" 58 - 59 - Note: Reference Device Tree Implementations are temporary implementations 60 - to ease the migration from platform devices to Device Tree, and are 61 - intended to be removed in the future.
-2
MAINTAINERS
··· 1496 1496 F: arch/arm/boot/dts/r7s* 1497 1497 F: arch/arm/boot/dts/r8a* 1498 1498 F: arch/arm/boot/dts/sh* 1499 - F: arch/arm/configs/bockw_defconfig 1500 - F: arch/arm/configs/marzen_defconfig 1501 1499 F: arch/arm/configs/shmobile_defconfig 1502 1500 F: arch/arm/include/debug/renesas-scif.S 1503 1501 F: arch/arm/mach-shmobile/
+1 -25
arch/arm/Kconfig
··· 621 621 help 622 622 Support for Intel/Marvell's PXA2xx/PXA3xx processor line. 623 623 624 - config ARCH_SHMOBILE_LEGACY 625 - bool "Renesas ARM SoCs (non-multiplatform)" 626 - select ARCH_SHMOBILE 627 - select ARM_PATCH_PHYS_VIRT if MMU 628 - select CLKDEV_LOOKUP 629 - select CPU_V7 630 - select GENERIC_CLOCKEVENTS 631 - select HAVE_ARM_SCU if SMP 632 - select HAVE_ARM_TWD if SMP 633 - select HAVE_SMP 634 - select MIGHT_HAVE_CACHE_L2X0 635 - select MULTI_IRQ_HANDLER 636 - select NO_IOPORT_MAP 637 - select PINCTRL 638 - select PM_GENERIC_DOMAINS if PM 639 - select SH_CLK_CPG 640 - select SPARSE_IRQ 641 - help 642 - Support for Renesas ARM SoC platforms using a non-multiplatform 643 - kernel. This includes the SH-Mobile, R-Mobile, EMMA-Mobile, R-Car 644 - and RZ families. 645 - 646 624 config ARCH_RPC 647 625 bool "RiscPC" 648 626 select ARCH_ACORN ··· 1512 1534 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \ 1513 1535 ARCH_S5PV210 || ARCH_EXYNOS4 1514 1536 default 128 if SOC_AT91RM9200 1515 - default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY 1516 1537 default 0 1517 1538 1518 1539 choice ··· 1729 1752 source "mm/Kconfig" 1730 1753 1731 1754 config FORCE_MAX_ZONEORDER 1732 - int "Maximum zone order" if ARCH_SHMOBILE_LEGACY 1733 - range 11 64 if ARCH_SHMOBILE_LEGACY 1755 + int "Maximum zone order" 1734 1756 default "12" if SOC_AM33XX 1735 1757 default "9" if SA1111 || ARCH_EFM32 1736 1758 default "11"
+1 -2
arch/arm/Kconfig.debug
··· 1621 1621 config UNCOMPRESS_INCLUDE 1622 1622 string 1623 1623 default "debug/uncompress.h" if ARCH_MULTIPLATFORM || ARCH_MSM || \ 1624 - PLAT_SAMSUNG || ARM_SINGLE_ARMV7M || \ 1625 - ARCH_SHMOBILE_LEGACY 1624 + PLAT_SAMSUNG || ARM_SINGLE_ARMV7M 1626 1625 default "mach/uncompress.h" 1627 1626 1628 1627 config EARLY_PRINTK
-3
arch/arm/boot/dts/Makefile
··· 522 522 s5pv210-smdkc110.dtb \ 523 523 s5pv210-smdkv210.dtb \ 524 524 s5pv210-torbreck.dtb 525 - dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += \ 526 - r8a7778-bockw.dtb \ 527 - r8a7778-bockw-reference.dtb 528 525 dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \ 529 526 emev2-kzm9d.dtb \ 530 527 r7s72100-genmai.dtb \
-139
arch/arm/boot/dts/r8a7778-bockw-reference.dts
··· 1 - /* 2 - * Reference Device Tree Source for the Bock-W board 3 - * 4 - * Copyright (C) 2013 Renesas Solutions Corp. 5 - * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> 6 - * 7 - * based on r8a7779 8 - * 9 - * Copyright (C) 2013 Renesas Solutions Corp. 10 - * Copyright (C) 2013 Simon Horman 11 - * 12 - * This file is licensed under the terms of the GNU General Public License 13 - * version 2. This program is licensed "as is" without any warranty of any 14 - * kind, whether express or implied. 15 - */ 16 - 17 - /dts-v1/; 18 - #include "r8a7778.dtsi" 19 - #include <dt-bindings/interrupt-controller/irq.h> 20 - #include <dt-bindings/gpio/gpio.h> 21 - 22 - / { 23 - model = "bockw"; 24 - compatible = "renesas,bockw-reference", "renesas,r8a7778"; 25 - 26 - aliases { 27 - serial0 = &scif0; 28 - }; 29 - 30 - chosen { 31 - bootargs = "ignore_loglevel root=/dev/nfs ip=dhcp rw"; 32 - stdout-path = &scif0; 33 - }; 34 - 35 - memory { 36 - device_type = "memory"; 37 - reg = <0x60000000 0x10000000>; 38 - }; 39 - 40 - fixedregulator3v3: fixedregulator@0 { 41 - compatible = "regulator-fixed"; 42 - regulator-name = "fixed-3.3V"; 43 - regulator-min-microvolt = <3300000>; 44 - regulator-max-microvolt = <3300000>; 45 - regulator-boot-on; 46 - regulator-always-on; 47 - }; 48 - 49 - ethernet@18300000 { 50 - compatible = "smsc,lan9220", "smsc,lan9115"; 51 - reg = <0x18300000 0x1000>; 52 - 53 - phy-mode = "mii"; 54 - interrupt-parent = <&irqpin>; 55 - interrupts = <0 IRQ_TYPE_EDGE_FALLING>; 56 - reg-io-width = <4>; 57 - vddvario-supply = <&fixedregulator3v3>; 58 - vdd33a-supply = <&fixedregulator3v3>; 59 - }; 60 - 61 - }; 62 - 63 - &mmcif { 64 - pinctrl-0 = <&mmc_pins>; 65 - pinctrl-names = "default"; 66 - 67 - vmmc-supply = <&fixedregulator3v3>; 68 - bus-width = <8>; 69 - broken-cd; 70 - status = "okay"; 71 - }; 72 - 73 - &irqpin { 74 - status = "okay"; 75 - }; 76 - 77 - &tmu0 { 78 - status = "okay"; 79 - }; 80 - 81 - &pfc { 82 - scif0_pins: serial0 { 83 - renesas,groups = "scif0_data_a", "scif0_ctrl"; 84 - renesas,function = "scif0"; 85 - }; 86 - 87 - mmc_pins: mmc { 88 - renesas,groups = "mmc_data8", "mmc_ctrl"; 89 - renesas,function = "mmc"; 90 - }; 91 - 92 - sdhi0_pins: sd0 { 93 - renesas,groups = "sdhi0_data4", "sdhi0_ctrl", 94 - "sdhi0_cd"; 95 - renesas,function = "sdhi0"; 96 - }; 97 - 98 - hspi0_pins: hspi0 { 99 - renesas,groups = "hspi0_a"; 100 - renesas,function = "hspi0"; 101 - }; 102 - }; 103 - 104 - &sdhi0 { 105 - pinctrl-0 = <&sdhi0_pins>; 106 - pinctrl-names = "default"; 107 - 108 - vmmc-supply = <&fixedregulator3v3>; 109 - bus-width = <4>; 110 - status = "okay"; 111 - wp-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>; 112 - }; 113 - 114 - &hspi0 { 115 - pinctrl-0 = <&hspi0_pins>; 116 - pinctrl-names = "default"; 117 - status = "okay"; 118 - 119 - flash: flash@0 { 120 - #address-cells = <1>; 121 - #size-cells = <1>; 122 - compatible = "spansion,s25fl008k", "jedec,spi-nor"; 123 - reg = <0>; 124 - spi-max-frequency = <104000000>; 125 - m25p,fast-read; 126 - 127 - partition@0 { 128 - label = "data(spi)"; 129 - reg = <0x00000000 0x00100000>; 130 - }; 131 - }; 132 - }; 133 - 134 - &scif0 { 135 - pinctrl-0 = <&scif0_pins>; 136 - pinctrl-names = "default"; 137 - 138 - status = "okay"; 139 - };
-133
arch/arm/configs/bockw_defconfig
··· 1 - # CONFIG_ARM_PATCH_PHYS_VIRT is not set 2 - CONFIG_KERNEL_LZMA=y 3 - CONFIG_NO_HZ=y 4 - CONFIG_IKCONFIG=y 5 - CONFIG_IKCONFIG_PROC=y 6 - CONFIG_LOG_BUF_SHIFT=16 7 - CONFIG_SYSCTL_SYSCALL=y 8 - CONFIG_EMBEDDED=y 9 - CONFIG_SLAB=y 10 - # CONFIG_IOSCHED_CFQ is not set 11 - CONFIG_ARCH_SHMOBILE_LEGACY=y 12 - CONFIG_ARCH_R8A7778=y 13 - CONFIG_MACH_BOCKW=y 14 - CONFIG_MEMORY_START=0x60000000 15 - CONFIG_MEMORY_SIZE=0x10000000 16 - CONFIG_SHMOBILE_TIMER_HZ=1024 17 - # CONFIG_SH_TIMER_CMT is not set 18 - # CONFIG_EM_TIMER_STI is not set 19 - CONFIG_ARM_ERRATA_430973=y 20 - CONFIG_ARM_ERRATA_458693=y 21 - CONFIG_ARM_ERRATA_460075=y 22 - CONFIG_ARM_ERRATA_743622=y 23 - CONFIG_ARM_ERRATA_754322=y 24 - CONFIG_AEABI=y 25 - # CONFIG_OABI_COMPAT is not set 26 - CONFIG_HIGHMEM=y 27 - CONFIG_ZBOOT_ROM_TEXT=0x0 28 - CONFIG_ZBOOT_ROM_BSS=0x0 29 - CONFIG_ARM_APPENDED_DTB=y 30 - CONFIG_VFP=y 31 - # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set 32 - CONFIG_PM=y 33 - CONFIG_NET=y 34 - CONFIG_PACKET=y 35 - CONFIG_UNIX=y 36 - CONFIG_INET=y 37 - CONFIG_IP_PNP=y 38 - CONFIG_IP_PNP_DHCP=y 39 - # CONFIG_INET_XFRM_MODE_TRANSPORT is not set 40 - # CONFIG_INET_XFRM_MODE_TUNNEL is not set 41 - # CONFIG_INET_XFRM_MODE_BEET is not set 42 - # CONFIG_INET_LRO is not set 43 - # CONFIG_INET_DIAG is not set 44 - # CONFIG_IPV6 is not set 45 - CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" 46 - CONFIG_DEVTMPFS=y 47 - CONFIG_DEVTMPFS_MOUNT=y 48 - # CONFIG_STANDALONE is not set 49 - # CONFIG_PREVENT_FIRMWARE_BUILD is not set 50 - # CONFIG_FW_LOADER is not set 51 - CONFIG_MTD=y 52 - CONFIG_MTD_CHAR=y 53 - CONFIG_MTD_BLOCK=y 54 - CONFIG_MTD_CFI=y 55 - CONFIG_MTD_CFI_AMDSTD=y 56 - CONFIG_MTD_M25P80=y 57 - CONFIG_MTD_SPI_NOR=y 58 - CONFIG_SCSI=y 59 - CONFIG_BLK_DEV_SD=y 60 - CONFIG_NETDEVICES=y 61 - # CONFIG_NET_CADENCE is not set 62 - # CONFIG_NET_VENDOR_BROADCOM is not set 63 - # CONFIG_NET_VENDOR_CIRRUS is not set 64 - # CONFIG_NET_VENDOR_FARADAY is not set 65 - # CONFIG_NET_VENDOR_INTEL is not set 66 - # CONFIG_NET_VENDOR_MARVELL is not set 67 - # CONFIG_NET_VENDOR_MICREL is not set 68 - # CONFIG_NET_VENDOR_NATSEMI is not set 69 - # CONFIG_NET_VENDOR_SEEQ is not set 70 - CONFIG_SMSC911X=y 71 - # CONFIG_NET_VENDOR_STMICRO is not set 72 - # CONFIG_NET_VENDOR_WIZNET is not set 73 - # CONFIG_INPUT is not set 74 - # CONFIG_SERIO is not set 75 - # CONFIG_VT is not set 76 - # CONFIG_LEGACY_PTYS is not set 77 - # CONFIG_DEVKMEM is not set 78 - CONFIG_SERIAL_SH_SCI=y 79 - CONFIG_SERIAL_SH_SCI_NR_UARTS=6 80 - CONFIG_SERIAL_SH_SCI_CONSOLE=y 81 - # CONFIG_HW_RANDOM is not set 82 - # CONFIG_HWMON is not set 83 - CONFIG_I2C=y 84 - CONFIG_I2C_RCAR=y 85 - CONFIG_GPIO_RCAR=y 86 - CONFIG_REGULATOR=y 87 - CONFIG_MEDIA_SUPPORT=y 88 - CONFIG_MEDIA_CAMERA_SUPPORT=y 89 - CONFIG_V4L_PLATFORM_DRIVERS=y 90 - CONFIG_SOC_CAMERA=y 91 - CONFIG_VIDEO_RCAR_VIN=y 92 - # CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set 93 - CONFIG_VIDEO_ML86V7667=y 94 - CONFIG_SPI=y 95 - CONFIG_SPI_SH_HSPI=y 96 - CONFIG_SOUND=y 97 - CONFIG_SND=y 98 - CONFIG_SND_SOC=y 99 - CONFIG_SND_SOC_RCAR=y 100 - CONFIG_USB=y 101 - CONFIG_USB_ANNOUNCE_NEW_DEVICES=y 102 - CONFIG_USB_EHCI_HCD=y 103 - CONFIG_USB_OHCI_HCD=y 104 - CONFIG_USB_OHCI_HCD_PLATFORM=y 105 - CONFIG_USB_EHCI_HCD_PLATFORM=y 106 - CONFIG_USB_STORAGE=y 107 - CONFIG_USB_RCAR_PHY=y 108 - CONFIG_MMC=y 109 - CONFIG_MMC_SDHI=y 110 - CONFIG_MMC_SH_MMCIF=y 111 - CONFIG_RTC_CLASS=y 112 - CONFIG_RTC_DRV_RX8581=y 113 - CONFIG_DMADEVICES=y 114 - CONFIG_RCAR_HPB_DMAE=y 115 - CONFIG_UIO=y 116 - CONFIG_UIO_PDRV_GENIRQ=y 117 - # CONFIG_IOMMU_SUPPORT is not set 118 - # CONFIG_DNOTIFY is not set 119 - CONFIG_TMPFS=y 120 - # CONFIG_MISC_FILESYSTEMS is not set 121 - CONFIG_NFS_FS=y 122 - CONFIG_NFS_V3_ACL=y 123 - CONFIG_NFS_V4=y 124 - CONFIG_NFS_SWAP=y 125 - CONFIG_NFS_V4_1=y 126 - CONFIG_ROOT_NFS=y 127 - # CONFIG_ENABLE_WARN_DEPRECATED is not set 128 - # CONFIG_ENABLE_MUST_CHECK is not set 129 - # CONFIG_SCHED_DEBUG is not set 130 - # CONFIG_DEBUG_BUGVERBOSE is not set 131 - # CONFIG_FTRACE is not set 132 - # CONFIG_ARM_UNWIND is not set 133 - CONFIG_AVERAGE=y
-73
arch/arm/mach-shmobile/Kconfig
··· 98 98 99 99 comment "Renesas ARM SoCs System Configuration" 100 100 endif 101 - 102 - if ARCH_SHMOBILE_LEGACY 103 - 104 - comment "Renesas ARM SoCs System Type" 105 - 106 - config ARCH_R8A7778 107 - bool "R-Car M1A (R8A77781)" 108 - select ARCH_RCAR_GEN1 109 - select ARCH_WANT_OPTIONAL_GPIOLIB 110 - select ARM_GIC 111 - 112 - config ARCH_R8A7779 113 - bool "R-Car H1 (R8A77790)" 114 - select ARCH_RCAR_GEN1 115 - select ARCH_WANT_OPTIONAL_GPIOLIB 116 - select ARM_GIC 117 - 118 - comment "Renesas ARM SoCs Board Type" 119 - 120 - config MACH_BOCKW 121 - bool "BOCK-W platform" 122 - depends on ARCH_R8A7778 123 - select ARCH_REQUIRE_GPIOLIB 124 - select REGULATOR_FIXED_VOLTAGE if REGULATOR 125 - select SND_SOC_AK4554 if SND_SIMPLE_CARD 126 - select SND_SOC_AK4642 if SND_SIMPLE_CARD && I2C 127 - select USE_OF 128 - 129 - config MACH_BOCKW_REFERENCE 130 - bool "BOCK-W - Reference Device Tree Implementation" 131 - depends on ARCH_R8A7778 132 - select ARCH_REQUIRE_GPIOLIB 133 - select REGULATOR_FIXED_VOLTAGE if REGULATOR 134 - select USE_OF 135 - ---help--- 136 - Use reference implementation of BockW board support 137 - which makes use of device tree at the expense 138 - of not supporting a number of devices. 139 - 140 - This is intended to aid developers 141 - 142 - comment "Renesas ARM SoCs System Configuration" 143 - 144 - config CPU_HAS_INTEVT 145 - bool 146 - default y 147 - 148 - config SH_CLK_CPG 149 - bool 150 - 151 - source "drivers/sh/Kconfig" 152 - 153 - endif 154 - 155 - if ARCH_SHMOBILE 156 - 157 - menu "Timer and clock configuration" 158 - 159 - config SHMOBILE_TIMER_HZ 160 - int "Kernel HZ (jiffies per second)" 161 - range 32 1024 162 - default "128" 163 - help 164 - Allows the configuration of the timer frequency. It is customary 165 - to have the timer interrupt run at 1000 Hz or 100 Hz, but in the 166 - case of low timer frequencies other values may be more suitable. 167 - Renesas ARM SoC systems using a 32768 Hz RCLK for clock events may 168 - want to select a HZ value such as 128 that can evenly divide RCLK. 169 - A HZ value that does not divide evenly may cause timer drift. 170 - 171 - endmenu 172 - 173 - endif
+1 -13
arch/arm/mach-shmobile/Makefile
··· 3 3 # 4 4 5 5 # Common objects 6 - obj-y := timer.o console.o 6 + obj-y := timer.o 7 7 8 8 # CPU objects 9 9 obj-$(CONFIG_ARCH_SH73A0) += setup-sh73a0.o ··· 17 17 obj-$(CONFIG_ARCH_R8A7794) += setup-r8a7794.o 18 18 obj-$(CONFIG_ARCH_EMEV2) += setup-emev2.o 19 19 obj-$(CONFIG_ARCH_R7S72100) += setup-r7s72100.o 20 - 21 - # Clock objects 22 - ifndef CONFIG_COMMON_CLK 23 - obj-y += clock.o 24 - obj-$(CONFIG_ARCH_R8A7778) += clock-r8a7778.o 25 - endif 26 20 27 21 # CPU reset vector handling objects 28 22 cpu-y := platsmp.o headsmp.o ··· 42 48 obj-$(CONFIG_PM_RCAR) += pm-rcar.o 43 49 obj-$(CONFIG_PM_RMOBILE) += pm-rmobile.o 44 50 obj-$(CONFIG_ARCH_RCAR_GEN2) += pm-rcar-gen2.o 45 - 46 - # Board objects 47 - ifndef CONFIG_ARCH_SHMOBILE_MULTI 48 - obj-$(CONFIG_MACH_BOCKW) += board-bockw.o 49 - obj-$(CONFIG_MACH_BOCKW_REFERENCE) += board-bockw-reference.o 50 - endif 51 51 52 52 # Framework support 53 53 obj-$(CONFIG_SMP) += $(smp-y)
-12
arch/arm/mach-shmobile/Makefile.boot
··· 1 - # per-board load address for uImage 2 - loadaddr-y := 3 - loadaddr-$(CONFIG_MACH_BOCKW) += 0x60008000 4 - loadaddr-$(CONFIG_MACH_BOCKW_REFERENCE) += 0x60008000 5 - 6 - __ZRELADDR := $(sort $(loadaddr-y)) 7 - zreladdr-y += $(__ZRELADDR) 8 - 9 - # Unsupported legacy stuff 10 - # 11 - #params_phys-y (Instead: Pass atags pointer in r2) 12 - #initrd_phys-y (Instead: Use compiled-in initramfs)
-86
arch/arm/mach-shmobile/board-bockw-reference.c
··· 1 - /* 2 - * Bock-W board support 3 - * 4 - * Copyright (C) 2013 Renesas Solutions Corp. 5 - * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> 6 - * 7 - * This program is free software; you can redistribute it and/or modify 8 - * it under the terms of the GNU General Public License as published by 9 - * the Free Software Foundation; version 2 of the License. 10 - * 11 - * This program is distributed in the hope that it will be useful, 12 - * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 - * GNU General Public License for more details. 15 - */ 16 - 17 - #include <linux/of_platform.h> 18 - 19 - #include <asm/mach/arch.h> 20 - 21 - #include "common.h" 22 - #include "r8a7778.h" 23 - 24 - /* 25 - * see board-bock.c for checking detail of dip-switch 26 - */ 27 - 28 - #define FPGA 0x18200000 29 - #define IRQ0MR 0x30 30 - #define COMCTLR 0x101c 31 - 32 - #define PFC 0xfffc0000 33 - #define PUPR4 0x110 34 - static void __init bockw_init(void) 35 - { 36 - void __iomem *fpga; 37 - void __iomem *pfc; 38 - 39 - #ifndef CONFIG_COMMON_CLK 40 - r8a7778_clock_init(); 41 - #endif 42 - r8a7778_init_irq_extpin_dt(1); 43 - r8a7778_add_dt_devices(); 44 - 45 - fpga = ioremap_nocache(FPGA, SZ_1M); 46 - if (fpga) { 47 - /* 48 - * CAUTION 49 - * 50 - * IRQ0/1 is cascaded interrupt from FPGA. 51 - * it should be cared in the future 52 - * Now, it is assuming IRQ0 was used only from SMSC. 53 - */ 54 - u16 val = ioread16(fpga + IRQ0MR); 55 - val &= ~(1 << 4); /* enable SMSC911x */ 56 - iowrite16(val, fpga + IRQ0MR); 57 - 58 - iounmap(fpga); 59 - } 60 - 61 - pfc = ioremap_nocache(PFC, 0x200); 62 - if (pfc) { 63 - /* 64 - * FIXME 65 - * 66 - * SDHI CD/WP pin needs pull-up 67 - */ 68 - iowrite32(ioread32(pfc + PUPR4) | (3 << 26), pfc + PUPR4); 69 - iounmap(pfc); 70 - } 71 - 72 - of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 73 - } 74 - 75 - static const char *const bockw_boards_compat_dt[] __initconst = { 76 - "renesas,bockw-reference", 77 - NULL, 78 - }; 79 - 80 - DT_MACHINE_START(BOCKW_DT, "bockw") 81 - .init_early = shmobile_init_delay, 82 - .init_irq = r8a7778_init_irq_dt, 83 - .init_machine = bockw_init, 84 - .init_late = shmobile_init_late, 85 - .dt_compat = bockw_boards_compat_dt, 86 - MACHINE_END
-737
arch/arm/mach-shmobile/board-bockw.c
··· 1 - /* 2 - * Bock-W board support 3 - * 4 - * Copyright (C) 2013-2014 Renesas Solutions Corp. 5 - * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> 6 - * Copyright (C) 2013-2014 Cogent Embedded, Inc. 7 - * 8 - * This program is free software; you can redistribute it and/or modify 9 - * it under the terms of the GNU General Public License as published by 10 - * the Free Software Foundation; version 2 of the License. 11 - * 12 - * This program is distributed in the hope that it will be useful, 13 - * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 - * GNU General Public License for more details. 16 - */ 17 - 18 - #include <linux/mfd/tmio.h> 19 - #include <linux/mmc/host.h> 20 - #include <linux/mmc/sh_mobile_sdhi.h> 21 - #include <linux/mmc/sh_mmcif.h> 22 - #include <linux/mtd/partitions.h> 23 - #include <linux/pinctrl/machine.h> 24 - #include <linux/platform_data/camera-rcar.h> 25 - #include <linux/platform_data/usb-rcar-phy.h> 26 - #include <linux/platform_device.h> 27 - #include <linux/regulator/fixed.h> 28 - #include <linux/regulator/machine.h> 29 - #include <linux/smsc911x.h> 30 - #include <linux/spi/spi.h> 31 - #include <linux/spi/flash.h> 32 - #include <linux/usb/renesas_usbhs.h> 33 - 34 - #include <media/soc_camera.h> 35 - #include <asm/mach/arch.h> 36 - #include <sound/rcar_snd.h> 37 - #include <sound/simple_card.h> 38 - 39 - #include "common.h" 40 - #include "irqs.h" 41 - #include "r8a7778.h" 42 - 43 - #define FPGA 0x18200000 44 - #define IRQ0MR 0x30 45 - #define COMCTLR 0x101c 46 - static void __iomem *fpga; 47 - 48 - /* 49 - * CN9(Upper side) SCIF/RCAN selection 50 - * 51 - * 1,4 3,6 52 - * SW40 SCIF RCAN 53 - * SW41 SCIF RCAN 54 - */ 55 - 56 - /* 57 - * MMC (CN26) pin 58 - * 59 - * SW6 (D2) 3 pin 60 - * SW7 (D5) ON 61 - * SW8 (D3) 3 pin 62 - * SW10 (D4) 1 pin 63 - * SW12 (CLK) 1 pin 64 - * SW13 (D6) 3 pin 65 - * SW14 (CMD) ON 66 - * SW15 (D6) 1 pin 67 - * SW16 (D0) ON 68 - * SW17 (D1) ON 69 - * SW18 (D7) 3 pin 70 - * SW19 (MMC) 1 pin 71 - */ 72 - 73 - /* 74 - * SSI settings 75 - * 76 - * SW45: 1-4 side (SSI5 out, ROUT/LOUT CN19 Mid) 77 - * SW46: 1101 (SSI6 Recorde) 78 - * SW47: 1110 (SSI5 Playback) 79 - * SW48: 11 (Recorde power) 80 - * SW49: 1 (SSI slave mode) 81 - * SW50: 1111 (SSI7, SSI8) 82 - * SW51: 1111 (SSI3, SSI4) 83 - * SW54: 1pin (ak4554 FPGA control) 84 - * SW55: 1 (CLKB is 24.5760MHz) 85 - * SW60: 1pin (ak4554 FPGA control) 86 - * SW61: 3pin (use X11 clock) 87 - * SW78: 3-6 (ak4642 connects I2C0) 88 - * 89 - * You can use sound as 90 - * 91 - * hw0: CN19: SSI56-AK4643 92 - * hw1: CN21: SSI3-AK4554(playback) 93 - * hw2: CN21: SSI4-AK4554(capture) 94 - * hw3: CN20: SSI7-AK4554(playback) 95 - * hw4: CN20: SSI8-AK4554(capture) 96 - * 97 - * this command is required when playback on hw0. 98 - * 99 - * # amixer set "LINEOUT Mixer DACL" on 100 - */ 101 - 102 - /* 103 - * USB 104 - * 105 - * USB1 (CN29) can be Host/Function 106 - * 107 - * Host Func 108 - * SW98 1 2 109 - * SW99 1 3 110 - */ 111 - 112 - /* Dummy supplies, where voltage doesn't matter */ 113 - static struct regulator_consumer_supply dummy_supplies[] = { 114 - REGULATOR_SUPPLY("vddvario", "smsc911x"), 115 - REGULATOR_SUPPLY("vdd33a", "smsc911x"), 116 - }; 117 - 118 - static struct regulator_consumer_supply fixed3v3_power_consumers[] = { 119 - REGULATOR_SUPPLY("vmmc", "sh_mmcif"), 120 - REGULATOR_SUPPLY("vqmmc", "sh_mmcif"), 121 - }; 122 - 123 - static struct smsc911x_platform_config smsc911x_data __initdata = { 124 - .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, 125 - .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, 126 - .flags = SMSC911X_USE_32BIT, 127 - .phy_interface = PHY_INTERFACE_MODE_MII, 128 - }; 129 - 130 - static struct resource smsc911x_resources[] __initdata = { 131 - DEFINE_RES_MEM(0x18300000, 0x1000), 132 - DEFINE_RES_IRQ(irq_pin(0)), /* IRQ 0 */ 133 - }; 134 - 135 - #if IS_ENABLED(CONFIG_USB_RENESAS_USBHS_UDC) 136 - /* 137 - * When USB1 is Func 138 - */ 139 - static int usbhsf_get_id(struct platform_device *pdev) 140 - { 141 - return USBHS_GADGET; 142 - } 143 - 144 - #define SUSPMODE 0x102 145 - static int usbhsf_power_ctrl(struct platform_device *pdev, 146 - void __iomem *base, int enable) 147 - { 148 - enable = !!enable; 149 - 150 - r8a7778_usb_phy_power(enable); 151 - 152 - iowrite16(enable << 14, base + SUSPMODE); 153 - 154 - return 0; 155 - } 156 - 157 - static struct resource usbhsf_resources[] __initdata = { 158 - DEFINE_RES_MEM(0xffe60000, 0x110), 159 - DEFINE_RES_IRQ(gic_iid(0x4f)), 160 - }; 161 - 162 - static struct renesas_usbhs_platform_info usbhs_info __initdata = { 163 - .platform_callback = { 164 - .get_id = usbhsf_get_id, 165 - .power_ctrl = usbhsf_power_ctrl, 166 - }, 167 - .driver_param = { 168 - .buswait_bwait = 4, 169 - .d0_tx_id = HPBDMA_SLAVE_USBFUNC_TX, 170 - .d1_rx_id = HPBDMA_SLAVE_USBFUNC_RX, 171 - }, 172 - }; 173 - 174 - #define USB_PHY_SETTING {.port1_func = 1, .ovc_pin[1].active_high = 1,} 175 - #define USB1_DEVICE "renesas_usbhs" 176 - #define ADD_USB_FUNC_DEVICE_IF_POSSIBLE() \ 177 - platform_device_register_resndata( \ 178 - NULL, "renesas_usbhs", -1, \ 179 - usbhsf_resources, \ 180 - ARRAY_SIZE(usbhsf_resources), \ 181 - &usbhs_info, sizeof(struct renesas_usbhs_platform_info)) 182 - 183 - #else 184 - /* 185 - * When USB1 is Host 186 - */ 187 - #define USB_PHY_SETTING { } 188 - #define USB1_DEVICE "ehci-platform" 189 - #define ADD_USB_FUNC_DEVICE_IF_POSSIBLE() 190 - 191 - #endif 192 - 193 - /* USB */ 194 - static struct resource usb_phy_resources[] __initdata = { 195 - DEFINE_RES_MEM(0xffe70800, 0x100), 196 - DEFINE_RES_MEM(0xffe76000, 0x100), 197 - }; 198 - 199 - static struct rcar_phy_platform_data usb_phy_platform_data __initdata = 200 - USB_PHY_SETTING; 201 - 202 - 203 - /* SDHI */ 204 - static struct tmio_mmc_data sdhi0_info __initdata = { 205 - .chan_priv_tx = (void *)HPBDMA_SLAVE_SDHI0_TX, 206 - .chan_priv_rx = (void *)HPBDMA_SLAVE_SDHI0_RX, 207 - .capabilities = MMC_CAP_SD_HIGHSPEED, 208 - .ocr_mask = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34, 209 - .flags = TMIO_MMC_HAS_IDLE_WAIT, 210 - }; 211 - 212 - static struct resource sdhi0_resources[] __initdata = { 213 - DEFINE_RES_MEM(0xFFE4C000, 0x100), 214 - DEFINE_RES_IRQ(gic_iid(0x77)), 215 - }; 216 - 217 - /* Ether */ 218 - static struct resource ether_resources[] __initdata = { 219 - DEFINE_RES_MEM(0xfde00000, 0x400), 220 - DEFINE_RES_IRQ(gic_iid(0x89)), 221 - }; 222 - 223 - static struct sh_eth_plat_data ether_platform_data __initdata = { 224 - .phy = 0x01, 225 - .edmac_endian = EDMAC_LITTLE_ENDIAN, 226 - .phy_interface = PHY_INTERFACE_MODE_RMII, 227 - /* 228 - * Although the LINK signal is available on the board, it's connected to 229 - * the link/activity LED output of the PHY, thus the link disappears and 230 - * reappears after each packet. We'd be better off ignoring such signal 231 - * and getting the link state from the PHY indirectly. 232 - */ 233 - .no_ether_link = 1, 234 - }; 235 - 236 - static struct platform_device_info ether_info __initdata = { 237 - .name = "r8a777x-ether", 238 - .id = -1, 239 - .res = ether_resources, 240 - .num_res = ARRAY_SIZE(ether_resources), 241 - .data = &ether_platform_data, 242 - .size_data = sizeof(ether_platform_data), 243 - .dma_mask = DMA_BIT_MASK(32), 244 - }; 245 - 246 - /* I2C */ 247 - static struct i2c_board_info i2c0_devices[] = { 248 - { 249 - I2C_BOARD_INFO("rx8581", 0x51), 250 - }, { 251 - I2C_BOARD_INFO("ak4643", 0x12), 252 - } 253 - }; 254 - 255 - /* HSPI*/ 256 - static struct mtd_partition m25p80_spi_flash_partitions[] = { 257 - { 258 - .name = "data(spi)", 259 - .size = 0x0100000, 260 - .offset = 0, 261 - }, 262 - }; 263 - 264 - static struct flash_platform_data spi_flash_data = { 265 - .name = "m25p80", 266 - .type = "s25fl008k", 267 - .parts = m25p80_spi_flash_partitions, 268 - .nr_parts = ARRAY_SIZE(m25p80_spi_flash_partitions), 269 - }; 270 - 271 - static struct spi_board_info spi_board_info[] __initdata = { 272 - { 273 - .modalias = "m25p80", 274 - .max_speed_hz = 104000000, 275 - .chip_select = 0, 276 - .bus_num = 0, 277 - .mode = SPI_MODE_0, 278 - .platform_data = &spi_flash_data, 279 - }, 280 - }; 281 - 282 - /* MMC */ 283 - static struct resource mmc_resources[] __initdata = { 284 - DEFINE_RES_MEM(0xffe4e000, 0x100), 285 - DEFINE_RES_IRQ(gic_iid(0x5d)), 286 - }; 287 - 288 - static struct sh_mmcif_plat_data sh_mmcif_plat __initdata = { 289 - .sup_pclk = 0, 290 - .caps = MMC_CAP_4_BIT_DATA | 291 - MMC_CAP_8_BIT_DATA | 292 - MMC_CAP_NEEDS_POLL, 293 - }; 294 - 295 - /* In the default configuration both decoders reside on I2C bus 0 */ 296 - #define BOCKW_CAMERA(idx) \ 297 - static struct i2c_board_info camera##idx##_info = { \ 298 - I2C_BOARD_INFO("ml86v7667", 0x41 + 2 * (idx)), \ 299 - }; \ 300 - \ 301 - static struct soc_camera_link iclink##idx##_ml86v7667 __initdata = { \ 302 - .bus_id = idx, \ 303 - .i2c_adapter_id = 0, \ 304 - .board_info = &camera##idx##_info, \ 305 - } 306 - 307 - BOCKW_CAMERA(0); 308 - BOCKW_CAMERA(1); 309 - 310 - /* VIN */ 311 - static struct rcar_vin_platform_data vin_platform_data __initdata = { 312 - .flags = RCAR_VIN_BT656, 313 - }; 314 - 315 - #define R8A7778_VIN(idx) \ 316 - static struct resource vin##idx##_resources[] __initdata = { \ 317 - DEFINE_RES_MEM(0xffc50000 + 0x1000 * (idx), 0x1000), \ 318 - DEFINE_RES_IRQ(gic_iid(0x5a)), \ 319 - }; \ 320 - \ 321 - static struct platform_device_info vin##idx##_info __initdata = { \ 322 - .name = "r8a7778-vin", \ 323 - .id = idx, \ 324 - .res = vin##idx##_resources, \ 325 - .num_res = ARRAY_SIZE(vin##idx##_resources), \ 326 - .dma_mask = DMA_BIT_MASK(32), \ 327 - .data = &vin_platform_data, \ 328 - .size_data = sizeof(vin_platform_data), \ 329 - } 330 - R8A7778_VIN(0); 331 - R8A7778_VIN(1); 332 - 333 - /* Sound */ 334 - static struct resource rsnd_resources[] __initdata = { 335 - [RSND_GEN1_SRU] = DEFINE_RES_MEM(0xffd90000, 0x1000), 336 - [RSND_GEN1_SSI] = DEFINE_RES_MEM(0xffd91000, 0x1240), 337 - [RSND_GEN1_ADG] = DEFINE_RES_MEM(0xfffe0000, 0x24), 338 - }; 339 - 340 - static struct rsnd_ssi_platform_info rsnd_ssi[] = { 341 - RSND_SSI_UNUSED, /* SSI 0 */ 342 - RSND_SSI_UNUSED, /* SSI 1 */ 343 - RSND_SSI_UNUSED, /* SSI 2 */ 344 - RSND_SSI(HPBDMA_SLAVE_HPBIF3_TX, gic_iid(0x85), 0), 345 - RSND_SSI(HPBDMA_SLAVE_HPBIF4_RX, gic_iid(0x85), RSND_SSI_CLK_PIN_SHARE), 346 - RSND_SSI(HPBDMA_SLAVE_HPBIF5_TX, gic_iid(0x86), 0), 347 - RSND_SSI(HPBDMA_SLAVE_HPBIF6_RX, gic_iid(0x86), 0), 348 - RSND_SSI(HPBDMA_SLAVE_HPBIF7_TX, gic_iid(0x86), 0), 349 - RSND_SSI(HPBDMA_SLAVE_HPBIF8_RX, gic_iid(0x86), RSND_SSI_CLK_PIN_SHARE), 350 - }; 351 - 352 - static struct rsnd_src_platform_info rsnd_src[9] = { 353 - RSND_SRC_UNUSED, /* SRU 0 */ 354 - RSND_SRC_UNUSED, /* SRU 1 */ 355 - RSND_SRC_UNUSED, /* SRU 2 */ 356 - RSND_SRC(0, 0), 357 - RSND_SRC(0, 0), 358 - RSND_SRC(0, 0), 359 - RSND_SRC(0, 0), 360 - RSND_SRC(0, 0), 361 - RSND_SRC(0, 0), 362 - }; 363 - 364 - static struct rsnd_dai_platform_info rsnd_dai[] = { 365 - { 366 - .playback = { .ssi = &rsnd_ssi[5], .src = &rsnd_src[5] }, 367 - .capture = { .ssi = &rsnd_ssi[6], .src = &rsnd_src[6] }, 368 - }, { 369 - .playback = { .ssi = &rsnd_ssi[3], .src = &rsnd_src[3] }, 370 - }, { 371 - .capture = { .ssi = &rsnd_ssi[4], .src = &rsnd_src[4] }, 372 - }, { 373 - .playback = { .ssi = &rsnd_ssi[7], .src = &rsnd_src[7] }, 374 - }, { 375 - .capture = { .ssi = &rsnd_ssi[8], .src = &rsnd_src[8] }, 376 - }, 377 - }; 378 - 379 - enum { 380 - AK4554_34 = 0, 381 - AK4643_56, 382 - AK4554_78, 383 - SOUND_MAX, 384 - }; 385 - 386 - static int rsnd_codec_power(int id, int enable) 387 - { 388 - static int sound_user[SOUND_MAX] = {0, 0, 0}; 389 - int *usr = NULL; 390 - u32 bit; 391 - 392 - switch (id) { 393 - case 3: 394 - case 4: 395 - usr = sound_user + AK4554_34; 396 - bit = (1 << 10); 397 - break; 398 - case 5: 399 - case 6: 400 - usr = sound_user + AK4643_56; 401 - bit = (1 << 6); 402 - break; 403 - case 7: 404 - case 8: 405 - usr = sound_user + AK4554_78; 406 - bit = (1 << 7); 407 - break; 408 - } 409 - 410 - if (!usr) 411 - return -EIO; 412 - 413 - if (enable) { 414 - if (*usr == 0) { 415 - u32 val = ioread16(fpga + COMCTLR); 416 - val &= ~bit; 417 - iowrite16(val, fpga + COMCTLR); 418 - } 419 - 420 - (*usr)++; 421 - } else { 422 - if (*usr == 0) 423 - return 0; 424 - 425 - (*usr)--; 426 - 427 - if (*usr == 0) { 428 - u32 val = ioread16(fpga + COMCTLR); 429 - val |= bit; 430 - iowrite16(val, fpga + COMCTLR); 431 - } 432 - } 433 - 434 - return 0; 435 - } 436 - 437 - static int rsnd_start(int id) 438 - { 439 - return rsnd_codec_power(id, 1); 440 - } 441 - 442 - static int rsnd_stop(int id) 443 - { 444 - return rsnd_codec_power(id, 0); 445 - } 446 - 447 - static struct rcar_snd_info rsnd_info = { 448 - .flags = RSND_GEN1, 449 - .ssi_info = rsnd_ssi, 450 - .ssi_info_nr = ARRAY_SIZE(rsnd_ssi), 451 - .src_info = rsnd_src, 452 - .src_info_nr = ARRAY_SIZE(rsnd_src), 453 - .dai_info = rsnd_dai, 454 - .dai_info_nr = ARRAY_SIZE(rsnd_dai), 455 - .start = rsnd_start, 456 - .stop = rsnd_stop, 457 - }; 458 - 459 - static struct asoc_simple_card_info rsnd_card_info[] = { 460 - /* SSI5, SSI6 */ 461 - { 462 - .name = "AK4643", 463 - .card = "SSI56-AK4643", 464 - .codec = "ak4642-codec.0-0012", 465 - .platform = "rcar_sound", 466 - .daifmt = SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_CBM_CFM, 467 - .cpu_dai = { 468 - .name = "rsnd-dai.0", 469 - }, 470 - .codec_dai = { 471 - .name = "ak4642-hifi", 472 - .sysclk = 11289600, 473 - }, 474 - }, 475 - /* SSI3 */ 476 - { 477 - .name = "AK4554", 478 - .card = "SSI3-AK4554(playback)", 479 - .codec = "ak4554-adc-dac.0", 480 - .platform = "rcar_sound", 481 - .daifmt = SND_SOC_DAIFMT_CBS_CFS | SND_SOC_DAIFMT_RIGHT_J, 482 - .cpu_dai = { 483 - .name = "rsnd-dai.1", 484 - }, 485 - .codec_dai = { 486 - .name = "ak4554-hifi", 487 - }, 488 - }, 489 - /* SSI4 */ 490 - { 491 - .name = "AK4554", 492 - .card = "SSI4-AK4554(capture)", 493 - .codec = "ak4554-adc-dac.0", 494 - .platform = "rcar_sound", 495 - .daifmt = SND_SOC_DAIFMT_CBS_CFS | SND_SOC_DAIFMT_LEFT_J, 496 - .cpu_dai = { 497 - .name = "rsnd-dai.2", 498 - }, 499 - .codec_dai = { 500 - .name = "ak4554-hifi", 501 - }, 502 - }, 503 - /* SSI7 */ 504 - { 505 - .name = "AK4554", 506 - .card = "SSI7-AK4554(playback)", 507 - .codec = "ak4554-adc-dac.1", 508 - .platform = "rcar_sound", 509 - .daifmt = SND_SOC_DAIFMT_CBS_CFS | SND_SOC_DAIFMT_RIGHT_J, 510 - .cpu_dai = { 511 - .name = "rsnd-dai.3", 512 - }, 513 - .codec_dai = { 514 - .name = "ak4554-hifi", 515 - }, 516 - }, 517 - /* SSI8 */ 518 - { 519 - .name = "AK4554", 520 - .card = "SSI8-AK4554(capture)", 521 - .codec = "ak4554-adc-dac.1", 522 - .platform = "rcar_sound", 523 - .daifmt = SND_SOC_DAIFMT_CBS_CFS | SND_SOC_DAIFMT_LEFT_J, 524 - .cpu_dai = { 525 - .name = "rsnd-dai.4", 526 - }, 527 - .codec_dai = { 528 - .name = "ak4554-hifi", 529 - }, 530 - } 531 - }; 532 - 533 - static const struct pinctrl_map bockw_pinctrl_map[] = { 534 - /* AUDIO */ 535 - PIN_MAP_MUX_GROUP_DEFAULT("rcar_sound", "pfc-r8a7778", 536 - "audio_clk_a", "audio_clk"), 537 - PIN_MAP_MUX_GROUP_DEFAULT("rcar_sound", "pfc-r8a7778", 538 - "audio_clk_b", "audio_clk"), 539 - PIN_MAP_MUX_GROUP_DEFAULT("rcar_sound", "pfc-r8a7778", 540 - "ssi34_ctrl", "ssi"), 541 - PIN_MAP_MUX_GROUP_DEFAULT("rcar_sound", "pfc-r8a7778", 542 - "ssi3_data", "ssi"), 543 - PIN_MAP_MUX_GROUP_DEFAULT("rcar_sound", "pfc-r8a7778", 544 - "ssi4_data", "ssi"), 545 - PIN_MAP_MUX_GROUP_DEFAULT("rcar_sound", "pfc-r8a7778", 546 - "ssi5_ctrl", "ssi"), 547 - PIN_MAP_MUX_GROUP_DEFAULT("rcar_sound", "pfc-r8a7778", 548 - "ssi5_data", "ssi"), 549 - PIN_MAP_MUX_GROUP_DEFAULT("rcar_sound", "pfc-r8a7778", 550 - "ssi6_ctrl", "ssi"), 551 - PIN_MAP_MUX_GROUP_DEFAULT("rcar_sound", "pfc-r8a7778", 552 - "ssi6_data", "ssi"), 553 - PIN_MAP_MUX_GROUP_DEFAULT("rcar_sound", "pfc-r8a7778", 554 - "ssi78_ctrl", "ssi"), 555 - PIN_MAP_MUX_GROUP_DEFAULT("rcar_sound", "pfc-r8a7778", 556 - "ssi7_data", "ssi"), 557 - PIN_MAP_MUX_GROUP_DEFAULT("rcar_sound", "pfc-r8a7778", 558 - "ssi8_data", "ssi"), 559 - /* Ether */ 560 - PIN_MAP_MUX_GROUP_DEFAULT("r8a777x-ether", "pfc-r8a7778", 561 - "ether_rmii", "ether"), 562 - /* HSPI0 */ 563 - PIN_MAP_MUX_GROUP_DEFAULT("sh-hspi.0", "pfc-r8a7778", 564 - "hspi0_a", "hspi0"), 565 - /* MMC */ 566 - PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif", "pfc-r8a7778", 567 - "mmc_data8", "mmc"), 568 - PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif", "pfc-r8a7778", 569 - "mmc_ctrl", "mmc"), 570 - /* SCIF0 */ 571 - PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-r8a7778", 572 - "scif0_data_a", "scif0"), 573 - PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-r8a7778", 574 - "scif0_ctrl", "scif0"), 575 - /* USB */ 576 - PIN_MAP_MUX_GROUP_DEFAULT("ehci-platform", "pfc-r8a7778", 577 - "usb0", "usb0"), 578 - PIN_MAP_MUX_GROUP_DEFAULT(USB1_DEVICE, "pfc-r8a7778", 579 - "usb1", "usb1"), 580 - /* SDHI0 */ 581 - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7778", 582 - "sdhi0_data4", "sdhi0"), 583 - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7778", 584 - "sdhi0_ctrl", "sdhi0"), 585 - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7778", 586 - "sdhi0_cd", "sdhi0"), 587 - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7778", 588 - "sdhi0_wp", "sdhi0"), 589 - /* VIN0 */ 590 - PIN_MAP_MUX_GROUP_DEFAULT("r8a7778-vin.0", "pfc-r8a7778", 591 - "vin0_clk", "vin0"), 592 - PIN_MAP_MUX_GROUP_DEFAULT("r8a7778-vin.0", "pfc-r8a7778", 593 - "vin0_data8", "vin0"), 594 - /* VIN1 */ 595 - PIN_MAP_MUX_GROUP_DEFAULT("r8a7778-vin.1", "pfc-r8a7778", 596 - "vin1_clk", "vin1"), 597 - PIN_MAP_MUX_GROUP_DEFAULT("r8a7778-vin.1", "pfc-r8a7778", 598 - "vin1_data8", "vin1"), 599 - }; 600 - 601 - #define PFC 0xfffc0000 602 - #define PUPR4 0x110 603 - static void __init bockw_init(void) 604 - { 605 - void __iomem *base; 606 - struct clk *clk; 607 - struct platform_device *pdev; 608 - int i; 609 - 610 - r8a7778_clock_init(); 611 - r8a7778_init_irq_extpin(1); 612 - r8a7778_add_standard_devices(); 613 - 614 - platform_device_register_full(&ether_info); 615 - 616 - platform_device_register_full(&vin0_info); 617 - /* VIN1 has a pin conflict with Ether */ 618 - if (!IS_ENABLED(CONFIG_SH_ETH)) 619 - platform_device_register_full(&vin1_info); 620 - platform_device_register_data(NULL, "soc-camera-pdrv", 0, 621 - &iclink0_ml86v7667, 622 - sizeof(iclink0_ml86v7667)); 623 - platform_device_register_data(NULL, "soc-camera-pdrv", 1, 624 - &iclink1_ml86v7667, 625 - sizeof(iclink1_ml86v7667)); 626 - 627 - i2c_register_board_info(0, i2c0_devices, 628 - ARRAY_SIZE(i2c0_devices)); 629 - spi_register_board_info(spi_board_info, 630 - ARRAY_SIZE(spi_board_info)); 631 - pinctrl_register_mappings(bockw_pinctrl_map, 632 - ARRAY_SIZE(bockw_pinctrl_map)); 633 - r8a7778_pinmux_init(); 634 - 635 - platform_device_register_resndata( 636 - NULL, "sh_mmcif", -1, 637 - mmc_resources, ARRAY_SIZE(mmc_resources), 638 - &sh_mmcif_plat, sizeof(struct sh_mmcif_plat_data)); 639 - 640 - platform_device_register_resndata( 641 - NULL, "rcar_usb_phy", -1, 642 - usb_phy_resources, 643 - ARRAY_SIZE(usb_phy_resources), 644 - &usb_phy_platform_data, 645 - sizeof(struct rcar_phy_platform_data)); 646 - 647 - regulator_register_fixed(0, dummy_supplies, 648 - ARRAY_SIZE(dummy_supplies)); 649 - regulator_register_always_on(1, "fixed-3.3V", fixed3v3_power_consumers, 650 - ARRAY_SIZE(fixed3v3_power_consumers), 3300000); 651 - 652 - /* for SMSC */ 653 - fpga = ioremap_nocache(FPGA, SZ_1M); 654 - if (fpga) { 655 - /* 656 - * CAUTION 657 - * 658 - * IRQ0/1 is cascaded interrupt from FPGA. 659 - * it should be cared in the future 660 - * Now, it is assuming IRQ0 was used only from SMSC. 661 - */ 662 - u16 val = ioread16(fpga + IRQ0MR); 663 - val &= ~(1 << 4); /* enable SMSC911x */ 664 - iowrite16(val, fpga + IRQ0MR); 665 - 666 - platform_device_register_resndata( 667 - NULL, "smsc911x", -1, 668 - smsc911x_resources, ARRAY_SIZE(smsc911x_resources), 669 - &smsc911x_data, sizeof(smsc911x_data)); 670 - } 671 - 672 - /* for SDHI */ 673 - base = ioremap_nocache(PFC, 0x200); 674 - if (base) { 675 - /* 676 - * FIXME 677 - * 678 - * SDHI CD/WP pin needs pull-up 679 - */ 680 - iowrite32(ioread32(base + PUPR4) | (3 << 26), base + PUPR4); 681 - iounmap(base); 682 - 683 - platform_device_register_resndata( 684 - NULL, "sh_mobile_sdhi", 0, 685 - sdhi0_resources, ARRAY_SIZE(sdhi0_resources), 686 - &sdhi0_info, sizeof(struct tmio_mmc_data)); 687 - } 688 - 689 - /* for Audio */ 690 - rsnd_codec_power(5, 1); /* enable ak4642 */ 691 - 692 - platform_device_register_simple( 693 - "ak4554-adc-dac", 0, NULL, 0); 694 - 695 - platform_device_register_simple( 696 - "ak4554-adc-dac", 1, NULL, 0); 697 - 698 - pdev = platform_device_register_resndata( 699 - NULL, "rcar_sound", -1, 700 - rsnd_resources, ARRAY_SIZE(rsnd_resources), 701 - &rsnd_info, sizeof(rsnd_info)); 702 - 703 - clk = clk_get(&pdev->dev, "clk_b"); 704 - clk_set_rate(clk, 24576000); 705 - clk_put(clk); 706 - 707 - for (i = 0; i < ARRAY_SIZE(rsnd_card_info); i++) { 708 - struct platform_device_info cardinfo = { 709 - .name = "asoc-simple-card", 710 - .id = i, 711 - .data = &rsnd_card_info[i], 712 - .size_data = sizeof(struct asoc_simple_card_info), 713 - .dma_mask = DMA_BIT_MASK(32), 714 - }; 715 - 716 - platform_device_register_full(&cardinfo); 717 - } 718 - } 719 - 720 - static void __init bockw_init_late(void) 721 - { 722 - r8a7778_init_late(); 723 - ADD_USB_FUNC_DEVICE_IF_POSSIBLE(); 724 - } 725 - 726 - static const char *const bockw_boards_compat_dt[] __initconst = { 727 - "renesas,bockw", 728 - NULL, 729 - }; 730 - 731 - DT_MACHINE_START(BOCKW_DT, "bockw") 732 - .init_early = shmobile_init_delay, 733 - .init_irq = r8a7778_init_irq_dt, 734 - .init_machine = bockw_init, 735 - .dt_compat = bockw_boards_compat_dt, 736 - .init_late = bockw_init_late, 737 - MACHINE_END
-342
arch/arm/mach-shmobile/clock-r8a7778.c
··· 1 - /* 2 - * r8a7778 clock framework support 3 - * 4 - * Copyright (C) 2013 Renesas Solutions Corp. 5 - * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> 6 - * 7 - * based on r8a7779 8 - * 9 - * Copyright (C) 2011 Renesas Solutions Corp. 10 - * Copyright (C) 2011 Magnus Damm 11 - * 12 - * This program is free software; you can redistribute it and/or modify 13 - * it under the terms of the GNU General Public License as published by 14 - * the Free Software Foundation; either version 2 of the License 15 - * 16 - * This program is distributed in the hope that it will be useful, 17 - * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 - * GNU General Public License for more details. 20 - */ 21 - 22 - /* 23 - * MD MD MD MD PLLA PLLB EXTAL clki clkz 24 - * 19 18 12 11 (HMz) (MHz) (MHz) 25 - *---------------------------------------------------------------------------- 26 - * 1 0 0 0 x21 x21 38.00 800 800 27 - * 1 0 0 1 x24 x24 33.33 800 800 28 - * 1 0 1 0 x28 x28 28.50 800 800 29 - * 1 0 1 1 x32 x32 25.00 800 800 30 - * 1 1 0 1 x24 x21 33.33 800 700 31 - * 1 1 1 0 x28 x21 28.50 800 600 32 - * 1 1 1 1 x32 x24 25.00 800 600 33 - */ 34 - 35 - #include <linux/io.h> 36 - #include <linux/sh_clk.h> 37 - #include <linux/clkdev.h> 38 - #include "clock.h" 39 - #include "common.h" 40 - 41 - #define MSTPCR0 IOMEM(0xffc80030) 42 - #define MSTPCR1 IOMEM(0xffc80034) 43 - #define MSTPCR3 IOMEM(0xffc8003c) 44 - #define MSTPSR1 IOMEM(0xffc80044) 45 - #define MSTPSR4 IOMEM(0xffc80048) 46 - #define MSTPSR6 IOMEM(0xffc8004c) 47 - #define MSTPCR4 IOMEM(0xffc80050) 48 - #define MSTPCR5 IOMEM(0xffc80054) 49 - #define MSTPCR6 IOMEM(0xffc80058) 50 - #define MODEMR 0xFFCC0020 51 - 52 - #define MD(nr) BIT(nr) 53 - 54 - /* ioremap() through clock mapping mandatory to avoid 55 - * collision with ARM coherent DMA virtual memory range. 56 - */ 57 - 58 - static struct clk_mapping cpg_mapping = { 59 - .phys = 0xffc80000, 60 - .len = 0x80, 61 - }; 62 - 63 - static struct clk extal_clk = { 64 - /* .rate will be updated on r8a7778_clock_init() */ 65 - .mapping = &cpg_mapping, 66 - }; 67 - 68 - static struct clk audio_clk_a = { 69 - }; 70 - 71 - static struct clk audio_clk_b = { 72 - }; 73 - 74 - static struct clk audio_clk_c = { 75 - }; 76 - 77 - /* 78 - * clock ratio of these clock will be updated 79 - * on r8a7778_clock_init() 80 - */ 81 - SH_FIXED_RATIO_CLK_SET(plla_clk, extal_clk, 1, 1); 82 - SH_FIXED_RATIO_CLK_SET(pllb_clk, extal_clk, 1, 1); 83 - SH_FIXED_RATIO_CLK_SET(i_clk, plla_clk, 1, 1); 84 - SH_FIXED_RATIO_CLK_SET(s_clk, plla_clk, 1, 1); 85 - SH_FIXED_RATIO_CLK_SET(s1_clk, plla_clk, 1, 1); 86 - SH_FIXED_RATIO_CLK_SET(s3_clk, plla_clk, 1, 1); 87 - SH_FIXED_RATIO_CLK_SET(s4_clk, plla_clk, 1, 1); 88 - SH_FIXED_RATIO_CLK_SET(b_clk, plla_clk, 1, 1); 89 - SH_FIXED_RATIO_CLK_SET(out_clk, plla_clk, 1, 1); 90 - SH_FIXED_RATIO_CLK_SET(p_clk, plla_clk, 1, 1); 91 - SH_FIXED_RATIO_CLK_SET(g_clk, plla_clk, 1, 1); 92 - SH_FIXED_RATIO_CLK_SET(z_clk, pllb_clk, 1, 1); 93 - 94 - static struct clk *main_clks[] = { 95 - &extal_clk, 96 - &plla_clk, 97 - &pllb_clk, 98 - &i_clk, 99 - &s_clk, 100 - &s1_clk, 101 - &s3_clk, 102 - &s4_clk, 103 - &b_clk, 104 - &out_clk, 105 - &p_clk, 106 - &g_clk, 107 - &z_clk, 108 - &audio_clk_a, 109 - &audio_clk_b, 110 - &audio_clk_c, 111 - }; 112 - 113 - enum { 114 - MSTP531, MSTP530, 115 - MSTP529, MSTP528, MSTP527, MSTP526, MSTP525, MSTP524, MSTP523, 116 - MSTP331, 117 - MSTP323, MSTP322, MSTP321, 118 - MSTP311, MSTP310, 119 - MSTP309, MSTP308, MSTP307, 120 - MSTP114, 121 - MSTP110, MSTP109, 122 - MSTP100, 123 - MSTP030, 124 - MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021, 125 - MSTP016, MSTP015, MSTP012, MSTP011, MSTP010, 126 - MSTP009, MSTP008, MSTP007, 127 - MSTP_NR }; 128 - 129 - static struct clk mstp_clks[MSTP_NR] = { 130 - [MSTP531] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 31, 0), /* SCU0 */ 131 - [MSTP530] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 30, 0), /* SCU1 */ 132 - [MSTP529] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 29, 0), /* SCU2 */ 133 - [MSTP528] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 28, 0), /* SCU3 */ 134 - [MSTP527] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 27, 0), /* SCU4 */ 135 - [MSTP526] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 26, 0), /* SCU5 */ 136 - [MSTP525] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 25, 0), /* SCU6 */ 137 - [MSTP524] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 24, 0), /* SCU7 */ 138 - [MSTP523] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 23, 0), /* SCU8 */ 139 - [MSTP331] = SH_CLK_MSTP32(&s4_clk, MSTPCR3, 31, 0), /* MMC */ 140 - [MSTP323] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 23, 0), /* SDHI0 */ 141 - [MSTP322] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 22, 0), /* SDHI1 */ 142 - [MSTP321] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 21, 0), /* SDHI2 */ 143 - [MSTP311] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 11, 0), /* SSI4 */ 144 - [MSTP310] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 10, 0), /* SSI5 */ 145 - [MSTP309] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 9, 0), /* SSI6 */ 146 - [MSTP308] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 8, 0), /* SSI7 */ 147 - [MSTP307] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 7, 0), /* SSI8 */ 148 - [MSTP114] = SH_CLK_MSTP32(&p_clk, MSTPCR1, 14, 0), /* Ether */ 149 - [MSTP110] = SH_CLK_MSTP32(&s_clk, MSTPCR1, 10, 0), /* VIN0 */ 150 - [MSTP109] = SH_CLK_MSTP32(&s_clk, MSTPCR1, 9, 0), /* VIN1 */ 151 - [MSTP100] = SH_CLK_MSTP32(&p_clk, MSTPCR1, 0, 0), /* USB0/1 */ 152 - [MSTP030] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 30, 0), /* I2C0 */ 153 - [MSTP029] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 29, 0), /* I2C1 */ 154 - [MSTP028] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 28, 0), /* I2C2 */ 155 - [MSTP027] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 27, 0), /* I2C3 */ 156 - [MSTP026] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 26, 0), /* SCIF0 */ 157 - [MSTP025] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 25, 0), /* SCIF1 */ 158 - [MSTP024] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 24, 0), /* SCIF2 */ 159 - [MSTP023] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 23, 0), /* SCIF3 */ 160 - [MSTP022] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 22, 0), /* SCIF4 */ 161 - [MSTP021] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 21, 0), /* SCIF5 */ 162 - [MSTP016] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 16, 0), /* TMU0 */ 163 - [MSTP015] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 15, 0), /* TMU1 */ 164 - [MSTP012] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 12, 0), /* SSI0 */ 165 - [MSTP011] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 11, 0), /* SSI1 */ 166 - [MSTP010] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 10, 0), /* SSI2 */ 167 - [MSTP009] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 9, 0), /* SSI3 */ 168 - [MSTP008] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 8, 0), /* SRU */ 169 - [MSTP007] = SH_CLK_MSTP32(&s_clk, MSTPCR0, 7, 0), /* HSPI */ 170 - }; 171 - 172 - static struct clk_lookup lookups[] = { 173 - /* main */ 174 - CLKDEV_CON_ID("shyway_clk", &s_clk), 175 - CLKDEV_CON_ID("peripheral_clk", &p_clk), 176 - 177 - /* MSTP32 clocks */ 178 - CLKDEV_DEV_ID("sh_mmcif", &mstp_clks[MSTP331]), /* MMC */ 179 - CLKDEV_DEV_ID("ffe4e000.mmc", &mstp_clks[MSTP331]), /* MMC */ 180 - CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP323]), /* SDHI0 */ 181 - CLKDEV_DEV_ID("ffe4c000.sd", &mstp_clks[MSTP323]), /* SDHI0 */ 182 - CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */ 183 - CLKDEV_DEV_ID("ffe4d000.sd", &mstp_clks[MSTP322]), /* SDHI1 */ 184 - CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */ 185 - CLKDEV_DEV_ID("ffe4f000.sd", &mstp_clks[MSTP321]), /* SDHI2 */ 186 - CLKDEV_DEV_ID("r8a777x-ether", &mstp_clks[MSTP114]), /* Ether */ 187 - CLKDEV_DEV_ID("r8a7778-vin.0", &mstp_clks[MSTP110]), /* VIN0 */ 188 - CLKDEV_DEV_ID("r8a7778-vin.1", &mstp_clks[MSTP109]), /* VIN1 */ 189 - CLKDEV_DEV_ID("ehci-platform", &mstp_clks[MSTP100]), /* USB EHCI port0/1 */ 190 - CLKDEV_DEV_ID("ohci-platform", &mstp_clks[MSTP100]), /* USB OHCI port0/1 */ 191 - CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP100]), /* USB FUNC */ 192 - CLKDEV_DEV_ID("i2c-rcar.0", &mstp_clks[MSTP030]), /* I2C0 */ 193 - CLKDEV_DEV_ID("ffc70000.i2c", &mstp_clks[MSTP030]), /* I2C0 */ 194 - CLKDEV_DEV_ID("i2c-rcar.1", &mstp_clks[MSTP029]), /* I2C1 */ 195 - CLKDEV_DEV_ID("ffc71000.i2c", &mstp_clks[MSTP029]), /* I2C1 */ 196 - CLKDEV_DEV_ID("i2c-rcar.2", &mstp_clks[MSTP028]), /* I2C2 */ 197 - CLKDEV_DEV_ID("ffc72000.i2c", &mstp_clks[MSTP028]), /* I2C2 */ 198 - CLKDEV_DEV_ID("i2c-rcar.3", &mstp_clks[MSTP027]), /* I2C3 */ 199 - CLKDEV_DEV_ID("ffc73000.i2c", &mstp_clks[MSTP027]), /* I2C3 */ 200 - CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP026]), /* SCIF0 */ 201 - CLKDEV_DEV_ID("ffe40000.serial", &mstp_clks[MSTP026]), /* SCIF0 */ 202 - CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP025]), /* SCIF1 */ 203 - CLKDEV_DEV_ID("ffe41000.serial", &mstp_clks[MSTP025]), /* SCIF1 */ 204 - CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP024]), /* SCIF2 */ 205 - CLKDEV_DEV_ID("ffe42000.serial", &mstp_clks[MSTP024]), /* SCIF2 */ 206 - CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP023]), /* SCIF3 */ 207 - CLKDEV_DEV_ID("ffe43000.serial", &mstp_clks[MSTP023]), /* SCIF3 */ 208 - CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP022]), /* SCIF4 */ 209 - CLKDEV_DEV_ID("ffe44000.serial", &mstp_clks[MSTP022]), /* SCIF4 */ 210 - CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP021]), /* SCIF6 */ 211 - CLKDEV_DEV_ID("ffe45000.serial", &mstp_clks[MSTP021]), /* SCIF5 */ 212 - CLKDEV_DEV_ID("sh-hspi.0", &mstp_clks[MSTP007]), /* HSPI0 */ 213 - CLKDEV_DEV_ID("fffc7000.spi", &mstp_clks[MSTP007]), /* HSPI0 */ 214 - CLKDEV_DEV_ID("sh-hspi.1", &mstp_clks[MSTP007]), /* HSPI1 */ 215 - CLKDEV_DEV_ID("fffc8000.spi", &mstp_clks[MSTP007]), /* HSPI1 */ 216 - CLKDEV_DEV_ID("sh-hspi.2", &mstp_clks[MSTP007]), /* HSPI2 */ 217 - CLKDEV_DEV_ID("fffc6000.spi", &mstp_clks[MSTP007]), /* HSPI2 */ 218 - CLKDEV_DEV_ID("rcar_sound", &mstp_clks[MSTP008]), /* SRU */ 219 - 220 - CLKDEV_ICK_ID("clk_a", "rcar_sound", &audio_clk_a), 221 - CLKDEV_ICK_ID("clk_b", "rcar_sound", &audio_clk_b), 222 - CLKDEV_ICK_ID("clk_c", "rcar_sound", &audio_clk_c), 223 - CLKDEV_ICK_ID("clk_i", "rcar_sound", &s1_clk), 224 - CLKDEV_ICK_ID("ssi.0", "rcar_sound", &mstp_clks[MSTP012]), 225 - CLKDEV_ICK_ID("ssi.1", "rcar_sound", &mstp_clks[MSTP011]), 226 - CLKDEV_ICK_ID("ssi.2", "rcar_sound", &mstp_clks[MSTP010]), 227 - CLKDEV_ICK_ID("ssi.3", "rcar_sound", &mstp_clks[MSTP009]), 228 - CLKDEV_ICK_ID("ssi.4", "rcar_sound", &mstp_clks[MSTP311]), 229 - CLKDEV_ICK_ID("ssi.5", "rcar_sound", &mstp_clks[MSTP310]), 230 - CLKDEV_ICK_ID("ssi.6", "rcar_sound", &mstp_clks[MSTP309]), 231 - CLKDEV_ICK_ID("ssi.7", "rcar_sound", &mstp_clks[MSTP308]), 232 - CLKDEV_ICK_ID("ssi.8", "rcar_sound", &mstp_clks[MSTP307]), 233 - CLKDEV_ICK_ID("src.0", "rcar_sound", &mstp_clks[MSTP531]), 234 - CLKDEV_ICK_ID("src.1", "rcar_sound", &mstp_clks[MSTP530]), 235 - CLKDEV_ICK_ID("src.2", "rcar_sound", &mstp_clks[MSTP529]), 236 - CLKDEV_ICK_ID("src.3", "rcar_sound", &mstp_clks[MSTP528]), 237 - CLKDEV_ICK_ID("src.4", "rcar_sound", &mstp_clks[MSTP527]), 238 - CLKDEV_ICK_ID("src.5", "rcar_sound", &mstp_clks[MSTP526]), 239 - CLKDEV_ICK_ID("src.6", "rcar_sound", &mstp_clks[MSTP525]), 240 - CLKDEV_ICK_ID("src.7", "rcar_sound", &mstp_clks[MSTP524]), 241 - CLKDEV_ICK_ID("src.8", "rcar_sound", &mstp_clks[MSTP523]), 242 - CLKDEV_ICK_ID("fck", "sh-tmu.0", &mstp_clks[MSTP016]), 243 - CLKDEV_ICK_ID("fck", "ffd80000.timer", &mstp_clks[MSTP016]), 244 - CLKDEV_ICK_ID("fck", "sh-tmu.1", &mstp_clks[MSTP015]), 245 - CLKDEV_ICK_ID("fck", "ffd81000.timer", &mstp_clks[MSTP015]), 246 - }; 247 - 248 - void __init r8a7778_clock_init(void) 249 - { 250 - void __iomem *modemr = ioremap_nocache(MODEMR, PAGE_SIZE); 251 - u32 mode; 252 - int k, ret = 0; 253 - 254 - BUG_ON(!modemr); 255 - mode = ioread32(modemr); 256 - iounmap(modemr); 257 - 258 - switch (mode & (MD(19) | MD(18) | MD(12) | MD(11))) { 259 - case MD(19): 260 - extal_clk.rate = 38000000; 261 - SH_CLK_SET_RATIO(&plla_clk_ratio, 21, 1); 262 - SH_CLK_SET_RATIO(&pllb_clk_ratio, 21, 1); 263 - break; 264 - case MD(19) | MD(11): 265 - extal_clk.rate = 33333333; 266 - SH_CLK_SET_RATIO(&plla_clk_ratio, 24, 1); 267 - SH_CLK_SET_RATIO(&pllb_clk_ratio, 24, 1); 268 - break; 269 - case MD(19) | MD(12): 270 - extal_clk.rate = 28500000; 271 - SH_CLK_SET_RATIO(&plla_clk_ratio, 28, 1); 272 - SH_CLK_SET_RATIO(&pllb_clk_ratio, 28, 1); 273 - break; 274 - case MD(19) | MD(12) | MD(11): 275 - extal_clk.rate = 25000000; 276 - SH_CLK_SET_RATIO(&plla_clk_ratio, 32, 1); 277 - SH_CLK_SET_RATIO(&pllb_clk_ratio, 32, 1); 278 - break; 279 - case MD(19) | MD(18) | MD(11): 280 - extal_clk.rate = 33333333; 281 - SH_CLK_SET_RATIO(&plla_clk_ratio, 24, 1); 282 - SH_CLK_SET_RATIO(&pllb_clk_ratio, 21, 1); 283 - break; 284 - case MD(19) | MD(18) | MD(12): 285 - extal_clk.rate = 28500000; 286 - SH_CLK_SET_RATIO(&plla_clk_ratio, 28, 1); 287 - SH_CLK_SET_RATIO(&pllb_clk_ratio, 21, 1); 288 - break; 289 - case MD(19) | MD(18) | MD(12) | MD(11): 290 - extal_clk.rate = 25000000; 291 - SH_CLK_SET_RATIO(&plla_clk_ratio, 32, 1); 292 - SH_CLK_SET_RATIO(&pllb_clk_ratio, 24, 1); 293 - break; 294 - default: 295 - BUG(); 296 - } 297 - 298 - if (mode & MD(1)) { 299 - SH_CLK_SET_RATIO(&i_clk_ratio, 1, 1); 300 - SH_CLK_SET_RATIO(&s_clk_ratio, 1, 3); 301 - SH_CLK_SET_RATIO(&s1_clk_ratio, 1, 6); 302 - SH_CLK_SET_RATIO(&s3_clk_ratio, 1, 4); 303 - SH_CLK_SET_RATIO(&s4_clk_ratio, 1, 8); 304 - SH_CLK_SET_RATIO(&p_clk_ratio, 1, 12); 305 - SH_CLK_SET_RATIO(&g_clk_ratio, 1, 12); 306 - if (mode & MD(2)) { 307 - SH_CLK_SET_RATIO(&b_clk_ratio, 1, 18); 308 - SH_CLK_SET_RATIO(&out_clk_ratio, 1, 18); 309 - } else { 310 - SH_CLK_SET_RATIO(&b_clk_ratio, 1, 12); 311 - SH_CLK_SET_RATIO(&out_clk_ratio, 1, 12); 312 - } 313 - } else { 314 - SH_CLK_SET_RATIO(&i_clk_ratio, 1, 1); 315 - SH_CLK_SET_RATIO(&s_clk_ratio, 1, 4); 316 - SH_CLK_SET_RATIO(&s1_clk_ratio, 1, 8); 317 - SH_CLK_SET_RATIO(&s3_clk_ratio, 1, 4); 318 - SH_CLK_SET_RATIO(&s4_clk_ratio, 1, 8); 319 - SH_CLK_SET_RATIO(&p_clk_ratio, 1, 16); 320 - SH_CLK_SET_RATIO(&g_clk_ratio, 1, 12); 321 - if (mode & MD(2)) { 322 - SH_CLK_SET_RATIO(&b_clk_ratio, 1, 16); 323 - SH_CLK_SET_RATIO(&out_clk_ratio, 1, 16); 324 - } else { 325 - SH_CLK_SET_RATIO(&b_clk_ratio, 1, 12); 326 - SH_CLK_SET_RATIO(&out_clk_ratio, 1, 12); 327 - } 328 - } 329 - 330 - for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) 331 - ret = clk_register(main_clks[k]); 332 - 333 - if (!ret) 334 - ret = sh_clk_mstp_register(mstp_clks, MSTP_NR); 335 - 336 - clkdev_add_table(lookups, ARRAY_SIZE(lookups)); 337 - 338 - if (!ret) 339 - shmobile_clk_init(); 340 - else 341 - panic("failed to setup r8a7778 clocks\n"); 342 - }
-47
arch/arm/mach-shmobile/clock.c
··· 1 - /* 2 - * SH-Mobile Clock Framework 3 - * 4 - * Copyright (C) 2010 Magnus Damm 5 - * 6 - * Used together with arch/arm/common/clkdev.c and drivers/sh/clk.c. 7 - * 8 - * This program is free software; you can redistribute it and/or modify 9 - * it under the terms of the GNU General Public License as published by 10 - * the Free Software Foundation; version 2 of the License. 11 - * 12 - * This program is distributed in the hope that it will be useful, 13 - * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 - * GNU General Public License for more details. 16 - * 17 - */ 18 - 19 - #include <linux/export.h> 20 - #include <linux/kernel.h> 21 - #include <linux/init.h> 22 - #include <linux/sh_clk.h> 23 - 24 - #include "clock.h" 25 - #include "common.h" 26 - 27 - unsigned long shmobile_fixed_ratio_clk_recalc(struct clk *clk) 28 - { 29 - struct clk_ratio *p = clk->priv; 30 - 31 - return clk->parent->rate / p->div * p->mul; 32 - }; 33 - 34 - struct sh_clk_ops shmobile_fixed_ratio_clk_ops = { 35 - .recalc = shmobile_fixed_ratio_clk_recalc, 36 - }; 37 - 38 - int __init shmobile_clk_init(void) 39 - { 40 - /* Kick the child clocks.. */ 41 - recalculate_root_clocks(); 42 - 43 - /* Enable the necessary init clocks */ 44 - clk_enable_init_clocks(); 45 - 46 - return 0; 47 - }
-42
arch/arm/mach-shmobile/clock.h
··· 1 - #ifndef CLOCK_H 2 - #define CLOCK_H 3 - 4 - /* legacy clock implementation */ 5 - 6 - struct clk; 7 - unsigned long shmobile_fixed_ratio_clk_recalc(struct clk *clk); 8 - extern struct sh_clk_ops shmobile_fixed_ratio_clk_ops; 9 - 10 - /* clock ratio */ 11 - struct clk_ratio { 12 - int mul; 13 - int div; 14 - }; 15 - 16 - #define SH_CLK_RATIO(name, m, d) \ 17 - static struct clk_ratio name ##_ratio = { \ 18 - .mul = m, \ 19 - .div = d, \ 20 - } 21 - 22 - #define SH_FIXED_RATIO_CLKg(name, p, r) \ 23 - struct clk name = { \ 24 - .parent = &p, \ 25 - .ops = &shmobile_fixed_ratio_clk_ops,\ 26 - .priv = &r ## _ratio, \ 27 - } 28 - 29 - #define SH_FIXED_RATIO_CLK(name, p, r) \ 30 - static SH_FIXED_RATIO_CLKg(name, p, r) 31 - 32 - #define SH_FIXED_RATIO_CLK_SET(name, p, m, d) \ 33 - SH_CLK_RATIO(name, m, d); \ 34 - SH_FIXED_RATIO_CLK(name, p, name) 35 - 36 - #define SH_CLK_SET_RATIO(p, m, d) \ 37 - do { \ 38 - (p)->mul = m; \ 39 - (p)->div = d; \ 40 - } while (0) 41 - 42 - #endif
-5
arch/arm/mach-shmobile/common.h
··· 1 1 #ifndef __ARCH_MACH_COMMON_H 2 2 #define __ARCH_MACH_COMMON_H 3 3 4 - extern void shmobile_earlytimer_init(void); 5 4 extern void shmobile_init_delay(void); 6 - struct twd_local_timer; 7 - extern void shmobile_setup_console(void); 8 5 extern void shmobile_boot_vector(void); 9 6 extern unsigned long shmobile_boot_fn; 10 7 extern unsigned long shmobile_boot_arg; ··· 15 18 extern void shmobile_smp_scu_prepare_cpus(unsigned int max_cpus); 16 19 extern void shmobile_smp_scu_cpu_die(unsigned int cpu); 17 20 extern int shmobile_smp_scu_cpu_kill(unsigned int cpu); 18 - struct clk; 19 - extern int shmobile_clk_init(void); 20 21 extern struct platform_suspend_ops shmobile_suspend_ops; 21 22 22 23 #ifdef CONFIG_SUSPEND
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arch/arm/mach-shmobile/console.c
··· 1 - /* 2 - * SH-Mobile Console 3 - * 4 - * Copyright (C) 2010 Magnus Damm 5 - * 6 - * This program is free software; you can redistribute it and/or modify 7 - * it under the terms of the GNU General Public License as published by 8 - * the Free Software Foundation; version 2 of the License. 9 - * 10 - * This program is distributed in the hope that it will be useful, 11 - * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 - * GNU General Public License for more details. 14 - */ 15 - #include <linux/kernel.h> 16 - #include <linux/init.h> 17 - #include <linux/platform_device.h> 18 - #include <asm/mach/map.h> 19 - #include "common.h" 20 - 21 - void __init shmobile_setup_console(void) 22 - { 23 - parse_early_param(); 24 - 25 - /* Let earlyprintk output early console messages */ 26 - early_platform_driver_probe("earlyprintk", 1, 1); 27 - }
-295
arch/arm/mach-shmobile/intc.h
··· 1 - #ifndef __ASM_MACH_INTC_H 2 - #define __ASM_MACH_INTC_H 3 - #include <linux/sh_intc.h> 4 - 5 - #define INTC_IRQ_PINS_ENUM_16L(p) \ 6 - p ## _IRQ0, p ## _IRQ1, p ## _IRQ2, p ## _IRQ3, \ 7 - p ## _IRQ4, p ## _IRQ5, p ## _IRQ6, p ## _IRQ7, \ 8 - p ## _IRQ8, p ## _IRQ9, p ## _IRQ10, p ## _IRQ11, \ 9 - p ## _IRQ12, p ## _IRQ13, p ## _IRQ14, p ## _IRQ15 10 - 11 - #define INTC_IRQ_PINS_ENUM_16H(p) \ 12 - p ## _IRQ16, p ## _IRQ17, p ## _IRQ18, p ## _IRQ19, \ 13 - p ## _IRQ20, p ## _IRQ21, p ## _IRQ22, p ## _IRQ23, \ 14 - p ## _IRQ24, p ## _IRQ25, p ## _IRQ26, p ## _IRQ27, \ 15 - p ## _IRQ28, p ## _IRQ29, p ## _IRQ30, p ## _IRQ31 16 - 17 - #define INTC_IRQ_PINS_VECT_16L(p, vect) \ 18 - vect(p ## _IRQ0, 0x0200), vect(p ## _IRQ1, 0x0220), \ 19 - vect(p ## _IRQ2, 0x0240), vect(p ## _IRQ3, 0x0260), \ 20 - vect(p ## _IRQ4, 0x0280), vect(p ## _IRQ5, 0x02a0), \ 21 - vect(p ## _IRQ6, 0x02c0), vect(p ## _IRQ7, 0x02e0), \ 22 - vect(p ## _IRQ8, 0x0300), vect(p ## _IRQ9, 0x0320), \ 23 - vect(p ## _IRQ10, 0x0340), vect(p ## _IRQ11, 0x0360), \ 24 - vect(p ## _IRQ12, 0x0380), vect(p ## _IRQ13, 0x03a0), \ 25 - vect(p ## _IRQ14, 0x03c0), vect(p ## _IRQ15, 0x03e0) 26 - 27 - #define INTC_IRQ_PINS_VECT_16H(p, vect) \ 28 - vect(p ## _IRQ16, 0x3200), vect(p ## _IRQ17, 0x3220), \ 29 - vect(p ## _IRQ18, 0x3240), vect(p ## _IRQ19, 0x3260), \ 30 - vect(p ## _IRQ20, 0x3280), vect(p ## _IRQ21, 0x32a0), \ 31 - vect(p ## _IRQ22, 0x32c0), vect(p ## _IRQ23, 0x32e0), \ 32 - vect(p ## _IRQ24, 0x3300), vect(p ## _IRQ25, 0x3320), \ 33 - vect(p ## _IRQ26, 0x3340), vect(p ## _IRQ27, 0x3360), \ 34 - vect(p ## _IRQ28, 0x3380), vect(p ## _IRQ29, 0x33a0), \ 35 - vect(p ## _IRQ30, 0x33c0), vect(p ## _IRQ31, 0x33e0) 36 - 37 - #define INTC_IRQ_PINS_MASK_16L(p, base) \ 38 - { base + 0x40, base + 0x60, 8, /* INTMSK00A / INTMSKCLR00A */ \ 39 - { p ## _IRQ0, p ## _IRQ1, p ## _IRQ2, p ## _IRQ3, \ 40 - p ## _IRQ4, p ## _IRQ5, p ## _IRQ6, p ## _IRQ7 } }, \ 41 - { base + 0x44, base + 0x64, 8, /* INTMSK10A / INTMSKCLR10A */ \ 42 - { p ## _IRQ8, p ## _IRQ9, p ## _IRQ10, p ## _IRQ11, \ 43 - p ## _IRQ12, p ## _IRQ13, p ## _IRQ14, p ## _IRQ15 } } 44 - 45 - #define INTC_IRQ_PINS_MASK_16H(p, base) \ 46 - { base + 0x48, base + 0x68, 8, /* INTMSK20A / INTMSKCLR20A */ \ 47 - { p ## _IRQ16, p ## _IRQ17, p ## _IRQ18, p ## _IRQ19, \ 48 - p ## _IRQ20, p ## _IRQ21, p ## _IRQ22, p ## _IRQ23 } }, \ 49 - { base + 0x4c, base + 0x6c, 8, /* INTMSK30A / INTMSKCLR30A */ \ 50 - { p ## _IRQ24, p ## _IRQ25, p ## _IRQ26, p ## _IRQ27, \ 51 - p ## _IRQ28, p ## _IRQ29, p ## _IRQ30, p ## _IRQ31 } } 52 - 53 - #define INTC_IRQ_PINS_PRIO_16L(p, base) \ 54 - { base + 0x10, 0, 32, 4, /* INTPRI00A */ \ 55 - { p ## _IRQ0, p ## _IRQ1, p ## _IRQ2, p ## _IRQ3, \ 56 - p ## _IRQ4, p ## _IRQ5, p ## _IRQ6, p ## _IRQ7 } }, \ 57 - { base + 0x14, 0, 32, 4, /* INTPRI10A */ \ 58 - { p ## _IRQ8, p ## _IRQ9, p ## _IRQ10, p ## _IRQ11, \ 59 - p ## _IRQ12, p ## _IRQ13, p ## _IRQ14, p ## _IRQ15 } } 60 - 61 - #define INTC_IRQ_PINS_PRIO_16H(p, base) \ 62 - { base + 0x18, 0, 32, 4, /* INTPRI20A */ \ 63 - { p ## _IRQ16, p ## _IRQ17, p ## _IRQ18, p ## _IRQ19, \ 64 - p ## _IRQ20, p ## _IRQ21, p ## _IRQ22, p ## _IRQ23 } }, \ 65 - { base + 0x1c, 0, 32, 4, /* INTPRI30A */ \ 66 - { p ## _IRQ24, p ## _IRQ25, p ## _IRQ26, p ## _IRQ27, \ 67 - p ## _IRQ28, p ## _IRQ29, p ## _IRQ30, p ## _IRQ31 } } 68 - 69 - #define INTC_IRQ_PINS_SENSE_16L(p, base) \ 70 - { base + 0x00, 32, 4, /* ICR1A */ \ 71 - { p ## _IRQ0, p ## _IRQ1, p ## _IRQ2, p ## _IRQ3, \ 72 - p ## _IRQ4, p ## _IRQ5, p ## _IRQ6, p ## _IRQ7 } }, \ 73 - { base + 0x04, 32, 4, /* ICR2A */ \ 74 - { p ## _IRQ8, p ## _IRQ9, p ## _IRQ10, p ## _IRQ11, \ 75 - p ## _IRQ12, p ## _IRQ13, p ## _IRQ14, p ## _IRQ15 } } 76 - 77 - #define INTC_IRQ_PINS_SENSE_16H(p, base) \ 78 - { base + 0x08, 32, 4, /* ICR3A */ \ 79 - { p ## _IRQ16, p ## _IRQ17, p ## _IRQ18, p ## _IRQ19, \ 80 - p ## _IRQ20, p ## _IRQ21, p ## _IRQ22, p ## _IRQ23 } }, \ 81 - { base + 0x0c, 32, 4, /* ICR4A */ \ 82 - { p ## _IRQ24, p ## _IRQ25, p ## _IRQ26, p ## _IRQ27, \ 83 - p ## _IRQ28, p ## _IRQ29, p ## _IRQ30, p ## _IRQ31 } } 84 - 85 - #define INTC_IRQ_PINS_ACK_16L(p, base) \ 86 - { base + 0x20, 0, 8, /* INTREQ00A */ \ 87 - { p ## _IRQ0, p ## _IRQ1, p ## _IRQ2, p ## _IRQ3, \ 88 - p ## _IRQ4, p ## _IRQ5, p ## _IRQ6, p ## _IRQ7 } }, \ 89 - { base + 0x24, 0, 8, /* INTREQ10A */ \ 90 - { p ## _IRQ8, p ## _IRQ9, p ## _IRQ10, p ## _IRQ11, \ 91 - p ## _IRQ12, p ## _IRQ13, p ## _IRQ14, p ## _IRQ15 } } 92 - 93 - #define INTC_IRQ_PINS_ACK_16H(p, base) \ 94 - { base + 0x28, 0, 8, /* INTREQ20A */ \ 95 - { p ## _IRQ16, p ## _IRQ17, p ## _IRQ18, p ## _IRQ19, \ 96 - p ## _IRQ20, p ## _IRQ21, p ## _IRQ22, p ## _IRQ23 } }, \ 97 - { base + 0x2c, 0, 8, /* INTREQ30A */ \ 98 - { p ## _IRQ24, p ## _IRQ25, p ## _IRQ26, p ## _IRQ27, \ 99 - p ## _IRQ28, p ## _IRQ29, p ## _IRQ30, p ## _IRQ31 } } 100 - 101 - #define INTC_IRQ_PINS_16(p, base, vect, str) \ 102 - \ 103 - static struct resource p ## _resources[] __initdata = { \ 104 - [0] = { \ 105 - .start = base, \ 106 - .end = base + 0x64, \ 107 - .flags = IORESOURCE_MEM, \ 108 - }, \ 109 - }; \ 110 - \ 111 - enum { \ 112 - p ## _UNUSED = 0, \ 113 - INTC_IRQ_PINS_ENUM_16L(p), \ 114 - }; \ 115 - \ 116 - static struct intc_vect p ## _vectors[] __initdata = { \ 117 - INTC_IRQ_PINS_VECT_16L(p, vect), \ 118 - }; \ 119 - \ 120 - static struct intc_mask_reg p ## _mask_registers[] __initdata = { \ 121 - INTC_IRQ_PINS_MASK_16L(p, base), \ 122 - }; \ 123 - \ 124 - static struct intc_prio_reg p ## _prio_registers[] __initdata = { \ 125 - INTC_IRQ_PINS_PRIO_16L(p, base), \ 126 - }; \ 127 - \ 128 - static struct intc_sense_reg p ## _sense_registers[] __initdata = { \ 129 - INTC_IRQ_PINS_SENSE_16L(p, base), \ 130 - }; \ 131 - \ 132 - static struct intc_mask_reg p ## _ack_registers[] __initdata = { \ 133 - INTC_IRQ_PINS_ACK_16L(p, base), \ 134 - }; \ 135 - \ 136 - static struct intc_desc p ## _desc __initdata = { \ 137 - .name = str, \ 138 - .resource = p ## _resources, \ 139 - .num_resources = ARRAY_SIZE(p ## _resources), \ 140 - .hw = INTC_HW_DESC(p ## _vectors, NULL, \ 141 - p ## _mask_registers, p ## _prio_registers, \ 142 - p ## _sense_registers, p ## _ack_registers) \ 143 - } 144 - 145 - #define INTC_IRQ_PINS_16H(p, base, vect, str) \ 146 - \ 147 - static struct resource p ## _resources[] __initdata = { \ 148 - [0] = { \ 149 - .start = base, \ 150 - .end = base + 0x64, \ 151 - .flags = IORESOURCE_MEM, \ 152 - }, \ 153 - }; \ 154 - \ 155 - enum { \ 156 - p ## _UNUSED = 0, \ 157 - INTC_IRQ_PINS_ENUM_16H(p), \ 158 - }; \ 159 - \ 160 - static struct intc_vect p ## _vectors[] __initdata = { \ 161 - INTC_IRQ_PINS_VECT_16H(p, vect), \ 162 - }; \ 163 - \ 164 - static struct intc_mask_reg p ## _mask_registers[] __initdata = { \ 165 - INTC_IRQ_PINS_MASK_16H(p, base), \ 166 - }; \ 167 - \ 168 - static struct intc_prio_reg p ## _prio_registers[] __initdata = { \ 169 - INTC_IRQ_PINS_PRIO_16H(p, base), \ 170 - }; \ 171 - \ 172 - static struct intc_sense_reg p ## _sense_registers[] __initdata = { \ 173 - INTC_IRQ_PINS_SENSE_16H(p, base), \ 174 - }; \ 175 - \ 176 - static struct intc_mask_reg p ## _ack_registers[] __initdata = { \ 177 - INTC_IRQ_PINS_ACK_16H(p, base), \ 178 - }; \ 179 - \ 180 - static struct intc_desc p ## _desc __initdata = { \ 181 - .name = str, \ 182 - .resource = p ## _resources, \ 183 - .num_resources = ARRAY_SIZE(p ## _resources), \ 184 - .hw = INTC_HW_DESC(p ## _vectors, NULL, \ 185 - p ## _mask_registers, p ## _prio_registers, \ 186 - p ## _sense_registers, p ## _ack_registers) \ 187 - } 188 - 189 - #define INTC_IRQ_PINS_32(p, base, vect, str) \ 190 - \ 191 - static struct resource p ## _resources[] __initdata = { \ 192 - [0] = { \ 193 - .start = base, \ 194 - .end = base + 0x6c, \ 195 - .flags = IORESOURCE_MEM, \ 196 - }, \ 197 - }; \ 198 - \ 199 - enum { \ 200 - p ## _UNUSED = 0, \ 201 - INTC_IRQ_PINS_ENUM_16L(p), \ 202 - INTC_IRQ_PINS_ENUM_16H(p), \ 203 - }; \ 204 - \ 205 - static struct intc_vect p ## _vectors[] __initdata = { \ 206 - INTC_IRQ_PINS_VECT_16L(p, vect), \ 207 - INTC_IRQ_PINS_VECT_16H(p, vect), \ 208 - }; \ 209 - \ 210 - static struct intc_mask_reg p ## _mask_registers[] __initdata = { \ 211 - INTC_IRQ_PINS_MASK_16L(p, base), \ 212 - INTC_IRQ_PINS_MASK_16H(p, base), \ 213 - }; \ 214 - \ 215 - static struct intc_prio_reg p ## _prio_registers[] __initdata = { \ 216 - INTC_IRQ_PINS_PRIO_16L(p, base), \ 217 - INTC_IRQ_PINS_PRIO_16H(p, base), \ 218 - }; \ 219 - \ 220 - static struct intc_sense_reg p ## _sense_registers[] __initdata = { \ 221 - INTC_IRQ_PINS_SENSE_16L(p, base), \ 222 - INTC_IRQ_PINS_SENSE_16H(p, base), \ 223 - }; \ 224 - \ 225 - static struct intc_mask_reg p ## _ack_registers[] __initdata = { \ 226 - INTC_IRQ_PINS_ACK_16L(p, base), \ 227 - INTC_IRQ_PINS_ACK_16H(p, base), \ 228 - }; \ 229 - \ 230 - static struct intc_desc p ## _desc __initdata = { \ 231 - .name = str, \ 232 - .resource = p ## _resources, \ 233 - .num_resources = ARRAY_SIZE(p ## _resources), \ 234 - .hw = INTC_HW_DESC(p ## _vectors, NULL, \ 235 - p ## _mask_registers, p ## _prio_registers, \ 236 - p ## _sense_registers, p ## _ack_registers) \ 237 - } 238 - 239 - #define INTC_PINT_E_EMPTY 240 - #define INTC_PINT_E_NONE 0, 0, 0, 0, 0, 0, 0, 0, 241 - #define INTC_PINT_E(p) \ 242 - PINT ## p ## 0, PINT ## p ## 1, PINT ## p ## 2, PINT ## p ## 3, \ 243 - PINT ## p ## 4, PINT ## p ## 5, PINT ## p ## 6, PINT ## p ## 7, 244 - 245 - #define INTC_PINT_V_NONE 246 - #define INTC_PINT_V(p, vect) \ 247 - vect(PINT ## p ## 0, 0), vect(PINT ## p ## 1, 1), \ 248 - vect(PINT ## p ## 2, 2), vect(PINT ## p ## 3, 3), \ 249 - vect(PINT ## p ## 4, 4), vect(PINT ## p ## 5, 5), \ 250 - vect(PINT ## p ## 6, 6), vect(PINT ## p ## 7, 7), 251 - 252 - #define INTC_PINT(p, mask_reg, sense_base, str, \ 253 - enums_1, enums_2, enums_3, enums_4, \ 254 - vect_1, vect_2, vect_3, vect_4, \ 255 - mask_a, mask_b, mask_c, mask_d, \ 256 - sense_a, sense_b, sense_c, sense_d) \ 257 - \ 258 - enum { \ 259 - PINT ## p ## _UNUSED = 0, \ 260 - enums_1 enums_2 enums_3 enums_4 \ 261 - }; \ 262 - \ 263 - static struct intc_vect p ## _vectors[] __initdata = { \ 264 - vect_1 vect_2 vect_3 vect_4 \ 265 - }; \ 266 - \ 267 - static struct intc_mask_reg p ## _mask_registers[] __initdata = { \ 268 - { mask_reg, 0, 32, /* PINTER */ \ 269 - { mask_a mask_b mask_c mask_d } } \ 270 - }; \ 271 - \ 272 - static struct intc_sense_reg p ## _sense_registers[] __initdata = { \ 273 - { sense_base + 0x00, 16, 2, /* PINTCR */ \ 274 - { sense_a } }, \ 275 - { sense_base + 0x04, 16, 2, /* PINTCR */ \ 276 - { sense_b } }, \ 277 - { sense_base + 0x08, 16, 2, /* PINTCR */ \ 278 - { sense_c } }, \ 279 - { sense_base + 0x0c, 16, 2, /* PINTCR */ \ 280 - { sense_d } }, \ 281 - }; \ 282 - \ 283 - static struct intc_desc p ## _desc __initdata = { \ 284 - .name = str, \ 285 - .hw = INTC_HW_DESC(p ## _vectors, NULL, \ 286 - p ## _mask_registers, NULL, \ 287 - p ## _sense_registers, NULL), \ 288 - } 289 - 290 - /* INTCS */ 291 - #define INTCS_VECT_BASE 0x3400 292 - #define INTCS_VECT(n, vect) INTC_VECT((n), INTCS_VECT_BASE + (vect)) 293 - #define intcs_evt2irq(evt) evt2irq(INTCS_VECT_BASE + (evt)) 294 - 295 - #endif /* __ASM_MACH_INTC_H */
-9
arch/arm/mach-shmobile/pm-rmobile.h
··· 12 12 13 13 #include <linux/pm_domain.h> 14 14 15 - #define DEFAULT_DEV_LATENCY_NS 250000 16 - 17 - struct platform_device; 18 - 19 15 struct rmobile_pm_domain { 20 16 struct generic_pm_domain genpd; 21 17 struct dev_power_governor *gov; ··· 20 24 void __iomem *base; 21 25 unsigned int bit_shift; 22 26 bool no_debug; 23 - }; 24 - 25 - struct pm_domain_device { 26 - const char *domain_name; 27 - struct platform_device *pdev; 28 27 }; 29 28 30 29 #endif /* PM_RMOBILE_H */
-78
arch/arm/mach-shmobile/r8a7778.h
··· 1 - /* 2 - * Copyright (C) 2013 Renesas Solutions Corp. 3 - * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> 4 - * Copyright (C) 2013 Cogent Embedded, Inc. 5 - * 6 - * This program is free software; you can redistribute it and/or modify 7 - * it under the terms of the GNU General Public License as published by 8 - * the Free Software Foundation; version 2 of the License. 9 - * 10 - * This program is distributed in the hope that it will be useful, 11 - * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 - * GNU General Public License for more details. 14 - */ 15 - #ifndef __ASM_R8A7778_H__ 16 - #define __ASM_R8A7778_H__ 17 - 18 - #include <linux/sh_eth.h> 19 - 20 - /* HPB-DMA slave IDs */ 21 - enum { 22 - HPBDMA_SLAVE_DUMMY, 23 - HPBDMA_SLAVE_SDHI0_TX, 24 - HPBDMA_SLAVE_SDHI0_RX, 25 - HPBDMA_SLAVE_SSI0_TX, 26 - HPBDMA_SLAVE_SSI0_RX, 27 - HPBDMA_SLAVE_SSI1_TX, 28 - HPBDMA_SLAVE_SSI1_RX, 29 - HPBDMA_SLAVE_SSI2_TX, 30 - HPBDMA_SLAVE_SSI2_RX, 31 - HPBDMA_SLAVE_SSI3_TX, 32 - HPBDMA_SLAVE_SSI3_RX, 33 - HPBDMA_SLAVE_SSI4_TX, 34 - HPBDMA_SLAVE_SSI4_RX, 35 - HPBDMA_SLAVE_SSI5_TX, 36 - HPBDMA_SLAVE_SSI5_RX, 37 - HPBDMA_SLAVE_SSI6_TX, 38 - HPBDMA_SLAVE_SSI6_RX, 39 - HPBDMA_SLAVE_SSI7_TX, 40 - HPBDMA_SLAVE_SSI7_RX, 41 - HPBDMA_SLAVE_SSI8_TX, 42 - HPBDMA_SLAVE_SSI8_RX, 43 - HPBDMA_SLAVE_HPBIF0_TX, 44 - HPBDMA_SLAVE_HPBIF0_RX, 45 - HPBDMA_SLAVE_HPBIF1_TX, 46 - HPBDMA_SLAVE_HPBIF1_RX, 47 - HPBDMA_SLAVE_HPBIF2_TX, 48 - HPBDMA_SLAVE_HPBIF2_RX, 49 - HPBDMA_SLAVE_HPBIF3_TX, 50 - HPBDMA_SLAVE_HPBIF3_RX, 51 - HPBDMA_SLAVE_HPBIF4_TX, 52 - HPBDMA_SLAVE_HPBIF4_RX, 53 - HPBDMA_SLAVE_HPBIF5_TX, 54 - HPBDMA_SLAVE_HPBIF5_RX, 55 - HPBDMA_SLAVE_HPBIF6_TX, 56 - HPBDMA_SLAVE_HPBIF6_RX, 57 - HPBDMA_SLAVE_HPBIF7_TX, 58 - HPBDMA_SLAVE_HPBIF7_RX, 59 - HPBDMA_SLAVE_HPBIF8_TX, 60 - HPBDMA_SLAVE_HPBIF8_RX, 61 - HPBDMA_SLAVE_USBFUNC_TX, 62 - HPBDMA_SLAVE_USBFUNC_RX, 63 - }; 64 - 65 - extern void r8a7778_add_standard_devices(void); 66 - extern void r8a7778_add_standard_devices_dt(void); 67 - extern void r8a7778_add_dt_devices(void); 68 - 69 - extern void r8a7778_init_late(void); 70 - extern void r8a7778_init_irq_dt(void); 71 - extern void r8a7778_clock_init(void); 72 - extern void r8a7778_init_irq_extpin(int irlm); 73 - extern void r8a7778_init_irq_extpin_dt(int irlm); 74 - extern void r8a7778_pinmux_init(void); 75 - 76 - extern int r8a7778_usb_phy_power(bool enable); 77 - 78 - #endif /* __ASM_R8A7778_H__ */
-2
arch/arm/mach-shmobile/r8a7779.h
··· 1 1 #ifndef __ASM_R8A7779_H__ 2 2 #define __ASM_R8A7779_H__ 3 3 4 - #include <linux/sh_clk.h> 5 - 6 4 extern void r8a7779_pm_init(void); 7 5 8 6 #ifdef CONFIG_PM
+1 -559
arch/arm/mach-shmobile/setup-r8a7778.c
··· 16 16 */ 17 17 18 18 #include <linux/clk/shmobile.h> 19 - #include <linux/kernel.h> 20 19 #include <linux/io.h> 21 - #include <linux/irqchip/arm-gic.h> 22 - #include <linux/of.h> 23 - #include <linux/of_platform.h> 24 - #include <linux/platform_data/dma-rcar-hpbdma.h> 25 - #include <linux/platform_data/gpio-rcar.h> 26 - #include <linux/platform_data/irq-renesas-intc-irqpin.h> 27 - #include <linux/platform_device.h> 28 20 #include <linux/irqchip.h> 29 - #include <linux/serial_sci.h> 30 - #include <linux/sh_timer.h> 31 - #include <linux/pm_runtime.h> 32 - #include <linux/usb/phy.h> 33 - #include <linux/usb/hcd.h> 34 - #include <linux/usb/ehci_pdriver.h> 35 - #include <linux/usb/ohci_pdriver.h> 36 - #include <linux/dma-mapping.h> 37 21 38 22 #include <asm/mach/arch.h> 39 - #include <asm/hardware/cache-l2x0.h> 40 23 41 24 #include "common.h" 42 25 #include "irqs.h" 43 - #include "r8a7778.h" 44 26 45 27 #define MODEMR 0xffcc0020 46 28 47 - #ifdef CONFIG_COMMON_CLK 48 29 static void __init r8a7778_timer_init(void) 49 30 { 50 31 u32 mode; ··· 36 55 iounmap(modemr); 37 56 r8a7778_clocks_init(mode); 38 57 } 39 - #endif 40 58 41 - /* SCIF */ 42 - #define R8A7778_SCIF(index, baseaddr, irq) \ 43 - static struct plat_sci_port scif##index##_platform_data = { \ 44 - .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ 45 - .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, \ 46 - .type = PORT_SCIF, \ 47 - }; \ 48 - \ 49 - static struct resource scif##index##_resources[] = { \ 50 - DEFINE_RES_MEM(baseaddr, 0x100), \ 51 - DEFINE_RES_IRQ(irq), \ 52 - } 53 - 54 - R8A7778_SCIF(0, 0xffe40000, gic_iid(0x66)); 55 - R8A7778_SCIF(1, 0xffe41000, gic_iid(0x67)); 56 - R8A7778_SCIF(2, 0xffe42000, gic_iid(0x68)); 57 - R8A7778_SCIF(3, 0xffe43000, gic_iid(0x69)); 58 - R8A7778_SCIF(4, 0xffe44000, gic_iid(0x6a)); 59 - R8A7778_SCIF(5, 0xffe45000, gic_iid(0x6b)); 60 - 61 - #define r8a7778_register_scif(index) \ 62 - platform_device_register_resndata(NULL, "sh-sci", index, \ 63 - scif##index##_resources, \ 64 - ARRAY_SIZE(scif##index##_resources), \ 65 - &scif##index##_platform_data, \ 66 - sizeof(scif##index##_platform_data)) 67 - 68 - /* TMU */ 69 - static struct sh_timer_config sh_tmu0_platform_data = { 70 - .channels_mask = 7, 71 - }; 72 - 73 - static struct resource sh_tmu0_resources[] = { 74 - DEFINE_RES_MEM(0xffd80000, 0x30), 75 - DEFINE_RES_IRQ(gic_iid(0x40)), 76 - DEFINE_RES_IRQ(gic_iid(0x41)), 77 - DEFINE_RES_IRQ(gic_iid(0x42)), 78 - }; 79 - 80 - #define r8a7778_register_tmu(idx) \ 81 - platform_device_register_resndata( \ 82 - NULL, "sh-tmu", idx, \ 83 - sh_tmu##idx##_resources, \ 84 - ARRAY_SIZE(sh_tmu##idx##_resources), \ 85 - &sh_tmu##idx##_platform_data, \ 86 - sizeof(sh_tmu##idx##_platform_data)) 87 - 88 - int r8a7778_usb_phy_power(bool enable) 89 - { 90 - static struct usb_phy *phy = NULL; 91 - int ret = 0; 92 - 93 - if (!phy) 94 - phy = usb_get_phy(USB_PHY_TYPE_USB2); 95 - 96 - if (IS_ERR(phy)) { 97 - pr_err("kernel doesn't have usb phy driver\n"); 98 - return PTR_ERR(phy); 99 - } 100 - 101 - if (enable) 102 - ret = usb_phy_init(phy); 103 - else 104 - usb_phy_shutdown(phy); 105 - 106 - return ret; 107 - } 108 - 109 - /* USB */ 110 - static int usb_power_on(struct platform_device *pdev) 111 - { 112 - int ret = r8a7778_usb_phy_power(true); 113 - 114 - if (ret) 115 - return ret; 116 - 117 - pm_runtime_enable(&pdev->dev); 118 - pm_runtime_get_sync(&pdev->dev); 119 - 120 - return 0; 121 - } 122 - 123 - static void usb_power_off(struct platform_device *pdev) 124 - { 125 - if (r8a7778_usb_phy_power(false)) 126 - return; 127 - 128 - pm_runtime_put_sync(&pdev->dev); 129 - pm_runtime_disable(&pdev->dev); 130 - } 131 - 132 - static int ehci_init_internal_buffer(struct usb_hcd *hcd) 133 - { 134 - /* 135 - * Below are recommended values from the datasheet; 136 - * see [USB :: Setting of EHCI Internal Buffer]. 137 - */ 138 - /* EHCI IP internal buffer setting */ 139 - iowrite32(0x00ff0040, hcd->regs + 0x0094); 140 - /* EHCI IP internal buffer enable */ 141 - iowrite32(0x00000001, hcd->regs + 0x009C); 142 - 143 - return 0; 144 - } 145 - 146 - static struct usb_ehci_pdata ehci_pdata __initdata = { 147 - .power_on = usb_power_on, 148 - .power_off = usb_power_off, 149 - .power_suspend = usb_power_off, 150 - .pre_setup = ehci_init_internal_buffer, 151 - }; 152 - 153 - static struct resource ehci_resources[] __initdata = { 154 - DEFINE_RES_MEM(0xffe70000, 0x400), 155 - DEFINE_RES_IRQ(gic_iid(0x4c)), 156 - }; 157 - 158 - static struct usb_ohci_pdata ohci_pdata __initdata = { 159 - .power_on = usb_power_on, 160 - .power_off = usb_power_off, 161 - .power_suspend = usb_power_off, 162 - }; 163 - 164 - static struct resource ohci_resources[] __initdata = { 165 - DEFINE_RES_MEM(0xffe70400, 0x400), 166 - DEFINE_RES_IRQ(gic_iid(0x4c)), 167 - }; 168 - 169 - #define USB_PLATFORM_INFO(hci) \ 170 - static struct platform_device_info hci##_info __initdata = { \ 171 - .name = #hci "-platform", \ 172 - .id = -1, \ 173 - .res = hci##_resources, \ 174 - .num_res = ARRAY_SIZE(hci##_resources), \ 175 - .data = &hci##_pdata, \ 176 - .size_data = sizeof(hci##_pdata), \ 177 - .dma_mask = DMA_BIT_MASK(32), \ 178 - } 179 - 180 - USB_PLATFORM_INFO(ehci); 181 - USB_PLATFORM_INFO(ohci); 182 - 183 - /* PFC/GPIO */ 184 - static struct resource pfc_resources[] __initdata = { 185 - DEFINE_RES_MEM(0xfffc0000, 0x118), 186 - }; 187 - 188 - #define R8A7778_GPIO(idx) \ 189 - static struct resource r8a7778_gpio##idx##_resources[] __initdata = { \ 190 - DEFINE_RES_MEM(0xffc40000 + 0x1000 * (idx), 0x30), \ 191 - DEFINE_RES_IRQ(gic_iid(0x87)), \ 192 - }; \ 193 - \ 194 - static struct gpio_rcar_config r8a7778_gpio##idx##_platform_data __initdata = { \ 195 - .gpio_base = 32 * (idx), \ 196 - .irq_base = GPIO_IRQ_BASE(idx), \ 197 - .number_of_pins = 32, \ 198 - .pctl_name = "pfc-r8a7778", \ 199 - } 200 - 201 - R8A7778_GPIO(0); 202 - R8A7778_GPIO(1); 203 - R8A7778_GPIO(2); 204 - R8A7778_GPIO(3); 205 - R8A7778_GPIO(4); 206 - 207 - #define r8a7778_register_gpio(idx) \ 208 - platform_device_register_resndata( \ 209 - NULL, "gpio_rcar", idx, \ 210 - r8a7778_gpio##idx##_resources, \ 211 - ARRAY_SIZE(r8a7778_gpio##idx##_resources), \ 212 - &r8a7778_gpio##idx##_platform_data, \ 213 - sizeof(r8a7778_gpio##idx##_platform_data)) 214 - 215 - void __init r8a7778_pinmux_init(void) 216 - { 217 - platform_device_register_simple( 218 - "pfc-r8a7778", -1, 219 - pfc_resources, 220 - ARRAY_SIZE(pfc_resources)); 221 - 222 - r8a7778_register_gpio(0); 223 - r8a7778_register_gpio(1); 224 - r8a7778_register_gpio(2); 225 - r8a7778_register_gpio(3); 226 - r8a7778_register_gpio(4); 227 - }; 228 - 229 - /* I2C */ 230 - static struct resource i2c_resources[] __initdata = { 231 - /* I2C0 */ 232 - DEFINE_RES_MEM(0xffc70000, 0x1000), 233 - DEFINE_RES_IRQ(gic_iid(0x63)), 234 - /* I2C1 */ 235 - DEFINE_RES_MEM(0xffc71000, 0x1000), 236 - DEFINE_RES_IRQ(gic_iid(0x6e)), 237 - /* I2C2 */ 238 - DEFINE_RES_MEM(0xffc72000, 0x1000), 239 - DEFINE_RES_IRQ(gic_iid(0x6c)), 240 - /* I2C3 */ 241 - DEFINE_RES_MEM(0xffc73000, 0x1000), 242 - DEFINE_RES_IRQ(gic_iid(0x6d)), 243 - }; 244 - 245 - static void __init r8a7778_register_i2c(int id) 246 - { 247 - BUG_ON(id < 0 || id > 3); 248 - 249 - platform_device_register_simple( 250 - "i2c-rcar", id, 251 - i2c_resources + (2 * id), 2); 252 - } 253 - 254 - /* HSPI */ 255 - static struct resource hspi_resources[] __initdata = { 256 - /* HSPI0 */ 257 - DEFINE_RES_MEM(0xfffc7000, 0x18), 258 - DEFINE_RES_IRQ(gic_iid(0x5f)), 259 - /* HSPI1 */ 260 - DEFINE_RES_MEM(0xfffc8000, 0x18), 261 - DEFINE_RES_IRQ(gic_iid(0x74)), 262 - /* HSPI2 */ 263 - DEFINE_RES_MEM(0xfffc6000, 0x18), 264 - DEFINE_RES_IRQ(gic_iid(0x75)), 265 - }; 266 - 267 - static void __init r8a7778_register_hspi(int id) 268 - { 269 - BUG_ON(id < 0 || id > 2); 270 - 271 - platform_device_register_simple( 272 - "sh-hspi", id, 273 - hspi_resources + (2 * id), 2); 274 - } 275 - 276 - void __init r8a7778_add_dt_devices(void) 277 - { 278 - #ifdef CONFIG_CACHE_L2X0 279 - void __iomem *base = ioremap_nocache(0xf0100000, 0x1000); 280 - if (base) { 281 - /* 282 - * Shared attribute override enable, 64K*16way 283 - * don't call iounmap(base) 284 - */ 285 - l2x0_init(base, 0x00400000, 0xc20f0fff); 286 - } 287 - #endif 288 - } 289 - 290 - /* HPB-DMA */ 291 - 292 - /* Asynchronous mode register (ASYNCMDR) bits */ 293 - #define HPB_DMAE_ASYNCMDR_ASMD22_MASK BIT(2) /* SDHI0 */ 294 - #define HPB_DMAE_ASYNCMDR_ASMD22_SINGLE BIT(2) /* SDHI0 */ 295 - #define HPB_DMAE_ASYNCMDR_ASMD22_MULTI 0 /* SDHI0 */ 296 - #define HPB_DMAE_ASYNCMDR_ASMD21_MASK BIT(1) /* SDHI0 */ 297 - #define HPB_DMAE_ASYNCMDR_ASMD21_SINGLE BIT(1) /* SDHI0 */ 298 - #define HPB_DMAE_ASYNCMDR_ASMD21_MULTI 0 /* SDHI0 */ 299 - 300 - #define HPBDMA_SSI(_id) \ 301 - { \ 302 - .id = HPBDMA_SLAVE_SSI## _id ##_TX, \ 303 - .addr = 0xffd91008 + (_id * 0x40), \ 304 - .dcr = HPB_DMAE_DCR_CT | \ 305 - HPB_DMAE_DCR_DIP | \ 306 - HPB_DMAE_DCR_SPDS_32BIT | \ 307 - HPB_DMAE_DCR_DMDL | \ 308 - HPB_DMAE_DCR_DPDS_32BIT, \ 309 - .port = _id + (_id << 8), \ 310 - .dma_ch = (28 + _id), \ 311 - }, { \ 312 - .id = HPBDMA_SLAVE_SSI## _id ##_RX, \ 313 - .addr = 0xffd9100c + (_id * 0x40), \ 314 - .dcr = HPB_DMAE_DCR_CT | \ 315 - HPB_DMAE_DCR_DIP | \ 316 - HPB_DMAE_DCR_SMDL | \ 317 - HPB_DMAE_DCR_SPDS_32BIT | \ 318 - HPB_DMAE_DCR_DPDS_32BIT, \ 319 - .port = _id + (_id << 8), \ 320 - .dma_ch = (28 + _id), \ 321 - } 322 - 323 - #define HPBDMA_HPBIF(_id) \ 324 - { \ 325 - .id = HPBDMA_SLAVE_HPBIF## _id ##_TX, \ 326 - .addr = 0xffda0000 + (_id * 0x1000), \ 327 - .dcr = HPB_DMAE_DCR_CT | \ 328 - HPB_DMAE_DCR_DIP | \ 329 - HPB_DMAE_DCR_SPDS_32BIT | \ 330 - HPB_DMAE_DCR_DMDL | \ 331 - HPB_DMAE_DCR_DPDS_32BIT, \ 332 - .port = 0x1111, \ 333 - .dma_ch = (28 + _id), \ 334 - }, { \ 335 - .id = HPBDMA_SLAVE_HPBIF## _id ##_RX, \ 336 - .addr = 0xffda0000 + (_id * 0x1000), \ 337 - .dcr = HPB_DMAE_DCR_CT | \ 338 - HPB_DMAE_DCR_DIP | \ 339 - HPB_DMAE_DCR_SMDL | \ 340 - HPB_DMAE_DCR_SPDS_32BIT | \ 341 - HPB_DMAE_DCR_DPDS_32BIT, \ 342 - .port = 0x1111, \ 343 - .dma_ch = (28 + _id), \ 344 - } 345 - 346 - static const struct hpb_dmae_slave_config hpb_dmae_slaves[] = { 347 - { 348 - .id = HPBDMA_SLAVE_SDHI0_TX, 349 - .addr = 0xffe4c000 + 0x30, 350 - .dcr = HPB_DMAE_DCR_SPDS_16BIT | 351 - HPB_DMAE_DCR_DMDL | 352 - HPB_DMAE_DCR_DPDS_16BIT, 353 - .rstr = HPB_DMAE_ASYNCRSTR_ASRST21 | 354 - HPB_DMAE_ASYNCRSTR_ASRST22 | 355 - HPB_DMAE_ASYNCRSTR_ASRST23, 356 - .mdr = HPB_DMAE_ASYNCMDR_ASMD21_MULTI, 357 - .mdm = HPB_DMAE_ASYNCMDR_ASMD21_MASK, 358 - .port = 0x0D0C, 359 - .flags = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE, 360 - .dma_ch = 21, 361 - }, { 362 - .id = HPBDMA_SLAVE_SDHI0_RX, 363 - .addr = 0xffe4c000 + 0x30, 364 - .dcr = HPB_DMAE_DCR_SMDL | 365 - HPB_DMAE_DCR_SPDS_16BIT | 366 - HPB_DMAE_DCR_DPDS_16BIT, 367 - .rstr = HPB_DMAE_ASYNCRSTR_ASRST21 | 368 - HPB_DMAE_ASYNCRSTR_ASRST22 | 369 - HPB_DMAE_ASYNCRSTR_ASRST23, 370 - .mdr = HPB_DMAE_ASYNCMDR_ASMD22_MULTI, 371 - .mdm = HPB_DMAE_ASYNCMDR_ASMD22_MASK, 372 - .port = 0x0D0C, 373 - .flags = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE, 374 - .dma_ch = 22, 375 - }, { 376 - .id = HPBDMA_SLAVE_USBFUNC_TX, /* for D0 */ 377 - .addr = 0xffe60018, 378 - .dcr = HPB_DMAE_DCR_SPDS_32BIT | 379 - HPB_DMAE_DCR_DMDL | 380 - HPB_DMAE_DCR_DPDS_32BIT, 381 - .port = 0x0000, 382 - .dma_ch = 14, 383 - }, { 384 - .id = HPBDMA_SLAVE_USBFUNC_RX, /* for D1 */ 385 - .addr = 0xffe6001c, 386 - .dcr = HPB_DMAE_DCR_SMDL | 387 - HPB_DMAE_DCR_SPDS_32BIT | 388 - HPB_DMAE_DCR_DPDS_32BIT, 389 - .port = 0x0101, 390 - .dma_ch = 15, 391 - }, 392 - 393 - HPBDMA_SSI(0), 394 - HPBDMA_SSI(1), 395 - HPBDMA_SSI(2), 396 - HPBDMA_SSI(3), 397 - HPBDMA_SSI(4), 398 - HPBDMA_SSI(5), 399 - HPBDMA_SSI(6), 400 - HPBDMA_SSI(7), 401 - HPBDMA_SSI(8), 402 - 403 - HPBDMA_HPBIF(0), 404 - HPBDMA_HPBIF(1), 405 - HPBDMA_HPBIF(2), 406 - HPBDMA_HPBIF(3), 407 - HPBDMA_HPBIF(4), 408 - HPBDMA_HPBIF(5), 409 - HPBDMA_HPBIF(6), 410 - HPBDMA_HPBIF(7), 411 - HPBDMA_HPBIF(8), 412 - }; 413 - 414 - static const struct hpb_dmae_channel hpb_dmae_channels[] = { 415 - HPB_DMAE_CHANNEL(0x7c, HPBDMA_SLAVE_USBFUNC_TX), /* ch. 14 */ 416 - HPB_DMAE_CHANNEL(0x7c, HPBDMA_SLAVE_USBFUNC_RX), /* ch. 15 */ 417 - HPB_DMAE_CHANNEL(0x7e, HPBDMA_SLAVE_SDHI0_TX), /* ch. 21 */ 418 - HPB_DMAE_CHANNEL(0x7e, HPBDMA_SLAVE_SDHI0_RX), /* ch. 22 */ 419 - HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI0_TX), /* ch. 28 */ 420 - HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI0_RX), /* ch. 28 */ 421 - HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF0_TX), /* ch. 28 */ 422 - HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF0_RX), /* ch. 28 */ 423 - HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI1_TX), /* ch. 29 */ 424 - HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI1_RX), /* ch. 29 */ 425 - HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF1_TX), /* ch. 29 */ 426 - HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF1_RX), /* ch. 29 */ 427 - HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI2_TX), /* ch. 30 */ 428 - HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI2_RX), /* ch. 30 */ 429 - HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF2_TX), /* ch. 30 */ 430 - HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF2_RX), /* ch. 30 */ 431 - HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI3_TX), /* ch. 31 */ 432 - HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI3_RX), /* ch. 31 */ 433 - HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF3_TX), /* ch. 31 */ 434 - HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF3_RX), /* ch. 31 */ 435 - HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI4_TX), /* ch. 32 */ 436 - HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI4_RX), /* ch. 32 */ 437 - HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF4_TX), /* ch. 32 */ 438 - HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF4_RX), /* ch. 32 */ 439 - HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI5_TX), /* ch. 33 */ 440 - HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI5_RX), /* ch. 33 */ 441 - HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF5_TX), /* ch. 33 */ 442 - HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF5_RX), /* ch. 33 */ 443 - HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI6_TX), /* ch. 34 */ 444 - HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI6_RX), /* ch. 34 */ 445 - HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF6_TX), /* ch. 34 */ 446 - HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF6_RX), /* ch. 34 */ 447 - HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI7_TX), /* ch. 35 */ 448 - HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI7_RX), /* ch. 35 */ 449 - HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF7_TX), /* ch. 35 */ 450 - HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF7_RX), /* ch. 35 */ 451 - HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI8_TX), /* ch. 36 */ 452 - HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI8_RX), /* ch. 36 */ 453 - HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF8_TX), /* ch. 36 */ 454 - HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF8_RX), /* ch. 36 */ 455 - }; 456 - 457 - static struct hpb_dmae_pdata dma_platform_data __initdata = { 458 - .slaves = hpb_dmae_slaves, 459 - .num_slaves = ARRAY_SIZE(hpb_dmae_slaves), 460 - .channels = hpb_dmae_channels, 461 - .num_channels = ARRAY_SIZE(hpb_dmae_channels), 462 - .ts_shift = { 463 - [XMIT_SZ_8BIT] = 0, 464 - [XMIT_SZ_16BIT] = 1, 465 - [XMIT_SZ_32BIT] = 2, 466 - }, 467 - .num_hw_channels = 39, 468 - }; 469 - 470 - static struct resource hpb_dmae_resources[] __initdata = { 471 - /* Channel registers */ 472 - DEFINE_RES_MEM(0xffc08000, 0x1000), 473 - /* Common registers */ 474 - DEFINE_RES_MEM(0xffc09000, 0x170), 475 - /* Asynchronous reset registers */ 476 - DEFINE_RES_MEM(0xffc00300, 4), 477 - /* Asynchronous mode registers */ 478 - DEFINE_RES_MEM(0xffc00400, 4), 479 - /* IRQ for DMA channels */ 480 - DEFINE_RES_NAMED(gic_iid(0x7b), 5, NULL, IORESOURCE_IRQ), 481 - }; 482 - 483 - static void __init r8a7778_register_hpb_dmae(void) 484 - { 485 - platform_device_register_resndata(NULL, "hpb-dma-engine", 486 - -1, hpb_dmae_resources, 487 - ARRAY_SIZE(hpb_dmae_resources), 488 - &dma_platform_data, 489 - sizeof(dma_platform_data)); 490 - } 491 - 492 - void __init r8a7778_add_standard_devices(void) 493 - { 494 - r8a7778_add_dt_devices(); 495 - r8a7778_register_tmu(0); 496 - r8a7778_register_scif(0); 497 - r8a7778_register_scif(1); 498 - r8a7778_register_scif(2); 499 - r8a7778_register_scif(3); 500 - r8a7778_register_scif(4); 501 - r8a7778_register_scif(5); 502 - r8a7778_register_i2c(0); 503 - r8a7778_register_i2c(1); 504 - r8a7778_register_i2c(2); 505 - r8a7778_register_i2c(3); 506 - r8a7778_register_hspi(0); 507 - r8a7778_register_hspi(1); 508 - r8a7778_register_hspi(2); 509 - 510 - r8a7778_register_hpb_dmae(); 511 - } 512 - 513 - void __init r8a7778_init_late(void) 514 - { 515 - shmobile_init_late(); 516 - platform_device_register_full(&ehci_info); 517 - platform_device_register_full(&ohci_info); 518 - } 519 - 520 - static struct renesas_intc_irqpin_config irqpin_platform_data __initdata = { 521 - .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */ 522 - .sense_bitfield_width = 2, 523 - }; 524 - 525 - static struct resource irqpin_resources[] __initdata = { 526 - DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */ 527 - DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */ 528 - DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */ 529 - DEFINE_RES_MEM(0xfe780044, 4), /* INTMSK0 */ 530 - DEFINE_RES_MEM(0xfe780064, 4), /* INTMSKCLR0 */ 531 - DEFINE_RES_IRQ(gic_iid(0x3b)), /* IRQ0 */ 532 - DEFINE_RES_IRQ(gic_iid(0x3c)), /* IRQ1 */ 533 - DEFINE_RES_IRQ(gic_iid(0x3d)), /* IRQ2 */ 534 - DEFINE_RES_IRQ(gic_iid(0x3e)), /* IRQ3 */ 535 - }; 536 - 537 - void __init r8a7778_init_irq_extpin_dt(int irlm) 538 - { 539 - void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE); 540 - unsigned long tmp; 541 - 542 - if (!icr0) { 543 - pr_warn("r8a7778: unable to setup external irq pin mode\n"); 544 - return; 545 - } 546 - 547 - tmp = ioread32(icr0); 548 - if (irlm) 549 - tmp |= 1 << 23; /* IRQ0 -> IRQ3 as individual pins */ 550 - else 551 - tmp &= ~(1 << 23); /* IRL mode - not supported */ 552 - tmp |= (1 << 21); /* LVLMODE = 1 */ 553 - iowrite32(tmp, icr0); 554 - iounmap(icr0); 555 - } 556 - 557 - void __init r8a7778_init_irq_extpin(int irlm) 558 - { 559 - r8a7778_init_irq_extpin_dt(irlm); 560 - if (irlm) 561 - platform_device_register_resndata( 562 - NULL, "renesas_intc_irqpin", -1, 563 - irqpin_resources, ARRAY_SIZE(irqpin_resources), 564 - &irqpin_platform_data, sizeof(irqpin_platform_data)); 565 - } 566 - 567 - #ifdef CONFIG_USE_OF 568 59 #define INT2SMSKCR0 0x82288 /* 0xfe782288 */ 569 60 #define INT2SMSKCR1 0x8228c /* 0xfe78228c */ 570 61 ··· 45 592 void __init r8a7778_init_irq_dt(void) 46 593 { 47 594 void __iomem *base = ioremap_nocache(0xfe700000, 0x00100000); 48 - #ifdef CONFIG_ARCH_SHMOBILE_LEGACY 49 - void __iomem *gic_dist_base = ioremap_nocache(0xfe438000, 0x1000); 50 - void __iomem *gic_cpu_base = ioremap_nocache(0xfe430000, 0x1000); 51 - #endif 52 595 53 596 BUG_ON(!base); 54 597 55 - #ifdef CONFIG_ARCH_SHMOBILE_LEGACY 56 - gic_init(0, 29, gic_dist_base, gic_cpu_base); 57 - #else 58 598 irqchip_init(); 59 - #endif 599 + 60 600 /* route all interrupts to ARM */ 61 601 __raw_writel(0x73ffffff, base + INT2NTSR0); 62 602 __raw_writel(0xffffffff, base + INT2NTSR1); ··· 70 624 .init_early = shmobile_init_delay, 71 625 .init_irq = r8a7778_init_irq_dt, 72 626 .init_late = shmobile_init_late, 73 - #ifdef CONFIG_COMMON_CLK 74 627 .init_time = r8a7778_timer_init, 75 - #endif 76 628 .dt_compat = r8a7778_compat_dt, 77 629 MACHINE_END 78 - 79 - #endif /* CONFIG_USE_OF */
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arch/arm/mach-shmobile/sh-gpio.h
··· 1 - /* 2 - * Generic GPIO API and pinmux table support 3 - * 4 - * Copyright (c) 2008 Magnus Damm 5 - * 6 - * This file is subject to the terms and conditions of the GNU General Public 7 - * License. See the file "COPYING" in the main directory of this archive 8 - * for more details. 9 - */ 10 - #ifndef __ASM_ARCH_GPIO_H 11 - #define __ASM_ARCH_GPIO_H 12 - 13 - #include <linux/kernel.h> 14 - #include <linux/errno.h> 15 - #include <linux/io.h> 16 - 17 - /* 18 - * FIXME !! 19 - * 20 - * current gpio frame work doesn't have 21 - * the method to control only pull up/down/free. 22 - * this function should be replaced by correct gpio function 23 - */ 24 - static inline void __init gpio_direction_none(void __iomem * addr) 25 - { 26 - __raw_writeb(0x00, addr); 27 - } 28 - 29 - #endif /* __ASM_ARCH_GPIO_H */
-21
arch/arm/mach-shmobile/timer.c
··· 77 77 shmobile_setup_delay_hz(max_freq, 2, 4); 78 78 } 79 79 } 80 - 81 - static void __init shmobile_late_time_init(void) 82 - { 83 - /* 84 - * Make sure all compiled-in early timers register themselves. 85 - * 86 - * Run probe() for two "earlytimer" devices, these will be the 87 - * clockevents and clocksource devices respectively. In the event 88 - * that only a clockevents device is available, we -ENODEV on the 89 - * clocksource and the jiffies clocksource is used transparently 90 - * instead. No error handling is necessary here. 91 - */ 92 - early_platform_driver_register_all("earlytimer"); 93 - early_platform_driver_probe("earlytimer", 2, 0); 94 - } 95 - 96 - void __init shmobile_earlytimer_init(void) 97 - { 98 - late_time_init = shmobile_late_time_init; 99 - } 100 -