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[PATCH] ARM: 2676/1: S3C2440 - NAND register additions
Patch from Ben Dooks
Add the register definitions for the s3c2440 NAND controller
to the s3c2410 NAND register definitions
Signed-off-by: Ben Dooks
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
authored by
Ben Dooks
and committed by
Russell King
9dabf9da
70489c88
+41
-3
include/asm-arm/arch-s3c2410/regs-nand.h
+41
-3
include/asm-arm/arch-s3c2410/regs-nand.h
···
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/* linux/include/asm-arm/arch-s3c2410/regs-nand.h
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*
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-
* Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
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* http://www.simtec.co.uk/products/SWLINUX/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* S3C2410 clock register definitions
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*
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* Changelog:
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* 18-Aug-2004 BJD Copied file from 2.4 and updated
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*/
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#ifndef __ASM_ARM_REGS_NAND
···
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#define S3C2410_NFSTAT S3C2410_NFREG(0x10)
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#define S3C2410_NFECC S3C2410_NFREG(0x14)
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#define S3C2410_NFCONF_EN (1<<15)
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#define S3C2410_NFCONF_512BYTE (1<<14)
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#define S3C2410_NFCONF_4STEP (1<<13)
···
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#define S3C2410_NFSTAT_BUSY (1<<0)
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-
/* think ECC can only be 8bit read? */
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#endif /* __ASM_ARM_REGS_NAND */
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···
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/* linux/include/asm-arm/arch-s3c2410/regs-nand.h
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*
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+
* Copyright (c) 2004,2005 Simtec Electronics <linux@simtec.co.uk>
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* http://www.simtec.co.uk/products/SWLINUX/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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+
* S3C2410 NAND register definitions
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*
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* Changelog:
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* 18-Aug-2004 BJD Copied file from 2.4 and updated
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+
* 01-May-2005 BJD Added definitions for s3c2440 controller
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*/
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#ifndef __ASM_ARM_REGS_NAND
···
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#define S3C2410_NFSTAT S3C2410_NFREG(0x10)
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#define S3C2410_NFECC S3C2410_NFREG(0x14)
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#define S3C2440_NFCONT S3C2410_NFREG(0x04)
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#define S3C2440_NFCMD S3C2410_NFREG(0x08)
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#define S3C2440_NFADDR S3C2410_NFREG(0x0C)
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#define S3C2440_NFDATA S3C2410_NFREG(0x10)
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#define S3C2440_NFECCD0 S3C2410_NFREG(0x14)
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#define S3C2440_NFECCD1 S3C2410_NFREG(0x18)
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#define S3C2440_NFECCD S3C2410_NFREG(0x1C)
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#define S3C2440_NFSTAT S3C2410_NFREG(0x20)
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#define S3C2440_NFESTAT0 S3C2410_NFREG(0x24)
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#define S3C2440_NFESTAT1 S3C2410_NFREG(0x28)
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#define S3C2440_NFMECC0 S3C2410_NFREG(0x2C)
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#define S3C2440_NFMECC1 S3C2410_NFREG(0x30)
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#define S3C2440_NFSECC S3C2410_NFREG(0x34)
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#define S3C2440_NFSBLK S3C2410_NFREG(0x38)
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#define S3C2440_NFEBLK S3C2410_NFREG(0x3C)
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#define S3C2410_NFCONF_EN (1<<15)
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#define S3C2410_NFCONF_512BYTE (1<<14)
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#define S3C2410_NFCONF_4STEP (1<<13)
···
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#define S3C2410_NFSTAT_BUSY (1<<0)
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#define S3C2440_NFCONF_BUSWIDTH_8 (0<<0)
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#define S3C2440_NFCONF_BUSWIDTH_16 (1<<0)
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#define S3C2440_NFCONF_ADVFLASH (1<<3)
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#define S3C2440_NFCONF_TACLS(x) ((x)<<12)
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#define S3C2440_NFCONF_TWRPH0(x) ((x)<<8)
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#define S3C2440_NFCONF_TWRPH1(x) ((x)<<4)
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+
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#define S3C2440_NFCONT_LOCKTIGHT (1<<13)
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#define S3C2440_NFCONT_SOFTLOCK (1<<12)
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#define S3C2440_NFCONT_ILLEGALACC_EN (1<<10)
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#define S3C2440_NFCONT_RNBINT_EN (1<<9)
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#define S3C2440_NFCONT_RN_FALLING (1<<8)
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#define S3C2440_NFCONT_SPARE_ECCLOCK (1<<6)
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#define S3C2440_NFCONT_MAIN_ECCLOCK (1<<5)
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#define S3C2440_NFCONT_INITECC (1<<4)
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#define S3C2440_NFCONT_nFCE (1<<1)
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#define S3C2440_NFCONT_ENABLE (1<<0)
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#define S3C2440_NFSTAT_READY (1<<0)
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#define S3C2440_NFSTAT_nCE (1<<1)
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#define S3C2440_NFSTAT_RnB_CHANGE (1<<2)
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#define S3C2440_NFSTAT_ILLEGAL_ACCESS (1<<3)
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#endif /* __ASM_ARM_REGS_NAND */
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