media: rockchip: rkisp1: Mask invalid bits in DPCC parameters

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

Restrict the DPCC configuration that can be set by userspace to valid
register bits. To do so, reorganize the related register macros to
define valid bitmasks, as well as bits of the DPCC mode register.

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Paul Elder <paul.elder@ideasonboard.com>
Reviewed-by: Dafna Hirschfeld <dafna@fastmail.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>

authored by

Laurent Pinchart and committed by

Mauro Carvalho Chehab 3 years ago 9daa2b84 596fa6e7

+41 -29

2 changed files

expand all

drivers

media

platform

rockchip

rkisp1

rkisp1-params.c

rkisp1-regs.h

+28 -16

drivers/media/platform/rockchip/rkisp1/rkisp1-params.c

··· 58 58 unsigned int i; 59 59 u32 mode; 60 60 61 - /* avoid to override the old enable value */ 61 + /* 62 + * The enable bit is controlled in rkisp1_isp_isr_other_config() and 63 + * must be preserved. The grayscale mode should be configured 64 + * automatically based on the media bus code on the ISP sink pad, so 65 + * only the STAGE1_ENABLE bit can be set by userspace. 66 + */ 62 67 mode = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_DPCC_MODE); 63 - mode &= RKISP1_CIF_ISP_DPCC_ENA; 64 - mode |= arg->mode & ~RKISP1_CIF_ISP_DPCC_ENA; 68 + mode &= RKISP1_CIF_ISP_DPCC_MODE_DPCC_ENABLE; 69 + mode |= arg->mode & RKISP1_CIF_ISP_DPCC_MODE_STAGE1_ENABLE; 65 70 rkisp1_write(params->rkisp1, RKISP1_CIF_ISP_DPCC_MODE, mode); 71 + 66 72 rkisp1_write(params->rkisp1, RKISP1_CIF_ISP_DPCC_OUTPUT_MODE, 67 - arg->output_mode); 73 + arg->output_mode & RKISP1_CIF_ISP_DPCC_OUTPUT_MODE_MASK); 68 74 rkisp1_write(params->rkisp1, RKISP1_CIF_ISP_DPCC_SET_USE, 69 - arg->set_use); 75 + arg->set_use & RKISP1_CIF_ISP_DPCC_SET_USE_MASK); 70 76 71 77 for (i = 0; i < RKISP1_CIF_ISP_DPCC_METHODS_MAX; i++) { 72 78 rkisp1_write(params->rkisp1, RKISP1_ISP_DPCC_METHODS_SET(i), 73 - arg->methods[i].method); 79 + arg->methods[i].method & 80 + RKISP1_CIF_ISP_DPCC_METHODS_SET_MASK); 74 81 rkisp1_write(params->rkisp1, RKISP1_ISP_DPCC_LINE_THRESH(i), 75 - arg->methods[i].line_thresh); 82 + arg->methods[i].line_thresh & 83 + RKISP1_CIF_ISP_DPCC_LINE_THRESH_MASK); 76 84 rkisp1_write(params->rkisp1, RKISP1_ISP_DPCC_LINE_MAD_FAC(i), 77 - arg->methods[i].line_mad_fac); 85 + arg->methods[i].line_mad_fac & 86 + RKISP1_CIF_ISP_DPCC_LINE_MAD_FAC_MASK); 78 87 rkisp1_write(params->rkisp1, RKISP1_ISP_DPCC_PG_FAC(i), 79 - arg->methods[i].pg_fac); 88 + arg->methods[i].pg_fac & 89 + RKISP1_CIF_ISP_DPCC_PG_FAC_MASK); 80 90 rkisp1_write(params->rkisp1, RKISP1_ISP_DPCC_RND_THRESH(i), 81 - arg->methods[i].rnd_thresh); 91 + arg->methods[i].rnd_thresh & 92 + RKISP1_CIF_ISP_DPCC_RND_THRESH_MASK); 82 93 rkisp1_write(params->rkisp1, RKISP1_ISP_DPCC_RG_FAC(i), 83 - arg->methods[i].rg_fac); 94 + arg->methods[i].rg_fac & 95 + RKISP1_CIF_ISP_DPCC_RG_FAC_MASK); 84 96 } 85 97 86 98 rkisp1_write(params->rkisp1, RKISP1_CIF_ISP_DPCC_RND_OFFS, 87 - arg->rnd_offs); 99 + arg->rnd_offs & RKISP1_CIF_ISP_DPCC_RND_OFFS_MASK); 88 100 rkisp1_write(params->rkisp1, RKISP1_CIF_ISP_DPCC_RO_LIMITS, 89 - arg->ro_limits); 101 + arg->ro_limits & RKISP1_CIF_ISP_DPCC_RO_LIMIT_MASK); 90 102 } 91 103 92 104 /* ISP black level subtraction interface function */ ··· 1226 1214 if (module_ens & RKISP1_CIF_ISP_MODULE_DPCC) 1227 1215 rkisp1_param_set_bits(params, 1228 1216 RKISP1_CIF_ISP_DPCC_MODE, 1229 - RKISP1_CIF_ISP_DPCC_ENA); 1217 + RKISP1_CIF_ISP_DPCC_MODE_DPCC_ENABLE); 1230 1218 else 1231 1219 rkisp1_param_clear_bits(params, 1232 1220 RKISP1_CIF_ISP_DPCC_MODE, 1233 - RKISP1_CIF_ISP_DPCC_ENA); 1221 + RKISP1_CIF_ISP_DPCC_MODE_DPCC_ENABLE); 1234 1222 } 1235 1223 1236 1224 /* update bls config */ ··· 1592 1580 void rkisp1_params_disable(struct rkisp1_params *params) 1593 1581 { 1594 1582 rkisp1_param_clear_bits(params, RKISP1_CIF_ISP_DPCC_MODE, 1595 - RKISP1_CIF_ISP_DPCC_ENA); 1583 + RKISP1_CIF_ISP_DPCC_MODE_DPCC_ENABLE); 1596 1584 rkisp1_param_clear_bits(params, RKISP1_CIF_ISP_LSC_CTRL, 1597 1585 RKISP1_CIF_ISP_LSC_CTRL_ENA); 1598 1586 rkisp1_param_clear_bits(params, RKISP1_CIF_ISP_BLS_CTRL,

+13 -13

drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h

··· 618 618 #define RKISP1_CIF_ISP_CTRL_ISP_GAMMA_OUT_ENA_READ(x) (((x) >> 11) & 1) 619 619 620 620 /* DPCC */ 621 - /* ISP_DPCC_MODE */ 622 - #define RKISP1_CIF_ISP_DPCC_ENA BIT(0) 623 - #define RKISP1_CIF_ISP_DPCC_MODE_MAX 0x07 624 - #define RKISP1_CIF_ISP_DPCC_OUTPUTMODE_MAX 0x0F 625 - #define RKISP1_CIF_ISP_DPCC_SETUSE_MAX 0x0F 626 - #define RKISP1_CIF_ISP_DPCC_METHODS_SET_RESERVED 0xFFFFE000 627 - #define RKISP1_CIF_ISP_DPCC_LINE_THRESH_RESERVED 0xFFFF0000 628 - #define RKISP1_CIF_ISP_DPCC_LINE_MAD_FAC_RESERVED 0xFFFFC0C0 629 - #define RKISP1_CIF_ISP_DPCC_PG_FAC_RESERVED 0xFFFFC0C0 630 - #define RKISP1_CIF_ISP_DPCC_RND_THRESH_RESERVED 0xFFFF0000 631 - #define RKISP1_CIF_ISP_DPCC_RG_FAC_RESERVED 0xFFFFC0C0 632 - #define RKISP1_CIF_ISP_DPCC_RO_LIMIT_RESERVED 0xFFFFF000 633 - #define RKISP1_CIF_ISP_DPCC_RND_OFFS_RESERVED 0xFFFFF000 621 + #define RKISP1_CIF_ISP_DPCC_MODE_DPCC_ENABLE BIT(0) 622 + #define RKISP1_CIF_ISP_DPCC_MODE_GRAYSCALE_MODE BIT(1) 623 + #define RKISP1_CIF_ISP_DPCC_MODE_STAGE1_ENABLE BIT(2) 624 + #define RKISP1_CIF_ISP_DPCC_OUTPUT_MODE_MASK GENMASK(3, 0) 625 + #define RKISP1_CIF_ISP_DPCC_SET_USE_MASK GENMASK(3, 0) 626 + #define RKISP1_CIF_ISP_DPCC_METHODS_SET_MASK 0x00001f1f 627 + #define RKISP1_CIF_ISP_DPCC_LINE_THRESH_MASK 0x0000ffff 628 + #define RKISP1_CIF_ISP_DPCC_LINE_MAD_FAC_MASK 0x00003f3f 629 + #define RKISP1_CIF_ISP_DPCC_PG_FAC_MASK 0x00003f3f 630 + #define RKISP1_CIF_ISP_DPCC_RND_THRESH_MASK 0x0000ffff 631 + #define RKISP1_CIF_ISP_DPCC_RG_FAC_MASK 0x00003f3f 632 + #define RKISP1_CIF_ISP_DPCC_RO_LIMIT_MASK 0x00000fff 633 + #define RKISP1_CIF_ISP_DPCC_RND_OFFS_MASK 0x00000fff 634 634 635 635 /* BLS */ 636 636 /* ISP_BLS_CTRL */