Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
tjh.dev
kernel
os
linux
Merge branch 'omap-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6
* 'omap-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6:
omap: Disable serial port autoidle by default
omap: Fix access to already released memory in clk_debugfs_register_one()
omap: Fix arch/arm/mach-omap2/mux.c: Off by one error
omap: Fix 3630 mux errors
OMAP2/3: GPMC: ensure valid clock pointer
OMAP2/3: IRQ: ensure valid base address
ARCH OMAP : enable ARCH_HAS_HOLES_MEMORYMODEL for OMAP
omap: Remove old unused defines for OMAP_32KSYNCT_BASE
omap: define _toggle_gpio_edge_triggering only for OMAP1
+1
arch/arm/Kconfig
+1
arch/arm/Kconfig
+4
-1
arch/arm/mach-omap2/gpmc.c
+4
-1
arch/arm/mach-omap2/gpmc.c
···
505
505
void __init gpmc_init(void)
506
506
{
507
507
u32 l;
508
-
char *ck;
508
+
char *ck = NULL;
509
509
510
510
if (cpu_is_omap24xx()) {
511
511
ck = "core_l3_ck";
···
520
520
ck = "gpmc_ck";
521
521
l = OMAP44XX_GPMC_BASE;
522
522
}
523
+
524
+
if (WARN_ON(!ck))
525
+
return;
523
526
524
527
gpmc_l3_clk = clk_get(NULL, ck);
525
528
if (IS_ERR(gpmc_l3_clk)) {
+3
-1
arch/arm/mach-omap2/irq.c
+3
-1
arch/arm/mach-omap2/irq.c
···
194
194
int i;
195
195
196
196
for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
197
-
unsigned long base;
197
+
unsigned long base = 0;
198
198
struct omap_irq_bank *bank = irq_banks + i;
199
199
200
200
if (cpu_is_omap24xx())
201
201
base = OMAP24XX_IC_BASE;
202
202
else if (cpu_is_omap34xx())
203
203
base = OMAP34XX_IC_BASE;
204
+
205
+
BUG_ON(!base);
204
206
205
207
/* Static mapping, never released */
206
208
bank->base_reg = ioremap(base, SZ_4K);
+9
-1
arch/arm/mach-omap2/mux.c
+9
-1
arch/arm/mach-omap2/mux.c
···
486
486
static inline void omap_mux_decode(struct seq_file *s, u16 val)
487
487
{
488
488
char *flags[OMAP_MUX_MAX_NR_FLAGS];
489
-
char mode[14];
489
+
char mode[sizeof("OMAP_MUX_MODE") + 1];
490
490
int i = -1;
491
491
492
492
sprintf(mode, "OMAP_MUX_MODE%d", val & 0x7);
···
553
553
if (!m0_name)
554
554
continue;
555
555
556
+
/* REVISIT: Needs to be updated if mode0 names get longer */
556
557
for (i = 0; i < OMAP_MUX_DEFNAME_LEN; i++) {
557
558
if (m0_name[i] == '\0') {
558
559
m0_def[i] = m0_name[i];
···
964
963
#ifndef CONFIG_OMAP_MUX
965
964
/* Skip pins that are not muxed as GPIO by bootloader */
966
965
if (!OMAP_MODE_GPIO(omap_mux_read(superset->reg_offset))) {
966
+
superset++;
967
+
continue;
968
+
}
969
+
#endif
970
+
971
+
#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS)
972
+
if (!superset->muxnames || !superset->muxnames[0]) {
967
973
superset++;
968
974
continue;
969
975
}
+47
arch/arm/mach-omap2/mux34xx.c
+47
arch/arm/mach-omap2/mux34xx.c
···
649
649
_OMAP3_MUXENTRY(UART3_TX_IRTX, 166,
650
650
"uart3_tx_irtx", NULL, NULL, NULL,
651
651
"gpio_166", NULL, NULL, "safe_mode"),
652
+
653
+
/* Only on 3630, see omap36xx_cbp_subset for the signals */
654
+
_OMAP3_MUXENTRY(GPMC_A11, 0,
655
+
NULL, NULL, NULL, NULL,
656
+
NULL, NULL, NULL, NULL),
657
+
_OMAP3_MUXENTRY(SAD2D_MBUSFLAG, 0,
658
+
NULL, NULL, NULL, NULL,
659
+
NULL, NULL, NULL, NULL),
660
+
_OMAP3_MUXENTRY(SAD2D_MREAD, 0,
661
+
NULL, NULL, NULL, NULL,
662
+
NULL, NULL, NULL, NULL),
663
+
_OMAP3_MUXENTRY(SAD2D_MWRITE, 0,
664
+
NULL, NULL, NULL, NULL,
665
+
NULL, NULL, NULL, NULL),
666
+
_OMAP3_MUXENTRY(SAD2D_SBUSFLAG, 0,
667
+
NULL, NULL, NULL, NULL,
668
+
NULL, NULL, NULL, NULL),
669
+
_OMAP3_MUXENTRY(SAD2D_SREAD, 0,
670
+
NULL, NULL, NULL, NULL,
671
+
NULL, NULL, NULL, NULL),
672
+
_OMAP3_MUXENTRY(SAD2D_SWRITE, 0,
673
+
NULL, NULL, NULL, NULL,
674
+
NULL, NULL, NULL, NULL),
675
+
_OMAP3_MUXENTRY(GPMC_A11, 0,
676
+
NULL, NULL, NULL, NULL,
677
+
NULL, NULL, NULL, NULL),
678
+
_OMAP3_MUXENTRY(SAD2D_MCAD28, 0,
679
+
NULL, NULL, NULL, NULL,
680
+
NULL, NULL, NULL, NULL),
681
+
_OMAP3_MUXENTRY(SAD2D_MCAD29, 0,
682
+
NULL, NULL, NULL, NULL,
683
+
NULL, NULL, NULL, NULL),
684
+
_OMAP3_MUXENTRY(SAD2D_MCAD32, 0,
685
+
NULL, NULL, NULL, NULL,
686
+
NULL, NULL, NULL, NULL),
687
+
_OMAP3_MUXENTRY(SAD2D_MCAD33, 0,
688
+
NULL, NULL, NULL, NULL,
689
+
NULL, NULL, NULL, NULL),
690
+
_OMAP3_MUXENTRY(SAD2D_MCAD34, 0,
691
+
NULL, NULL, NULL, NULL,
692
+
NULL, NULL, NULL, NULL),
693
+
_OMAP3_MUXENTRY(SAD2D_MCAD35, 0,
694
+
NULL, NULL, NULL, NULL,
695
+
NULL, NULL, NULL, NULL),
696
+
_OMAP3_MUXENTRY(SAD2D_MCAD36, 0,
697
+
NULL, NULL, NULL, NULL,
698
+
NULL, NULL, NULL, NULL),
652
699
{ .reg_offset = OMAP_MUX_TERMINATOR },
653
700
};
654
701
+9
-2
arch/arm/mach-omap2/serial.c
+9
-2
arch/arm/mach-omap2/serial.c
···
36
36
#define UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV 0x52
37
37
#define UART_OMAP_WER 0x17 /* Wake-up enable register */
38
38
39
-
#define DEFAULT_TIMEOUT (5 * HZ)
39
+
/*
40
+
* NOTE: By default the serial timeout is disabled as it causes lost characters
41
+
* over the serial ports. This means that the UART clocks will stay on until
42
+
* disabled via sysfs. This also causes that any deeper omap sleep states are
43
+
* blocked.
44
+
*/
45
+
#define DEFAULT_TIMEOUT 0
40
46
41
47
struct omap_uart_state {
42
48
int num;
···
428
422
uart->timeout = DEFAULT_TIMEOUT;
429
423
setup_timer(&uart->timer, omap_uart_idle_timer,
430
424
(unsigned long) uart);
431
-
mod_timer(&uart->timer, jiffies + uart->timeout);
425
+
if (uart->timeout)
426
+
mod_timer(&uart->timer, jiffies + uart->timeout);
432
427
omap_uart_smart_idle_enable(uart, 0);
433
428
434
429
if (cpu_is_omap34xx()) {
+2
-2
arch/arm/plat-omap/clock.c
+2
-2
arch/arm/plat-omap/clock.c
···
391
391
static int clk_debugfs_register_one(struct clk *c)
392
392
{
393
393
int err;
394
-
struct dentry *d, *child;
394
+
struct dentry *d, *child, *child_tmp;
395
395
struct clk *pa = c->parent;
396
396
char s[255];
397
397
char *p = s;
···
423
423
424
424
err_out:
425
425
d = c->dent;
426
-
list_for_each_entry(child, &d->d_subdirs, d_u.d_child)
426
+
list_for_each_entry_safe(child, child_tmp, &d->d_subdirs, d_u.d_child)
427
427
debugfs_remove(child);
428
428
debugfs_remove(c->dent);
429
429
return err;
+2
-2
arch/arm/plat-omap/gpio.c
+2
-2
arch/arm/plat-omap/gpio.c
···
750
750
}
751
751
#endif
752
752
753
+
#ifdef CONFIG_ARCH_OMAP1
753
754
/*
754
755
* This only applies to chips that can't do both rising and falling edge
755
756
* detection at once. For all other chips, this function is a noop.
···
761
760
u32 l = 0;
762
761
763
762
switch (bank->method) {
764
-
#ifdef CONFIG_ARCH_OMAP1
765
763
case METHOD_MPUIO:
766
764
reg += OMAP_MPUIO_GPIO_INT_EDGE;
767
765
break;
768
-
#endif
769
766
#ifdef CONFIG_ARCH_OMAP15XX
770
767
case METHOD_GPIO_1510:
771
768
reg += OMAP1510_GPIO_INT_CONTROL;
···
786
787
787
788
__raw_writel(l, reg);
788
789
}
790
+
#endif
789
791
790
792
static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
791
793
{
-10
arch/arm/plat-omap/omap_device.c
-10
arch/arm/plat-omap/omap_device.c
···
89
89
#define USE_WAKEUP_LAT 0
90
90
#define IGNORE_WAKEUP_LAT 1
91
91
92
-
/* XXX this should be moved into a separate file */
93
-
#if defined(CONFIG_ARCH_OMAP2420)
94
-
# define OMAP_32KSYNCT_BASE 0x48004000
95
-
#elif defined(CONFIG_ARCH_OMAP2430)
96
-
# define OMAP_32KSYNCT_BASE 0x49020000
97
-
#elif defined(CONFIG_ARCH_OMAP3430)
98
-
# define OMAP_32KSYNCT_BASE 0x48320000
99
-
#else
100
-
# error Unknown OMAP device
101
-
#endif
102
92
103
93
/* Private functions */
104
94