MIPS: Clear Cause.BD in instruction_pointer_set

Clear Cause.BD after we use instruction_pointer_set to override
EPC.

This can prevent exception_epc check against instruction code at
new return address.
It won't be considered as "in delay slot" after epc being overridden
anyway.

Signed-off-by: Jiaxun Yang <[e-mail]>
Signed-off-by: Thomas Bogendoerfer <[e-mail]>

arch/mips/include/asm/ptrace.h

···
                                            unsigned long val)
 {
 	regs->cp0_epc = val;
+	regs->cp0_cause &= ~CAUSEF_BD;
 }
 
 /* Query offset/name of register from its name/offset */