tjh.dev / kernel
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drm/amdgpu:enable mcbp for gfx9(v2)

set bit 21 of IB.control filed to actually enable
MCBP for SRIOV
v2:
add flag for preemption enable bit for soc15 and use
this flag instead of hardcode.

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Monk Liu and committed by
Alex Deucher 9ccd52eb 806ba2d4

+4
+3
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
··· 3073 3073 3074 3074 control |= ib->length_dw | (vm_id << 24); 3075 3075 3076 + if (amdgpu_sriov_vf(ring->adev) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) 3077 + control |= INDIRECT_BUFFER_PRE_ENB(1); 3078 + 3076 3079 amdgpu_ring_write(ring, header); 3077 3080 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 3078 3081 amdgpu_ring_write(ring,
+1
drivers/gpu/drm/amd/amdgpu/soc15d.h
··· 137 137 * 1 - Stream 138 138 * 2 - Bypass 139 139 */ 140 + #define INDIRECT_BUFFER_PRE_ENB(x) ((x) << 21) 140 141 #define PACKET3_COPY_DATA 0x40 141 142 #define PACKET3_PFP_SYNC_ME 0x42 142 143 #define PACKET3_COND_WRITE 0x45