tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
clk: samsung: exynos7: add gate clock for DMA block
Add support for PDMA0 and PDMA1 gate clks.
Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
authored by
Padmavathi Venna
and committed by
Sylwester Nawrocki
9cc2a0c9
83f191a7
+7
-1
+4
drivers/clk/samsung/clk-exynos7.c
+4
drivers/clk/samsung/clk-exynos7.c
···
722
722
GATE(ACLK_AXIUS_USBDRD30X_FSYS0X, "aclk_axius_usbdrd30x_fsys0x",
723
723
"mout_aclk_fsys0_200_user",
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724
ENABLE_ACLK_FSYS00, 19, 0, 0),
725
+
GATE(ACLK_PDMA1, "aclk_pdma1", "mout_aclk_fsys0_200_user",
726
+
ENABLE_ACLK_FSYS00, 3, 0, 0),
727
+
GATE(ACLK_PDMA0, "aclk_pdma0", "mout_aclk_fsys0_200_user",
728
+
ENABLE_ACLK_FSYS00, 4, 0, 0),
725
729
726
730
GATE(ACLK_USBDRD300, "aclk_usbdrd300", "mout_aclk_fsys0_200_user",
727
731
ENABLE_ACLK_FSYS01, 29, 0, 0),
+3
-1
include/dt-bindings/clock/exynos7-clk.h
+3
-1
include/dt-bindings/clock/exynos7-clk.h
···
91
91
#define PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER 6
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#define PHYCLK_USBDRD300_UDRD30_PHYCLK_USER 7
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#define OSCCLK_PHY_CLKOUT_USB30_PHY 8
94
-
#define FSYS0_NR_CLK 9
94
+
#define ACLK_PDMA0 9
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+
#define ACLK_PDMA1 10
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+
#define FSYS0_NR_CLK 11
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/* FSYS1 */
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#define ACLK_MMC1 1