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docs: PCI: Fix typos

Fix typos in PCI docs.

Link: https://lore.kernel.org/r/20231223184720.25645-1-tintinm2017@gmail.com
Link: https://lore.kernel.org/r/20231223184412.25598-1-tintinm2017@gmail.com
Signed-off-by: Attreyee Mukherjee <tintinm2017@gmail.com>
[bhelgaas: squashed, commit log]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Randy Dunlap <rdunlap@infradead.org> # for "busses" only

authored by

attreyee-muk and committed by
Bjorn Helgaas 9ca65c37 0942155a

+2 -2
+1 -1
Documentation/PCI/boot-interrupts.rst
··· 61 61 ========== 62 62 63 63 The use of threaded interrupts is the most likely condition to trigger 64 - this problem today. Threaded interrupts may not be reenabled after the IRQ 64 + this problem today. Threaded interrupts may not be re-enabled after the IRQ 65 65 handler wakes. These "one shot" conditions mean that the threaded interrupt 66 66 needs to keep the interrupt line masked until the threaded handler has run. 67 67 Especially when dealing with high data rate interrupts, the thread needs to
+1 -1
Documentation/PCI/msi-howto.rst
··· 236 236 Disabling MSIs below a bridge 237 237 ----------------------------- 238 238 239 - Some PCI bridges are not able to route MSIs between busses properly. 239 + Some PCI bridges are not able to route MSIs between buses properly. 240 240 In this case, MSIs must be disabled on all devices behind the bridge. 241 241 242 242 Some bridges allow you to enable MSIs by changing some bits in their