tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
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ARM: dts: exynos: use lowercase hex addresses

By convention the hex addresses should be lowercase.

Link: https://lore.kernel.org/r/20230125094513.155063-7-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Krzysztof Kozlowski 9ca5a7ce 7bac2cd7

+171 -171
+1 -1
arch/arm/boot/dts/exynos-syscon-restart.dtsi
··· 7 7 poweroff: syscon-poweroff { 8 8 compatible = "syscon-poweroff"; 9 9 regmap = <&pmu_system_controller>; 10 - offset = <0x330C>; /* PS_HOLD_CONTROL */ 10 + offset = <0x330c>; /* PS_HOLD_CONTROL */ 11 11 mask = <0x5200>; /* reset value */ 12 12 }; 13 13
+1 -1
arch/arm/boot/dts/exynos3250-monk.dts
··· 31 31 32 32 firmware@205f000 { 33 33 compatible = "samsung,secure-firmware"; 34 - reg = <0x0205F000 0x1000>; 34 + reg = <0x0205f000 0x1000>; 35 35 }; 36 36 37 37 gpio-keys {
+1 -1
arch/arm/boot/dts/exynos3250-rinato.dts
··· 36 36 37 37 firmware@205f000 { 38 38 compatible = "samsung,secure-firmware"; 39 - reg = <0x0205F000 0x1000>; 39 + reg = <0x0205f000 0x1000>; 40 40 }; 41 41 42 42 gpio-keys {
+15 -15
arch/arm/boot/dts/exynos3250.dtsi
··· 188 188 189 189 pd_cam: power-domain@10023c00 { 190 190 compatible = "samsung,exynos4210-pd"; 191 - reg = <0x10023C00 0x20>; 191 + reg = <0x10023c00 0x20>; 192 192 #power-domain-cells = <0>; 193 193 label = "CAM"; 194 194 }; 195 195 196 196 pd_mfc: power-domain@10023c40 { 197 197 compatible = "samsung,exynos4210-pd"; 198 - reg = <0x10023C40 0x20>; 198 + reg = <0x10023c40 0x20>; 199 199 #power-domain-cells = <0>; 200 200 label = "MFC"; 201 201 }; 202 202 203 203 pd_g3d: power-domain@10023c60 { 204 204 compatible = "samsung,exynos4210-pd"; 205 - reg = <0x10023C60 0x20>; 205 + reg = <0x10023c60 0x20>; 206 206 #power-domain-cells = <0>; 207 207 label = "G3D"; 208 208 }; 209 209 210 210 pd_lcd0: power-domain@10023c80 { 211 211 compatible = "samsung,exynos4210-pd"; 212 - reg = <0x10023C80 0x20>; 212 + reg = <0x10023c80 0x20>; 213 213 #power-domain-cells = <0>; 214 214 label = "LCD0"; 215 215 }; 216 216 217 217 pd_isp: power-domain@10023ca0 { 218 218 compatible = "samsung,exynos4210-pd"; 219 - reg = <0x10023CA0 0x20>; 219 + reg = <0x10023ca0 0x20>; 220 220 #power-domain-cells = <0>; 221 221 label = "ISP"; 222 222 }; ··· 233 233 234 234 cmu_dmc: clock-controller@105c0000 { 235 235 compatible = "samsung,exynos3250-cmu-dmc"; 236 - reg = <0x105C0000 0x2000>; 236 + reg = <0x105c0000 0x2000>; 237 237 #clock-cells = <1>; 238 238 }; 239 239 ··· 248 248 249 249 tmu: tmu@100c0000 { 250 250 compatible = "samsung,exynos3250-tmu"; 251 - reg = <0x100C0000 0x100>; 251 + reg = <0x100c0000 0x100>; 252 252 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; 253 253 clocks = <&cmu CLK_TMU_APBIF>; 254 254 clock-names = "tmu_apbif"; ··· 342 342 343 343 dsi_0: dsi@11c80000 { 344 344 compatible = "samsung,exynos3250-mipi-dsi"; 345 - reg = <0x11C80000 0x10000>; 345 + reg = <0x11c80000 0x10000>; 346 346 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 347 347 samsung,phy-type = <0>; 348 348 power-domains = <&pd_lcd0>; ··· 414 414 415 415 exynos_usbphy: usb-phy@125b0000 { 416 416 compatible = "samsung,exynos3250-usb2-phy"; 417 - reg = <0x125B0000 0x100>; 417 + reg = <0x125b0000 0x100>; 418 418 samsung,pmureg-phandle = <&pmu_system_controller>; 419 419 clocks = <&cmu CLK_USBOTG>, <&cmu CLK_SCLK_UPLL>; 420 420 clock-names = "phy", "ref"; ··· 442 442 443 443 adc: adc@126c0000 { 444 444 compatible = "samsung,exynos3250-adc"; 445 - reg = <0x126C0000 0x100>; 445 + reg = <0x126c0000 0x100>; 446 446 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 447 447 clock-names = "adc", "sclk"; 448 448 clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>; ··· 593 593 #address-cells = <1>; 594 594 #size-cells = <0>; 595 595 compatible = "samsung,s3c2440-i2c"; 596 - reg = <0x138A0000 0x100>; 596 + reg = <0x138a0000 0x100>; 597 597 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 598 598 clocks = <&cmu CLK_I2C4>; 599 599 clock-names = "i2c"; ··· 606 606 #address-cells = <1>; 607 607 #size-cells = <0>; 608 608 compatible = "samsung,s3c2440-i2c"; 609 - reg = <0x138B0000 0x100>; 609 + reg = <0x138b0000 0x100>; 610 610 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 611 611 clocks = <&cmu CLK_I2C5>; 612 612 clock-names = "i2c"; ··· 619 619 #address-cells = <1>; 620 620 #size-cells = <0>; 621 621 compatible = "samsung,s3c2440-i2c"; 622 - reg = <0x138C0000 0x100>; 622 + reg = <0x138c0000 0x100>; 623 623 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 624 624 clocks = <&cmu CLK_I2C6>; 625 625 clock-names = "i2c"; ··· 632 632 #address-cells = <1>; 633 633 #size-cells = <0>; 634 634 compatible = "samsung,s3c2440-i2c"; 635 - reg = <0x138D0000 0x100>; 635 + reg = <0x138d0000 0x100>; 636 636 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 637 637 clocks = <&cmu CLK_I2C7>; 638 638 clock-names = "i2c"; ··· 688 688 689 689 pwm: pwm@139d0000 { 690 690 compatible = "samsung,exynos4210-pwm"; 691 - reg = <0x139D0000 0x1000>; 691 + reg = <0x139d0000 0x1000>; 692 692 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 693 693 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 694 694 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+29 -29
arch/arm/boot/dts/exynos4.dtsi
··· 65 65 66 66 clock_audss: clock-controller@3810000 { 67 67 compatible = "samsung,exynos4210-audss-clock"; 68 - reg = <0x03810000 0x0C>; 68 + reg = <0x03810000 0x0c>; 69 69 #clock-cells = <1>; 70 70 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>, 71 71 <&clock CLK_SCLK_AUDIO0>, ··· 113 113 114 114 pd_mfc: power-domain@10023c40 { 115 115 compatible = "samsung,exynos4210-pd"; 116 - reg = <0x10023C40 0x20>; 116 + reg = <0x10023c40 0x20>; 117 117 #power-domain-cells = <0>; 118 118 label = "MFC"; 119 119 }; 120 120 121 121 pd_g3d: power-domain@10023c60 { 122 122 compatible = "samsung,exynos4210-pd"; 123 - reg = <0x10023C60 0x20>; 123 + reg = <0x10023c60 0x20>; 124 124 #power-domain-cells = <0>; 125 125 label = "G3D"; 126 126 }; 127 127 128 128 pd_lcd0: power-domain@10023c80 { 129 129 compatible = "samsung,exynos4210-pd"; 130 - reg = <0x10023C80 0x20>; 130 + reg = <0x10023c80 0x20>; 131 131 #power-domain-cells = <0>; 132 132 label = "LCD0"; 133 133 }; 134 134 135 135 pd_tv: power-domain@10023c20 { 136 136 compatible = "samsung,exynos4210-pd"; 137 - reg = <0x10023C20 0x20>; 137 + reg = <0x10023c20 0x20>; 138 138 #power-domain-cells = <0>; 139 139 power-domains = <&pd_lcd0>; 140 140 label = "TV"; ··· 142 142 143 143 pd_cam: power-domain@10023c00 { 144 144 compatible = "samsung,exynos4210-pd"; 145 - reg = <0x10023C00 0x20>; 145 + reg = <0x10023c00 0x20>; 146 146 #power-domain-cells = <0>; 147 147 label = "CAM"; 148 148 }; 149 149 150 150 pd_gps: power-domain@10023ce0 { 151 151 compatible = "samsung,exynos4210-pd"; 152 - reg = <0x10023CE0 0x20>; 152 + reg = <0x10023ce0 0x20>; 153 153 #power-domain-cells = <0>; 154 154 label = "GPS"; 155 155 }; 156 156 157 157 pd_gps_alive: power-domain@10023d00 { 158 158 compatible = "samsung,exynos4210-pd"; 159 - reg = <0x10023D00 0x20>; 159 + reg = <0x10023d00 0x20>; 160 160 #power-domain-cells = <0>; 161 161 label = "GPS alive"; 162 162 }; ··· 190 190 191 191 dsi_0: dsi@11c80000 { 192 192 compatible = "samsung,exynos4210-mipi-dsi"; 193 - reg = <0x11C80000 0x10000>; 193 + reg = <0x11c80000 0x10000>; 194 194 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 195 195 power-domains = <&pd_lcd0>; 196 196 phys = <&mipi_phy 1>; ··· 309 309 310 310 keypad: keypad@100a0000 { 311 311 compatible = "samsung,s5pv210-keypad"; 312 - reg = <0x100A0000 0x100>; 312 + reg = <0x100a0000 0x100>; 313 313 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 314 314 clocks = <&clock CLK_KEYIF>; 315 315 clock-names = "keypad"; ··· 354 354 355 355 exynos_usbphy: usb-phy@125b0000 { 356 356 compatible = "samsung,exynos4210-usb2-phy"; 357 - reg = <0x125B0000 0x100>; 357 + reg = <0x125b0000 0x100>; 358 358 samsung,pmureg-phandle = <&pmu_system_controller>; 359 359 clocks = <&clock CLK_USB_DEVICE>, <&clock CLK_XUSBXTI>; 360 360 clock-names = "phy", "ref"; ··· 546 546 #address-cells = <1>; 547 547 #size-cells = <0>; 548 548 compatible = "samsung,s3c2440-i2c"; 549 - reg = <0x138A0000 0x100>; 549 + reg = <0x138a0000 0x100>; 550 550 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 551 551 clocks = <&clock CLK_I2C4>; 552 552 clock-names = "i2c"; ··· 559 559 #address-cells = <1>; 560 560 #size-cells = <0>; 561 561 compatible = "samsung,s3c2440-i2c"; 562 - reg = <0x138B0000 0x100>; 562 + reg = <0x138b0000 0x100>; 563 563 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 564 564 clocks = <&clock CLK_I2C5>; 565 565 clock-names = "i2c"; ··· 572 572 #address-cells = <1>; 573 573 #size-cells = <0>; 574 574 compatible = "samsung,s3c2440-i2c"; 575 - reg = <0x138C0000 0x100>; 575 + reg = <0x138c0000 0x100>; 576 576 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 577 577 clocks = <&clock CLK_I2C6>; 578 578 clock-names = "i2c"; ··· 585 585 #address-cells = <1>; 586 586 #size-cells = <0>; 587 587 compatible = "samsung,s3c2440-i2c"; 588 - reg = <0x138D0000 0x100>; 588 + reg = <0x138d0000 0x100>; 589 589 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 590 590 clocks = <&clock CLK_I2C7>; 591 591 clock-names = "i2c"; ··· 598 598 #address-cells = <1>; 599 599 #size-cells = <0>; 600 600 compatible = "samsung,s3c2440-hdmiphy-i2c"; 601 - reg = <0x138E0000 0x100>; 601 + reg = <0x138e0000 0x100>; 602 602 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 603 603 clocks = <&clock CLK_I2C_HDMI>; 604 604 clock-names = "i2c"; ··· 657 657 658 658 pwm: pwm@139d0000 { 659 659 compatible = "samsung,exynos4210-pwm"; 660 - reg = <0x139D0000 0x1000>; 660 + reg = <0x139d0000 0x1000>; 661 661 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 662 662 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 663 663 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, ··· 712 712 713 713 tmu: tmu@100c0000 { 714 714 interrupt-parent = <&combiner>; 715 - reg = <0x100C0000 0x100>; 715 + reg = <0x100c0000 0x100>; 716 716 interrupts = <2 4>; 717 717 status = "disabled"; 718 718 #thermal-sensor-cells = <0>; ··· 739 739 740 740 hdmi: hdmi@12d00000 { 741 741 compatible = "samsung,exynos4210-hdmi"; 742 - reg = <0x12D00000 0x70000>; 742 + reg = <0x12d00000 0x70000>; 743 743 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 744 744 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", 745 745 "sclk_hdmiphy", "mout_hdmi"; ··· 756 756 757 757 hdmicec: cec@100b0000 { 758 758 compatible = "samsung,s5p-cec"; 759 - reg = <0x100B0000 0x200>; 759 + reg = <0x100b0000 0x200>; 760 760 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 761 761 clocks = <&clock CLK_HDMI_CEC>; 762 762 clock-names = "hdmicec"; ··· 770 770 mixer: mixer@12c10000 { 771 771 compatible = "samsung,exynos4210-mixer"; 772 772 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 773 - reg = <0x12C10000 0x2100>, <0x12c00000 0x300>; 773 + reg = <0x12c10000 0x2100>, <0x12c00000 0x300>; 774 774 power-domains = <&pd_tv>; 775 775 iommus = <&sysmmu_tv>; 776 776 status = "disabled"; ··· 902 902 903 903 sysmmu_tv: sysmmu@12e20000 { 904 904 compatible = "samsung,exynos-sysmmu"; 905 - reg = <0x12E20000 0x1000>; 905 + reg = <0x12e20000 0x1000>; 906 906 interrupt-parent = <&combiner>; 907 907 interrupts = <5 4>; 908 908 clock-names = "sysmmu", "master"; ··· 913 913 914 914 sysmmu_fimc0: sysmmu@11a20000 { 915 915 compatible = "samsung,exynos-sysmmu"; 916 - reg = <0x11A20000 0x1000>; 916 + reg = <0x11a20000 0x1000>; 917 917 interrupt-parent = <&combiner>; 918 918 interrupts = <4 2>; 919 919 clock-names = "sysmmu", "master"; ··· 924 924 925 925 sysmmu_fimc1: sysmmu@11a30000 { 926 926 compatible = "samsung,exynos-sysmmu"; 927 - reg = <0x11A30000 0x1000>; 927 + reg = <0x11a30000 0x1000>; 928 928 interrupt-parent = <&combiner>; 929 929 interrupts = <4 3>; 930 930 clock-names = "sysmmu", "master"; ··· 935 935 936 936 sysmmu_fimc2: sysmmu@11a40000 { 937 937 compatible = "samsung,exynos-sysmmu"; 938 - reg = <0x11A40000 0x1000>; 938 + reg = <0x11a40000 0x1000>; 939 939 interrupt-parent = <&combiner>; 940 940 interrupts = <4 4>; 941 941 clock-names = "sysmmu", "master"; ··· 946 946 947 947 sysmmu_fimc3: sysmmu@11a50000 { 948 948 compatible = "samsung,exynos-sysmmu"; 949 - reg = <0x11A50000 0x1000>; 949 + reg = <0x11a50000 0x1000>; 950 950 interrupt-parent = <&combiner>; 951 951 interrupts = <4 5>; 952 952 clock-names = "sysmmu", "master"; ··· 957 957 958 958 sysmmu_jpeg: sysmmu@11a60000 { 959 959 compatible = "samsung,exynos-sysmmu"; 960 - reg = <0x11A60000 0x1000>; 960 + reg = <0x11a60000 0x1000>; 961 961 interrupt-parent = <&combiner>; 962 962 interrupts = <4 6>; 963 963 clock-names = "sysmmu", "master"; ··· 968 968 969 969 sysmmu_rotator: sysmmu@12a30000 { 970 970 compatible = "samsung,exynos-sysmmu"; 971 - reg = <0x12A30000 0x1000>; 971 + reg = <0x12a30000 0x1000>; 972 972 interrupt-parent = <&combiner>; 973 973 interrupts = <5 0>; 974 974 clock-names = "sysmmu", "master"; ··· 979 979 980 980 sysmmu_fimd0: sysmmu@11e20000 { 981 981 compatible = "samsung,exynos-sysmmu"; 982 - reg = <0x11E20000 0x1000>; 982 + reg = <0x11e20000 0x1000>; 983 983 interrupt-parent = <&combiner>; 984 984 interrupts = <5 2>; 985 985 clock-names = "sysmmu", "master";
+2 -2
arch/arm/boot/dts/exynos4210.dtsi
··· 103 103 104 104 pd_lcd1: power-domain@10023ca0 { 105 105 compatible = "samsung,exynos4210-pd"; 106 - reg = <0x10023CA0 0x20>; 106 + reg = <0x10023ca0 0x20>; 107 107 #power-domain-cells = <0>; 108 108 label = "LCD1"; 109 109 }; ··· 195 195 196 196 sysmmu_g2d: sysmmu@12a20000 { 197 197 compatible = "samsung,exynos-sysmmu"; 198 - reg = <0x12A20000 0x1000>; 198 + reg = <0x12a20000 0x1000>; 199 199 interrupt-parent = <&combiner>; 200 200 interrupts = <4 7>; 201 201 clock-names = "sysmmu", "master";
+1 -1
arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi
··· 25 25 26 26 firmware@203f000 { 27 27 compatible = "samsung,secure-firmware"; 28 - reg = <0x0203F000 0x1000>; 28 + reg = <0x0203f000 0x1000>; 29 29 }; 30 30 31 31 fixed-rate-clocks {
+1 -1
arch/arm/boot/dts/exynos4412-midas.dtsi
··· 33 33 34 34 firmware@204f000 { 35 35 compatible = "samsung,secure-firmware"; 36 - reg = <0x0204F000 0x1000>; 36 + reg = <0x0204f000 0x1000>; 37 37 }; 38 38 39 39 fixed-rate-clocks {
+1 -1
arch/arm/boot/dts/exynos4412-odroid-common.dtsi
··· 19 19 20 20 firmware@204f000 { 21 21 compatible = "samsung,secure-firmware"; 22 - reg = <0x0204F000 0x1000>; 22 + reg = <0x0204f000 0x1000>; 23 23 }; 24 24 25 25 gpio_keys: gpio-keys {
+1 -1
arch/arm/boot/dts/exynos4412-odroidu3.dts
··· 23 23 24 24 memory@40000000 { 25 25 device_type = "memory"; 26 - reg = <0x40000000 0x7FF00000>; 26 + reg = <0x40000000 0x7ff00000>; 27 27 }; 28 28 29 29 vbus_otg_reg: regulator-1 {
+1 -1
arch/arm/boot/dts/exynos4412-odroidx.dts
··· 22 22 23 23 memory@40000000 { 24 24 device_type = "memory"; 25 - reg = <0x40000000 0x3FF00000>; 25 + reg = <0x40000000 0x3ff00000>; 26 26 }; 27 27 28 28 leds {
+1 -1
arch/arm/boot/dts/exynos4412-odroidx2.dts
··· 17 17 18 18 memory@40000000 { 19 19 device_type = "memory"; 20 - reg = <0x40000000 0x7FF00000>; 20 + reg = <0x40000000 0x7ff00000>; 21 21 }; 22 22 };
+1 -1
arch/arm/boot/dts/exynos4412-origen.dts
··· 31 31 32 32 firmware@203f000 { 33 33 compatible = "samsung,secure-firmware"; 34 - reg = <0x0203F000 0x1000>; 34 + reg = <0x0203f000 0x1000>; 35 35 }; 36 36 37 37 mmc_reg: regulator-0 {
+2 -2
arch/arm/boot/dts/exynos4412-p4note.dtsi
··· 32 32 33 33 firmware@204f000 { 34 34 compatible = "samsung,secure-firmware"; 35 - reg = <0x0204F000 0x1000>; 35 + reg = <0x0204f000 0x1000>; 36 36 }; 37 37 38 38 fixed-rate-clocks { ··· 198 198 stmpe_adc { 199 199 compatible = "st,stmpe-adc"; 200 200 #io-channel-cells = <1>; 201 - st,norequest-mask = <0x2F>; 201 + st,norequest-mask = <0x2f>; 202 202 }; 203 203 }; 204 204 };
+14 -14
arch/arm/boot/dts/exynos4412.dtsi
··· 55 55 cpu0: cpu@a00 { 56 56 device_type = "cpu"; 57 57 compatible = "arm,cortex-a9"; 58 - reg = <0xA00>; 58 + reg = <0xa00>; 59 59 clocks = <&clock CLK_ARM_CLK>; 60 60 clock-names = "cpu"; 61 61 operating-points-v2 = <&cpu0_opp_table>; ··· 65 65 cpu1: cpu@a01 { 66 66 device_type = "cpu"; 67 67 compatible = "arm,cortex-a9"; 68 - reg = <0xA01>; 68 + reg = <0xa01>; 69 69 clocks = <&clock CLK_ARM_CLK>; 70 70 clock-names = "cpu"; 71 71 operating-points-v2 = <&cpu0_opp_table>; ··· 75 75 cpu2: cpu@a02 { 76 76 device_type = "cpu"; 77 77 compatible = "arm,cortex-a9"; 78 - reg = <0xA02>; 78 + reg = <0xa02>; 79 79 clocks = <&clock CLK_ARM_CLK>; 80 80 clock-names = "cpu"; 81 81 operating-points-v2 = <&cpu0_opp_table>; ··· 85 85 cpu3: cpu@a03 { 86 86 device_type = "cpu"; 87 87 compatible = "arm,cortex-a9"; 88 - reg = <0xA03>; 88 + reg = <0xa03>; 89 89 clocks = <&clock CLK_ARM_CLK>; 90 90 clock-names = "cpu"; 91 91 operating-points-v2 = <&cpu0_opp_table>; ··· 201 201 202 202 pinctrl_3: pinctrl@106e0000 { 203 203 compatible = "samsung,exynos4x12-pinctrl"; 204 - reg = <0x106E0000 0x1000>; 204 + reg = <0x106e0000 0x1000>; 205 205 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 206 206 }; 207 207 ··· 225 225 226 226 pd_isp: power-domain@10023ca0 { 227 227 compatible = "samsung,exynos4210-pd"; 228 - reg = <0x10023CA0 0x20>; 228 + reg = <0x10023ca0 0x20>; 229 229 #power-domain-cells = <0>; 230 230 label = "ISP"; 231 231 }; ··· 285 285 286 286 adc: adc@126c0000 { 287 287 compatible = "samsung,exynos4212-adc"; 288 - reg = <0x126C0000 0x100>; 288 + reg = <0x126c0000 0x100>; 289 289 interrupt-parent = <&combiner>; 290 290 interrupts = <10 3>; 291 291 clocks = <&clock CLK_TSADC>; ··· 318 318 319 319 sysmmu_g2d: sysmmu@10a40000 { 320 320 compatible = "samsung,exynos-sysmmu"; 321 - reg = <0x10A40000 0x1000>; 321 + reg = <0x10a40000 0x1000>; 322 322 interrupt-parent = <&combiner>; 323 323 interrupts = <4 7>; 324 324 clock-names = "sysmmu", "master"; ··· 350 350 351 351 sysmmu_fimc_fd: sysmmu@122a0000 { 352 352 compatible = "samsung,exynos-sysmmu"; 353 - reg = <0x122A0000 0x1000>; 353 + reg = <0x122a0000 0x1000>; 354 354 interrupt-parent = <&combiner>; 355 355 interrupts = <16 4>; 356 356 power-domains = <&pd_isp>; ··· 361 361 362 362 sysmmu_fimc_mcuctl: sysmmu@122b0000 { 363 363 compatible = "samsung,exynos-sysmmu"; 364 - reg = <0x122B0000 0x1000>; 364 + reg = <0x122b0000 0x1000>; 365 365 interrupt-parent = <&combiner>; 366 366 interrupts = <16 5>; 367 367 power-domains = <&pd_isp>; ··· 372 372 373 373 sysmmu_fimc_lite0: sysmmu@123b0000 { 374 374 compatible = "samsung,exynos-sysmmu"; 375 - reg = <0x123B0000 0x1000>; 375 + reg = <0x123b0000 0x1000>; 376 376 interrupt-parent = <&combiner>; 377 377 interrupts = <16 0>; 378 378 power-domains = <&pd_isp>; ··· 384 384 385 385 sysmmu_fimc_lite1: sysmmu@123c0000 { 386 386 compatible = "samsung,exynos-sysmmu"; 387 - reg = <0x123C0000 0x1000>; 387 + reg = <0x123c0000 0x1000>; 388 388 interrupt-parent = <&combiner>; 389 389 interrupts = <16 1>; 390 390 power-domains = <&pd_isp>; ··· 615 615 616 616 fimc_lite_1: fimc-lite@123a0000 { 617 617 compatible = "samsung,exynos4212-fimc-lite"; 618 - reg = <0x123A0000 0x1000>; 618 + reg = <0x123a0000 0x1000>; 619 619 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 620 620 power-domains = <&pd_isp>; 621 621 clocks = <&isp_clock CLK_ISP_FIMC_LITE1>; ··· 812 812 compatible = "samsung,exynos4412-tmu"; 813 813 interrupt-parent = <&combiner>; 814 814 interrupts = <2 4>; 815 - reg = <0x100C0000 0x100>; 815 + reg = <0x100c0000 0x100>; 816 816 clocks = <&clock CLK_TMU_APBIF>; 817 817 clock-names = "tmu_apbif"; 818 818 status = "disabled";
+11 -11
arch/arm/boot/dts/exynos5.dtsi
··· 104 104 105 105 serial_0: serial@12c00000 { 106 106 compatible = "samsung,exynos4210-uart"; 107 - reg = <0x12C00000 0x100>; 107 + reg = <0x12c00000 0x100>; 108 108 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 109 109 }; 110 110 111 111 serial_1: serial@12c10000 { 112 112 compatible = "samsung,exynos4210-uart"; 113 - reg = <0x12C10000 0x100>; 113 + reg = <0x12c10000 0x100>; 114 114 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 115 115 }; 116 116 117 117 serial_2: serial@12c20000 { 118 118 compatible = "samsung,exynos4210-uart"; 119 - reg = <0x12C20000 0x100>; 119 + reg = <0x12c20000 0x100>; 120 120 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 121 121 }; 122 122 123 123 serial_3: serial@12c30000 { 124 124 compatible = "samsung,exynos4210-uart"; 125 - reg = <0x12C30000 0x100>; 125 + reg = <0x12c30000 0x100>; 126 126 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 127 127 }; 128 128 129 129 i2c_0: i2c@12c60000 { 130 130 compatible = "samsung,s3c2440-i2c"; 131 - reg = <0x12C60000 0x100>; 131 + reg = <0x12c60000 0x100>; 132 132 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 133 133 #address-cells = <1>; 134 134 #size-cells = <0>; ··· 138 138 139 139 i2c_1: i2c@12c70000 { 140 140 compatible = "samsung,s3c2440-i2c"; 141 - reg = <0x12C70000 0x100>; 141 + reg = <0x12c70000 0x100>; 142 142 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 143 143 #address-cells = <1>; 144 144 #size-cells = <0>; ··· 148 148 149 149 i2c_2: i2c@12c80000 { 150 150 compatible = "samsung,s3c2440-i2c"; 151 - reg = <0x12C80000 0x100>; 151 + reg = <0x12c80000 0x100>; 152 152 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 153 153 #address-cells = <1>; 154 154 #size-cells = <0>; ··· 158 158 159 159 i2c_3: i2c@12c90000 { 160 160 compatible = "samsung,s3c2440-i2c"; 161 - reg = <0x12C90000 0x100>; 161 + reg = <0x12c90000 0x100>; 162 162 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 163 163 #address-cells = <1>; 164 164 #size-cells = <0>; ··· 168 168 169 169 pwm: pwm@12dd0000 { 170 170 compatible = "samsung,exynos4210-pwm"; 171 - reg = <0x12DD0000 0x100>; 171 + reg = <0x12dd0000 0x100>; 172 172 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 173 173 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 174 174 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, ··· 180 180 181 181 rtc: rtc@101e0000 { 182 182 compatible = "samsung,s3c6410-rtc"; 183 - reg = <0x101E0000 0x100>; 183 + reg = <0x101e0000 0x100>; 184 184 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 185 185 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 186 186 status = "disabled"; ··· 198 198 199 199 dp: dp-controller@145b0000 { 200 200 compatible = "samsung,exynos5-dp"; 201 - reg = <0x145B0000 0x1000>; 201 + reg = <0x145b0000 0x1000>; 202 202 interrupts = <10 3>; 203 203 interrupt-parent = <&combiner>; 204 204 status = "disabled";
+35 -35
arch/arm/boot/dts/exynos5250.dtsi
··· 216 216 217 217 pd_disp1: power-domain@100440a0 { 218 218 compatible = "samsung,exynos4210-pd"; 219 - reg = <0x100440A0 0x20>; 219 + reg = <0x100440a0 0x20>; 220 220 #power-domain-cells = <0>; 221 221 label = "DISP1"; 222 222 }; 223 223 224 224 pd_mau: power-domain@100440c0 { 225 225 compatible = "samsung,exynos4210-pd"; 226 - reg = <0x100440C0 0x20>; 226 + reg = <0x100440c0 0x20>; 227 227 #power-domain-cells = <0>; 228 228 label = "MAU"; 229 229 }; ··· 236 236 237 237 clock_audss: audss-clock-controller@3810000 { 238 238 compatible = "samsung,exynos5250-audss-clock"; 239 - reg = <0x03810000 0x0C>; 239 + reg = <0x03810000 0x0c>; 240 240 #clock-cells = <1>; 241 241 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>, 242 242 <&clock CLK_SCLK_AUDIO0>, <&clock CLK_DIV_PCM0>; ··· 247 247 timer@101c0000 { 248 248 compatible = "samsung,exynos5250-mct", 249 249 "samsung,exynos4210-mct"; 250 - reg = <0x101C0000 0x800>; 250 + reg = <0x101c0000 0x800>; 251 251 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; 252 252 clock-names = "fin_pll", "mct"; 253 253 interrupts-extended = <&combiner 23 3>, ··· 302 302 303 303 watchdog@101d0000 { 304 304 compatible = "samsung,exynos5250-wdt"; 305 - reg = <0x101D0000 0x100>; 305 + reg = <0x101d0000 0x100>; 306 306 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 307 307 clocks = <&clock CLK_WDT>; 308 308 clock-names = "watchdog"; ··· 322 322 323 323 rotator: rotator@11c00000 { 324 324 compatible = "samsung,exynos5250-rotator"; 325 - reg = <0x11C00000 0x64>; 325 + reg = <0x11c00000 0x64>; 326 326 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 327 327 clocks = <&clock CLK_ROTATOR>; 328 328 clock-names = "rotator"; ··· 387 387 388 388 sata: sata@122f0000 { 389 389 compatible = "snps,dwc-ahci"; 390 - reg = <0x122F0000 0x1ff>; 390 + reg = <0x122f0000 0x1ff>; 391 391 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 392 392 clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>; 393 393 clock-names = "sata", "pclk"; ··· 410 410 /* i2c_0-3 are defined in exynos5.dtsi */ 411 411 i2c_4: i2c@12ca0000 { 412 412 compatible = "samsung,s3c2440-i2c"; 413 - reg = <0x12CA0000 0x100>; 413 + reg = <0x12ca0000 0x100>; 414 414 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 415 415 #address-cells = <1>; 416 416 #size-cells = <0>; ··· 423 423 424 424 i2c_5: i2c@12cb0000 { 425 425 compatible = "samsung,s3c2440-i2c"; 426 - reg = <0x12CB0000 0x100>; 426 + reg = <0x12cb0000 0x100>; 427 427 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 428 428 #address-cells = <1>; 429 429 #size-cells = <0>; ··· 436 436 437 437 i2c_6: i2c@12cc0000 { 438 438 compatible = "samsung,s3c2440-i2c"; 439 - reg = <0x12CC0000 0x100>; 439 + reg = <0x12cc0000 0x100>; 440 440 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 441 441 #address-cells = <1>; 442 442 #size-cells = <0>; ··· 449 449 450 450 i2c_7: i2c@12cd0000 { 451 451 compatible = "samsung,s3c2440-i2c"; 452 - reg = <0x12CD0000 0x100>; 452 + reg = <0x12cd0000 0x100>; 453 453 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 454 454 #address-cells = <1>; 455 455 #size-cells = <0>; ··· 462 462 463 463 i2c_8: i2c@12ce0000 { 464 464 compatible = "samsung,s3c2440-hdmiphy-i2c"; 465 - reg = <0x12CE0000 0x1000>; 465 + reg = <0x12ce0000 0x1000>; 466 466 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 467 467 #address-cells = <1>; 468 468 #size-cells = <0>; ··· 478 478 479 479 i2c_9: i2c@121d0000 { 480 480 compatible = "samsung,exynos5-sata-phy-i2c"; 481 - reg = <0x121D0000 0x100>; 481 + reg = <0x121d0000 0x100>; 482 482 #address-cells = <1>; 483 483 #size-cells = <0>; 484 484 clocks = <&clock CLK_SATA_PHYI2C>; ··· 608 608 i2s1: i2s@12d60000 { 609 609 compatible = "samsung,s3c6410-i2s"; 610 610 status = "disabled"; 611 - reg = <0x12D60000 0x100>; 611 + reg = <0x12d60000 0x100>; 612 612 dmas = <&pdma1 12>, 613 613 <&pdma1 11>; 614 614 dma-names = "tx", "rx"; ··· 623 623 i2s2: i2s@12d70000 { 624 624 compatible = "samsung,s3c6410-i2s"; 625 625 status = "disabled"; 626 - reg = <0x12D70000 0x100>; 626 + reg = <0x12d70000 0x100>; 627 627 dmas = <&pdma0 12>, 628 628 <&pdma0 11>; 629 629 dma-names = "tx", "rx"; ··· 695 695 696 696 pdma0: dma-controller@121a0000 { 697 697 compatible = "arm,pl330", "arm,primecell"; 698 - reg = <0x121A0000 0x1000>; 698 + reg = <0x121a0000 0x1000>; 699 699 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 700 700 clocks = <&clock CLK_PDMA0>; 701 701 clock-names = "apb_pclk"; ··· 704 704 705 705 pdma1: dma-controller@121b0000 { 706 706 compatible = "arm,pl330", "arm,primecell"; 707 - reg = <0x121B0000 0x1000>; 707 + reg = <0x121b0000 0x1000>; 708 708 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 709 709 clocks = <&clock CLK_PDMA1>; 710 710 clock-names = "apb_pclk"; ··· 722 722 723 723 mdma1: dma-controller@11c10000 { 724 724 compatible = "arm,pl330", "arm,primecell"; 725 - reg = <0x11C10000 0x1000>; 725 + reg = <0x11c10000 0x1000>; 726 726 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 727 727 clocks = <&clock CLK_MDMA1>; 728 728 clock-names = "apb_pclk"; ··· 787 787 788 788 hdmicec: cec@101b0000 { 789 789 compatible = "samsung,s5p-cec"; 790 - reg = <0x101B0000 0x200>; 790 + reg = <0x101b0000 0x200>; 791 791 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 792 792 clocks = <&clock CLK_HDMI_CEC>; 793 793 clock-names = "hdmicec"; ··· 838 838 839 839 adc: adc@12d10000 { 840 840 compatible = "samsung,exynos-adc-v1"; 841 - reg = <0x12D10000 0x100>; 841 + reg = <0x12d10000 0x100>; 842 842 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 843 843 clocks = <&clock CLK_ADC>; 844 844 clock-names = "adc"; ··· 849 849 850 850 sysmmu_g2d: sysmmu@10a60000 { 851 851 compatible = "samsung,exynos-sysmmu"; 852 - reg = <0x10A60000 0x1000>; 852 + reg = <0x10a60000 0x1000>; 853 853 interrupt-parent = <&combiner>; 854 854 interrupts = <24 5>; 855 855 clock-names = "sysmmu", "master"; ··· 881 881 882 882 sysmmu_rotator: sysmmu@11d40000 { 883 883 compatible = "samsung,exynos-sysmmu"; 884 - reg = <0x11D40000 0x1000>; 884 + reg = <0x11d40000 0x1000>; 885 885 interrupt-parent = <&combiner>; 886 886 interrupts = <4 0>; 887 887 clock-names = "sysmmu", "master"; ··· 891 891 892 892 sysmmu_jpeg: sysmmu@11f20000 { 893 893 compatible = "samsung,exynos-sysmmu"; 894 - reg = <0x11F20000 0x1000>; 894 + reg = <0x11f20000 0x1000>; 895 895 interrupt-parent = <&combiner>; 896 896 interrupts = <4 2>; 897 897 power-domains = <&pd_gsc>; ··· 922 922 923 923 sysmmu_fimc_fd: sysmmu@132a0000 { 924 924 compatible = "samsung,exynos-sysmmu"; 925 - reg = <0x132A0000 0x1000>; 925 + reg = <0x132a0000 0x1000>; 926 926 interrupt-parent = <&combiner>; 927 927 interrupts = <5 0>; 928 928 clock-names = "sysmmu"; ··· 952 952 953 953 sysmmu_fimc_mcuctl: sysmmu@132b0000 { 954 954 compatible = "samsung,exynos-sysmmu"; 955 - reg = <0x132B0000 0x1000>; 955 + reg = <0x132b0000 0x1000>; 956 956 interrupt-parent = <&combiner>; 957 957 interrupts = <5 4>; 958 958 clock-names = "sysmmu"; ··· 962 962 963 963 sysmmu_fimc_odc: sysmmu@132c0000 { 964 964 compatible = "samsung,exynos-sysmmu"; 965 - reg = <0x132C0000 0x1000>; 965 + reg = <0x132c0000 0x1000>; 966 966 interrupt-parent = <&combiner>; 967 967 interrupts = <11 0>; 968 968 clock-names = "sysmmu"; ··· 972 972 973 973 sysmmu_fimc_dis0: sysmmu@132d0000 { 974 974 compatible = "samsung,exynos-sysmmu"; 975 - reg = <0x132D0000 0x1000>; 975 + reg = <0x132d0000 0x1000>; 976 976 interrupt-parent = <&combiner>; 977 977 interrupts = <10 4>; 978 978 clock-names = "sysmmu"; ··· 982 982 983 983 sysmmu_fimc_dis1: sysmmu@132e0000 { 984 984 compatible = "samsung,exynos-sysmmu"; 985 - reg = <0x132E0000 0x1000>; 985 + reg = <0x132e0000 0x1000>; 986 986 interrupt-parent = <&combiner>; 987 987 interrupts = <9 4>; 988 988 clock-names = "sysmmu"; ··· 992 992 993 993 sysmmu_fimc_3dnr: sysmmu@132f0000 { 994 994 compatible = "samsung,exynos-sysmmu"; 995 - reg = <0x132F0000 0x1000>; 995 + reg = <0x132f0000 0x1000>; 996 996 interrupt-parent = <&combiner>; 997 997 interrupts = <5 6>; 998 998 clock-names = "sysmmu"; ··· 1002 1002 1003 1003 sysmmu_fimc_lite0: sysmmu@13c40000 { 1004 1004 compatible = "samsung,exynos-sysmmu"; 1005 - reg = <0x13C40000 0x1000>; 1005 + reg = <0x13c40000 0x1000>; 1006 1006 interrupt-parent = <&combiner>; 1007 1007 interrupts = <3 4>; 1008 1008 power-domains = <&pd_gsc>; ··· 1013 1013 1014 1014 sysmmu_fimc_lite1: sysmmu@13c50000 { 1015 1015 compatible = "samsung,exynos-sysmmu"; 1016 - reg = <0x13C50000 0x1000>; 1016 + reg = <0x13c50000 0x1000>; 1017 1017 interrupt-parent = <&combiner>; 1018 1018 interrupts = <24 1>; 1019 1019 power-domains = <&pd_gsc>; ··· 1024 1024 1025 1025 sysmmu_gsc0: sysmmu@13e80000 { 1026 1026 compatible = "samsung,exynos-sysmmu"; 1027 - reg = <0x13E80000 0x1000>; 1027 + reg = <0x13e80000 0x1000>; 1028 1028 interrupt-parent = <&combiner>; 1029 1029 interrupts = <2 0>; 1030 1030 power-domains = <&pd_gsc>; ··· 1035 1035 1036 1036 sysmmu_gsc1: sysmmu@13e90000 { 1037 1037 compatible = "samsung,exynos-sysmmu"; 1038 - reg = <0x13E90000 0x1000>; 1038 + reg = <0x13e90000 0x1000>; 1039 1039 interrupt-parent = <&combiner>; 1040 1040 interrupts = <2 2>; 1041 1041 power-domains = <&pd_gsc>; ··· 1046 1046 1047 1047 sysmmu_gsc2: sysmmu@13ea0000 { 1048 1048 compatible = "samsung,exynos-sysmmu"; 1049 - reg = <0x13EA0000 0x1000>; 1049 + reg = <0x13ea0000 0x1000>; 1050 1050 interrupt-parent = <&combiner>; 1051 1051 interrupts = <2 4>; 1052 1052 power-domains = <&pd_gsc>; ··· 1057 1057 1058 1058 sysmmu_gsc3: sysmmu@13eb0000 { 1059 1059 compatible = "samsung,exynos-sysmmu"; 1060 - reg = <0x13EB0000 0x1000>; 1060 + reg = <0x13eb0000 0x1000>; 1061 1061 interrupt-parent = <&combiner>; 1062 1062 interrupts = <2 6>; 1063 1063 power-domains = <&pd_gsc>;
+18 -18
arch/arm/boot/dts/exynos5260.dtsi
··· 177 177 178 178 clock_g2d: clock-controller@10a00000 { 179 179 compatible = "samsung,exynos5260-clock-g2d"; 180 - reg = <0x10A00000 0x10000>; 180 + reg = <0x10a00000 0x10000>; 181 181 #clock-cells = <1>; 182 182 clocks = <&fin_pll>, 183 183 <&clock_top TOP_DOUT_ACLK_G2D_333>; ··· 187 187 188 188 clock_mif: clock-controller@10ce0000 { 189 189 compatible = "samsung,exynos5260-clock-mif"; 190 - reg = <0x10CE0000 0x10000>; 190 + reg = <0x10ce0000 0x10000>; 191 191 #clock-cells = <1>; 192 192 clocks = <&fin_pll>; 193 193 clock-names = "fin_pll"; ··· 213 213 214 214 clock_fsys: clock-controller@122e0000 { 215 215 compatible = "samsung,exynos5260-clock-fsys"; 216 - reg = <0x122E0000 0x10000>; 216 + reg = <0x122e0000 0x10000>; 217 217 #clock-cells = <1>; 218 218 clocks = <&fin_pll>, 219 219 <&fin_pll>, ··· 233 233 234 234 clock_aud: clock-controller@128c0000 { 235 235 compatible = "samsung,exynos5260-clock-aud"; 236 - reg = <0x128C0000 0x10000>; 236 + reg = <0x128c0000 0x10000>; 237 237 #clock-cells = <1>; 238 238 clocks = <&fin_pll>, 239 239 <&clock_top TOP_FOUT_AUD_PLL>, ··· 247 247 248 248 clock_isp: clock-controller@133c0000 { 249 249 compatible = "samsung,exynos5260-clock-isp"; 250 - reg = <0x133C0000 0x10000>; 250 + reg = <0x133c0000 0x10000>; 251 251 #clock-cells = <1>; 252 252 clocks = <&fin_pll>, 253 253 <&clock_top TOP_DOUT_ACLK_ISP1_266>, ··· 261 261 262 262 clock_gscl: clock-controller@13f00000 { 263 263 compatible = "samsung,exynos5260-clock-gscl"; 264 - reg = <0x13F00000 0x10000>; 264 + reg = <0x13f00000 0x10000>; 265 265 #clock-cells = <1>; 266 266 clocks = <&fin_pll>, 267 267 <&clock_top TOP_DOUT_ACLK_GSCL_400>, ··· 335 335 mct: timer@100b0000 { 336 336 compatible = "samsung,exynos5260-mct", 337 337 "samsung,exynos4210-mct"; 338 - reg = <0x100B0000 0x1000>; 338 + reg = <0x100b0000 0x1000>; 339 339 clocks = <&fin_pll>, <&clock_peri PERI_CLK_MCT>; 340 340 clock-names = "fin_pll", "mct"; 341 341 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, ··· 356 356 compatible = "arm,cci-400"; 357 357 #address-cells = <1>; 358 358 #size-cells = <1>; 359 - reg = <0x10F00000 0x1000>; 360 - ranges = <0x0 0x10F00000 0x6000>; 359 + reg = <0x10f00000 0x1000>; 360 + ranges = <0x0 0x10f00000 0x6000>; 361 361 362 362 cci_control0: slave-if@4000 { 363 363 compatible = "arm,cci-400-ctrl-if"; ··· 392 392 393 393 pinctrl_2: pinctrl@128b0000 { 394 394 compatible = "samsung,exynos5260-pinctrl"; 395 - reg = <0x128B0000 0x1000>; 395 + reg = <0x128b0000 0x1000>; 396 396 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 397 397 }; 398 398 399 399 pmu_system_controller: system-controller@10d50000 { 400 400 compatible = "samsung,exynos5260-pmu", "syscon"; 401 - reg = <0x10D50000 0x10000>; 401 + reg = <0x10d50000 0x10000>; 402 402 }; 403 403 404 404 uart0: serial@12c00000 { 405 405 compatible = "samsung,exynos4210-uart"; 406 - reg = <0x12C00000 0x100>; 406 + reg = <0x12c00000 0x100>; 407 407 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 408 408 clocks = <&clock_peri PERI_CLK_UART0>, <&clock_peri PERI_SCLK_UART0>; 409 409 clock-names = "uart", "clk_uart_baud0"; ··· 412 412 413 413 uart1: serial@12c10000 { 414 414 compatible = "samsung,exynos4210-uart"; 415 - reg = <0x12C10000 0x100>; 415 + reg = <0x12c10000 0x100>; 416 416 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 417 417 clocks = <&clock_peri PERI_CLK_UART1>, <&clock_peri PERI_SCLK_UART1>; 418 418 clock-names = "uart", "clk_uart_baud0"; ··· 421 421 422 422 uart2: serial@12c20000 { 423 423 compatible = "samsung,exynos4210-uart"; 424 - reg = <0x12C20000 0x100>; 424 + reg = <0x12c20000 0x100>; 425 425 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 426 426 clocks = <&clock_peri PERI_CLK_UART2>, <&clock_peri PERI_SCLK_UART2>; 427 427 clock-names = "uart", "clk_uart_baud0"; ··· 499 499 500 500 hsi2c_0: i2c@12da0000 { 501 501 compatible = "samsung,exynos5260-hsi2c"; 502 - reg = <0x12DA0000 0x1000>; 502 + reg = <0x12da0000 0x1000>; 503 503 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 504 504 #address-cells = <1>; 505 505 #size-cells = <0>; ··· 512 512 513 513 hsi2c_1: i2c@12db0000 { 514 514 compatible = "samsung,exynos5260-hsi2c"; 515 - reg = <0x12DB0000 0x1000>; 515 + reg = <0x12db0000 0x1000>; 516 516 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 517 517 #address-cells = <1>; 518 518 #size-cells = <0>; ··· 525 525 526 526 hsi2c_2: i2c@12dc0000 { 527 527 compatible = "samsung,exynos5260-hsi2c"; 528 - reg = <0x12DC0000 0x1000>; 528 + reg = <0x12dc0000 0x1000>; 529 529 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 530 530 #address-cells = <1>; 531 531 #size-cells = <0>; ··· 538 538 539 539 hsi2c_3: i2c@12dd0000 { 540 540 compatible = "samsung,exynos5260-hsi2c"; 541 - reg = <0x12DD0000 0x1000>; 541 + reg = <0x12dd0000 0x1000>; 542 542 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 543 543 #address-cells = <1>; 544 544 #size-cells = <0>;
+1 -1
arch/arm/boot/dts/exynos5410.dtsi
··· 81 81 82 82 clock_audss: audss-clock-controller@3810000 { 83 83 compatible = "samsung,exynos5410-audss-clock"; 84 - reg = <0x03810000 0x0C>; 84 + reg = <0x03810000 0x0c>; 85 85 #clock-cells = <1>; 86 86 clocks = <&fin_pll>, <&clock CLK_FOUT_EPLL>; 87 87 clock-names = "pll_ref", "pll_in";
+33 -33
arch/arm/boot/dts/exynos5420.dtsi
··· 182 182 183 183 clock_audss: audss-clock-controller@3810000 { 184 184 compatible = "samsung,exynos5420-audss-clock"; 185 - reg = <0x03810000 0x0C>; 185 + reg = <0x03810000 0x0c>; 186 186 #clock-cells = <1>; 187 187 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>, 188 188 <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>; ··· 262 262 263 263 nocp_mem0_0: nocp@10ca1000 { 264 264 compatible = "samsung,exynos5420-nocp"; 265 - reg = <0x10CA1000 0x200>; 265 + reg = <0x10ca1000 0x200>; 266 266 status = "disabled"; 267 267 }; 268 268 269 269 nocp_mem0_1: nocp@10ca1400 { 270 270 compatible = "samsung,exynos5420-nocp"; 271 - reg = <0x10CA1400 0x200>; 271 + reg = <0x10ca1400 0x200>; 272 272 status = "disabled"; 273 273 }; 274 274 275 275 nocp_mem1_0: nocp@10ca1800 { 276 276 compatible = "samsung,exynos5420-nocp"; 277 - reg = <0x10CA1800 0x200>; 277 + reg = <0x10ca1800 0x200>; 278 278 status = "disabled"; 279 279 }; 280 280 281 281 nocp_mem1_1: nocp@10ca1c00 { 282 282 compatible = "samsung,exynos5420-nocp"; 283 - reg = <0x10CA1C00 0x200>; 283 + reg = <0x10ca1c00 0x200>; 284 284 status = "disabled"; 285 285 }; 286 286 287 287 nocp_g3d_0: nocp@11a51000 { 288 288 compatible = "samsung,exynos5420-nocp"; 289 - reg = <0x11A51000 0x200>; 289 + reg = <0x11a51000 0x200>; 290 290 status = "disabled"; 291 291 }; 292 292 293 293 nocp_g3d_1: nocp@11a51400 { 294 294 compatible = "samsung,exynos5420-nocp"; 295 - reg = <0x11A51400 0x200>; 295 + reg = <0x11a51400 0x200>; 296 296 status = "disabled"; 297 297 }; 298 298 ··· 374 374 375 375 disp_pd: power-domain@100440c0 { 376 376 compatible = "samsung,exynos4210-pd"; 377 - reg = <0x100440C0 0x20>; 377 + reg = <0x100440c0 0x20>; 378 378 #power-domain-cells = <0>; 379 379 label = "DISP"; 380 380 }; 381 381 382 382 mau_pd: power-domain@100440e0 { 383 383 compatible = "samsung,exynos4210-pd"; 384 - reg = <0x100440E0 0x20>; 384 + reg = <0x100440e0 0x20>; 385 385 #power-domain-cells = <0>; 386 386 label = "MAU"; 387 387 }; ··· 442 442 443 443 pdma0: dma-controller@121a0000 { 444 444 compatible = "arm,pl330", "arm,primecell"; 445 - reg = <0x121A0000 0x1000>; 445 + reg = <0x121a0000 0x1000>; 446 446 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 447 447 clocks = <&clock CLK_PDMA0>; 448 448 clock-names = "apb_pclk"; ··· 451 451 452 452 pdma1: dma-controller@121b0000 { 453 453 compatible = "arm,pl330", "arm,primecell"; 454 - reg = <0x121B0000 0x1000>; 454 + reg = <0x121b0000 0x1000>; 455 455 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 456 456 clocks = <&clock CLK_PDMA1>; 457 457 clock-names = "apb_pclk"; ··· 469 469 470 470 mdma1: dma-controller@11c10000 { 471 471 compatible = "arm,pl330", "arm,primecell"; 472 - reg = <0x11C10000 0x1000>; 472 + reg = <0x11c10000 0x1000>; 473 473 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 474 474 clocks = <&clock CLK_MDMA1>; 475 475 clock-names = "apb_pclk"; ··· 507 507 508 508 i2s1: i2s@12d60000 { 509 509 compatible = "samsung,exynos5420-i2s"; 510 - reg = <0x12D60000 0x100>; 510 + reg = <0x12d60000 0x100>; 511 511 dmas = <&pdma1 12>, 512 512 <&pdma1 11>; 513 513 dma-names = "tx", "rx"; ··· 523 523 524 524 i2s2: i2s@12d70000 { 525 525 compatible = "samsung,exynos5420-i2s"; 526 - reg = <0x12D70000 0x100>; 526 + reg = <0x12d70000 0x100>; 527 527 dmas = <&pdma0 12>, 528 528 <&pdma0 11>; 529 529 dma-names = "tx", "rx"; ··· 612 612 613 613 hsi2c_8: i2c@12e00000 { 614 614 compatible = "samsung,exynos5250-hsi2c"; 615 - reg = <0x12E00000 0x1000>; 615 + reg = <0x12e00000 0x1000>; 616 616 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 617 617 #address-cells = <1>; 618 618 #size-cells = <0>; ··· 625 625 626 626 hsi2c_9: i2c@12e10000 { 627 627 compatible = "samsung,exynos5250-hsi2c"; 628 - reg = <0x12E10000 0x1000>; 628 + reg = <0x12e10000 0x1000>; 629 629 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 630 630 #address-cells = <1>; 631 631 #size-cells = <0>; ··· 638 638 639 639 hsi2c_10: i2c@12e20000 { 640 640 compatible = "samsung,exynos5250-hsi2c"; 641 - reg = <0x12E20000 0x1000>; 641 + reg = <0x12e20000 0x1000>; 642 642 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 643 643 #address-cells = <1>; 644 644 #size-cells = <0>; ··· 666 666 }; 667 667 668 668 hdmiphy: hdmi-phy@145d0000 { 669 - reg = <0x145D0000 0x20>; 669 + reg = <0x145d0000 0x20>; 670 670 }; 671 671 672 672 hdmicec: cec@101b0000 { 673 673 compatible = "samsung,s5p-cec"; 674 - reg = <0x101B0000 0x200>; 674 + reg = <0x101b0000 0x200>; 675 675 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 676 676 clocks = <&clock CLK_HDMI_CEC>; 677 677 clock-names = "hdmicec"; ··· 696 696 697 697 rotator: rotator@11c00000 { 698 698 compatible = "samsung,exynos5250-rotator"; 699 - reg = <0x11C00000 0x64>; 699 + reg = <0x11c00000 0x64>; 700 700 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 701 701 clocks = <&clock CLK_ROTATOR>; 702 702 clock-names = "rotator"; ··· 805 805 806 806 jpeg_0: jpeg@11f50000 { 807 807 compatible = "samsung,exynos5420-jpeg"; 808 - reg = <0x11F50000 0x1000>; 808 + reg = <0x11f50000 0x1000>; 809 809 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 810 810 clock-names = "jpeg"; 811 811 clocks = <&clock CLK_JPEG>; ··· 814 814 815 815 jpeg_1: jpeg@11f60000 { 816 816 compatible = "samsung,exynos5420-jpeg"; 817 - reg = <0x11F60000 0x1000>; 817 + reg = <0x11f60000 0x1000>; 818 818 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 819 819 clock-names = "jpeg"; 820 820 clocks = <&clock CLK_JPEG2>; ··· 879 879 880 880 sysmmu_g2dr: sysmmu@10a60000 { 881 881 compatible = "samsung,exynos-sysmmu"; 882 - reg = <0x10A60000 0x1000>; 882 + reg = <0x10a60000 0x1000>; 883 883 interrupt-parent = <&combiner>; 884 884 interrupts = <24 5>; 885 885 clock-names = "sysmmu", "master"; ··· 889 889 890 890 sysmmu_g2dw: sysmmu@10a70000 { 891 891 compatible = "samsung,exynos-sysmmu"; 892 - reg = <0x10A70000 0x1000>; 892 + reg = <0x10a70000 0x1000>; 893 893 interrupt-parent = <&combiner>; 894 894 interrupts = <22 2>; 895 895 clock-names = "sysmmu", "master"; ··· 910 910 911 911 sysmmu_gscl0: sysmmu@13e80000 { 912 912 compatible = "samsung,exynos-sysmmu"; 913 - reg = <0x13E80000 0x1000>; 913 + reg = <0x13e80000 0x1000>; 914 914 interrupt-parent = <&combiner>; 915 915 interrupts = <2 0>; 916 916 clock-names = "sysmmu", "master"; ··· 921 921 922 922 sysmmu_gscl1: sysmmu@13e90000 { 923 923 compatible = "samsung,exynos-sysmmu"; 924 - reg = <0x13E90000 0x1000>; 924 + reg = <0x13e90000 0x1000>; 925 925 interrupt-parent = <&combiner>; 926 926 interrupts = <2 2>; 927 927 clock-names = "sysmmu", "master"; ··· 953 953 954 954 sysmmu_scaler2r: sysmmu@128a0000 { 955 955 compatible = "samsung,exynos-sysmmu"; 956 - reg = <0x128A0000 0x1000>; 956 + reg = <0x128a0000 0x1000>; 957 957 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 958 958 clock-names = "sysmmu", "master"; 959 959 clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>; ··· 963 963 964 964 sysmmu_scaler0w: sysmmu@128c0000 { 965 965 compatible = "samsung,exynos-sysmmu"; 966 - reg = <0x128C0000 0x1000>; 966 + reg = <0x128c0000 0x1000>; 967 967 interrupt-parent = <&combiner>; 968 968 interrupts = <27 2>; 969 969 clock-names = "sysmmu", "master"; ··· 974 974 975 975 sysmmu_scaler1w: sysmmu@128d0000 { 976 976 compatible = "samsung,exynos-sysmmu"; 977 - reg = <0x128D0000 0x1000>; 977 + reg = <0x128d0000 0x1000>; 978 978 interrupt-parent = <&combiner>; 979 979 interrupts = <22 6>; 980 980 clock-names = "sysmmu", "master"; ··· 985 985 986 986 sysmmu_scaler2w: sysmmu@128e0000 { 987 987 compatible = "samsung,exynos-sysmmu"; 988 - reg = <0x128E0000 0x1000>; 988 + reg = <0x128e0000 0x1000>; 989 989 interrupt-parent = <&combiner>; 990 990 interrupts = <19 6>; 991 991 clock-names = "sysmmu", "master"; ··· 996 996 997 997 sysmmu_rotator: sysmmu@11d40000 { 998 998 compatible = "samsung,exynos-sysmmu"; 999 - reg = <0x11D40000 0x1000>; 999 + reg = <0x11d40000 0x1000>; 1000 1000 interrupt-parent = <&combiner>; 1001 1001 interrupts = <4 0>; 1002 1002 clock-names = "sysmmu", "master"; ··· 1006 1006 1007 1007 sysmmu_jpeg0: sysmmu@11f10000 { 1008 1008 compatible = "samsung,exynos-sysmmu"; 1009 - reg = <0x11F10000 0x1000>; 1009 + reg = <0x11f10000 0x1000>; 1010 1010 interrupt-parent = <&combiner>; 1011 1011 interrupts = <4 2>; 1012 1012 clock-names = "sysmmu", "master"; ··· 1016 1016 1017 1017 sysmmu_jpeg1: sysmmu@11f20000 { 1018 1018 compatible = "samsung,exynos-sysmmu"; 1019 - reg = <0x11F20000 0x1000>; 1019 + reg = <0x11f20000 0x1000>; 1020 1020 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 1021 1021 clock-names = "sysmmu", "master"; 1022 1022 clocks = <&clock CLK_SMMU_JPEG2>, <&clock CLK_JPEG2>;
+1 -1
arch/arm/boot/dts/exynos5422-odroid-core.dtsi
··· 16 16 / { 17 17 memory@40000000 { 18 18 device_type = "memory"; 19 - reg = <0x40000000 0x7EA00000>; 19 + reg = <0x40000000 0x7ea00000>; 20 20 }; 21 21 22 22 chosen {