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kernel
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linux
clk: mediatek: Add MT8195 imgsys clock support
Add MT8195 imgsys clock controllers which provide clock gate
control for image IP blocks.
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20210914021633.26377-13-chun-jie.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
authored by
Chun-Jie Chen
and committed by
Stephen Boyd
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drivers/clk/mediatek/Makefile
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drivers/clk/mediatek/Makefile
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obj-$(CONFIG_COMMON_CLK_MT8192_VENCSYS) += clk-mt8192-venc.o
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obj-$(CONFIG_COMMON_CLK_MT8195) += clk-mt8195-apmixedsys.o clk-mt8195-topckgen.o \
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clk-mt8195-peri_ao.o clk-mt8195-infra_ao.o \
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clk-mt8195-cam.o clk-mt8195-ccu.o
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clk-mt8195-cam.o clk-mt8195-ccu.o clk-mt8195-img.o
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obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516.o
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obj-$(CONFIG_COMMON_CLK_MT8516_AUDSYS) += clk-mt8516-aud.o
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drivers/clk/mediatek/clk-mt8195-img.c
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drivers/clk/mediatek/clk-mt8195-img.c
···
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// SPDX-License-Identifier: GPL-2.0-only
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//
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// Copyright (c) 2021 MediaTek Inc.
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// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
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#include "clk-gate.h"
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#include "clk-mtk.h"
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#include <dt-bindings/clock/mt8195-clk.h>
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#include <linux/clk-provider.h>
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#include <linux/platform_device.h>
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static const struct mtk_gate_regs img_cg_regs = {
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.set_ofs = 0x4,
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.clr_ofs = 0x8,
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.sta_ofs = 0x0,
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};
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#define GATE_IMG(_id, _name, _parent, _shift) \
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GATE_MTK(_id, _name, _parent, &img_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
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static const struct mtk_gate img_clks[] = {
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GATE_IMG(CLK_IMG_LARB9, "img_larb9", "top_img", 0),
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GATE_IMG(CLK_IMG_TRAW0, "img_traw0", "top_img", 1),
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GATE_IMG(CLK_IMG_TRAW1, "img_traw1", "top_img", 2),
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GATE_IMG(CLK_IMG_TRAW2, "img_traw2", "top_img", 3),
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GATE_IMG(CLK_IMG_TRAW3, "img_traw3", "top_img", 4),
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GATE_IMG(CLK_IMG_DIP0, "img_dip0", "top_img", 8),
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GATE_IMG(CLK_IMG_WPE0, "img_wpe0", "top_img", 9),
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GATE_IMG(CLK_IMG_IPE, "img_ipe", "top_img", 10),
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GATE_IMG(CLK_IMG_DIP1, "img_dip1", "top_img", 11),
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GATE_IMG(CLK_IMG_WPE1, "img_wpe1", "top_img", 12),
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GATE_IMG(CLK_IMG_GALS, "img_gals", "top_img", 31),
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};
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static const struct mtk_gate img1_dip_top_clks[] = {
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GATE_IMG(CLK_IMG1_DIP_TOP_LARB10, "img1_dip_top_larb10", "top_img", 0),
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GATE_IMG(CLK_IMG1_DIP_TOP_DIP_TOP, "img1_dip_top_dip_top", "top_img", 1),
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};
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static const struct mtk_gate img1_dip_nr_clks[] = {
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GATE_IMG(CLK_IMG1_DIP_NR_RESERVE, "img1_dip_nr_reserve", "top_img", 0),
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GATE_IMG(CLK_IMG1_DIP_NR_DIP_NR, "img1_dip_nr_dip_nr", "top_img", 1),
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};
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static const struct mtk_gate img1_wpe_clks[] = {
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GATE_IMG(CLK_IMG1_WPE_LARB11, "img1_wpe_larb11", "top_img", 0),
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GATE_IMG(CLK_IMG1_WPE_WPE, "img1_wpe_wpe", "top_img", 1),
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};
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static const struct mtk_clk_desc img_desc = {
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.clks = img_clks,
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.num_clks = ARRAY_SIZE(img_clks),
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};
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static const struct mtk_clk_desc img1_dip_top_desc = {
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.clks = img1_dip_top_clks,
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.num_clks = ARRAY_SIZE(img1_dip_top_clks),
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};
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static const struct mtk_clk_desc img1_dip_nr_desc = {
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.clks = img1_dip_nr_clks,
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.num_clks = ARRAY_SIZE(img1_dip_nr_clks),
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};
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static const struct mtk_clk_desc img1_wpe_desc = {
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.clks = img1_wpe_clks,
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.num_clks = ARRAY_SIZE(img1_wpe_clks),
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};
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static const struct of_device_id of_match_clk_mt8195_img[] = {
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{
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.compatible = "mediatek,mt8195-imgsys",
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.data = &img_desc,
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}, {
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.compatible = "mediatek,mt8195-imgsys1_dip_top",
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.data = &img1_dip_top_desc,
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}, {
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.compatible = "mediatek,mt8195-imgsys1_dip_nr",
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.data = &img1_dip_nr_desc,
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}, {
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.compatible = "mediatek,mt8195-imgsys1_wpe",
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.data = &img1_wpe_desc,
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}, {
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/* sentinel */
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}
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};
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static struct platform_driver clk_mt8195_img_drv = {
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.probe = mtk_clk_simple_probe,
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.driver = {
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.name = "clk-mt8195-img",
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.of_match_table = of_match_clk_mt8195_img,
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},
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};
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builtin_platform_driver(clk_mt8195_img_drv);