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dt-bindings: dma: Convert mtk-uart-apdma to DT schema
Convert the MediaTek UART APDMA Controller binding to DT schema.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Link: https://lore.kernel.org/r/20220217095242.13761-1-angelogioacchino.delregno@collabora.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
authored by
AngeloGioacchino Del Regno
and committed by
Vinod Koul
9c391ceb
417c7d0d
+122
-56
+122
Documentation/devicetree/bindings/dma/mediatek,uart-dma.yaml
+122
Documentation/devicetree/bindings/dma/mediatek,uart-dma.yaml
···
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/dma/mediatek,uart-dma.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MediaTek UART APDMA controller
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maintainers:
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- Long Cheng <long.cheng@mediatek.com>
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description: |
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The MediaTek UART APDMA controller provides DMA capabilities
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for the UART peripheral bus.
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allOf:
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- $ref: "dma-controller.yaml#"
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properties:
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compatible:
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oneOf:
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- items:
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- enum:
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- mediatek,mt2712-uart-dma
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- mediatek,mt8516-uart-dma
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- const: mediatek,mt6577-uart-dma
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- enum:
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- mediatek,mt6577-uart-dma
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reg:
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minItems: 1
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maxItems: 16
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interrupts:
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description: |
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TX, RX interrupt lines for each UART APDMA channel
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minItems: 1
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maxItems: 16
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clocks:
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description: Must contain one entry for the APDMA main clock
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maxItems: 1
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clock-names:
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const: apdma
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"#dma-cells":
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const: 1
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description: |
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The first cell specifies the UART APDMA channel number
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dma-requests:
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description: |
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Number of virtual channels of the UART APDMA controller
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maximum: 16
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mediatek,dma-33bits:
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type: boolean
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description: Enable 33-bits UART APDMA support
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required:
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- compatible
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- reg
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- interrupts
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additionalProperties: false
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if:
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not:
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required:
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- dma-requests
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then:
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properties:
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interrupts:
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maxItems: 8
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reg:
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maxItems: 8
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/mt2712-clk.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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apdma: dma-controller@11000400 {
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compatible = "mediatek,mt2712-uart-dma",
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"mediatek,mt6577-uart-dma";
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reg = <0 0x11000400 0 0x80>,
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<0 0x11000480 0 0x80>,
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<0 0x11000500 0 0x80>,
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<0 0x11000580 0 0x80>,
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<0 0x11000600 0 0x80>,
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<0 0x11000680 0 0x80>,
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<0 0x11000700 0 0x80>,
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<0 0x11000780 0 0x80>,
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<0 0x11000800 0 0x80>,
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<0 0x11000880 0 0x80>,
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<0 0x11000900 0 0x80>,
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<0 0x11000980 0 0x80>;
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interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 105 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 107 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 108 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 109 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 111 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 114 IRQ_TYPE_LEVEL_LOW>;
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dma-requests = <12>;
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clocks = <&pericfg CLK_PERI_AP_DMA>;
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clock-names = "apdma";
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mediatek,dma-33bits;
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#dma-cells = <1>;
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};
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};
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...
-56
Documentation/devicetree/bindings/dma/mtk-uart-apdma.txt
-56
Documentation/devicetree/bindings/dma/mtk-uart-apdma.txt
···
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* Mediatek UART APDMA Controller
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Required properties:
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- compatible should contain:
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* "mediatek,mt2712-uart-dma" for MT2712 compatible APDMA
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* "mediatek,mt6577-uart-dma" for MT6577 and all of the above
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* "mediatek,mt8516-uart-dma", "mediatek,mt6577" for MT8516 SoC
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-
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- reg: The base address of the APDMA register bank.
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-
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- interrupts: A single interrupt specifier.
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One interrupt per dma-requests, or 8 if no dma-requests property is present
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-
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- dma-requests: The number of DMA channels
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-
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- clocks : Must contain an entry for each entry in clock-names.
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See ../clocks/clock-bindings.txt for details.
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- clock-names: The APDMA clock for register accesses
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-
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- mediatek,dma-33bits: Present if the DMA requires support
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-
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Examples:
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apdma: dma-controller@11000400 {
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compatible = "mediatek,mt2712-uart-dma",
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"mediatek,mt6577-uart-dma";
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reg = <0 0x11000400 0 0x80>,
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<0 0x11000480 0 0x80>,
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<0 0x11000500 0 0x80>,
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<0 0x11000580 0 0x80>,
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<0 0x11000600 0 0x80>,
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<0 0x11000680 0 0x80>,
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<0 0x11000700 0 0x80>,
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<0 0x11000780 0 0x80>,
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<0 0x11000800 0 0x80>,
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<0 0x11000880 0 0x80>,
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<0 0x11000900 0 0x80>,
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<0 0x11000980 0 0x80>;
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interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 105 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 107 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 108 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 109 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 111 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 114 IRQ_TYPE_LEVEL_LOW>;
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dma-requests = <12>;
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clocks = <&pericfg CLK_PERI_AP_DMA>;
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clock-names = "apdma";
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mediatek,dma-33bits;
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#dma-cells = <1>;
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};