tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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dt-bindings: display/msm: expand to support MST

On a vast majority of Qualcomm chipsets DisplayPort controller can
support several MST streams (up to 4x). To support MST these chipsets
use up to 4 stream pixel clocks for the DisplayPort controller and
several extra register regions. Expand corresponding region and clock
bindings for these platforms and fix example schema files to follow
updated bindings.

Note: On chipsets that support MST, the number of streams supported
can vary between controllers. For example, SA8775P supports 4 MST
streams on mdss_dp0 but only 2 streams on mdss_dp1.

Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: Jessica Zhang <jessica.zhang@oss.qualcomm.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Patchwork: https://patchwork.freedesktop.org/patch/672585/
Link: https://lore.kernel.org/r/20250903-dp_mst_bindings-v8-7-7526f0311eaa@oss.qualcomm.com

authored by

Abhinav Kumar and committed by
Dmitry Baryshkov 9be5c479 0253f5ef

+150 -22
+99 -4
Documentation/devicetree/bindings/display/msm/dp-controller.yaml
··· 66 66 - description: link register block 67 67 - description: p0 register block 68 68 - description: p1 register block 69 + - description: p2 register block 70 + - description: p3 register block 71 + - description: mst2link register block 72 + - description: mst3link register block 69 73 70 74 interrupts: 71 75 maxItems: 1 72 76 73 77 clocks: 78 + minItems: 5 74 79 items: 75 80 - description: AHB clock to enable register access 76 81 - description: Display Port AUX clock 77 82 - description: Display Port Link clock 78 83 - description: Link interface clock between DP and PHY 79 - - description: Display Port Pixel clock 84 + - description: Display Port stream 0 Pixel clock 85 + - description: Display Port stream 1 Pixel clock 86 + - description: Display Port stream 2 Pixel clock 87 + - description: Display Port stream 3 Pixel clock 80 88 81 89 clock-names: 90 + minItems: 5 82 91 items: 83 92 - const: core_iface 84 93 - const: core_aux 85 94 - const: ctrl_link 86 95 - const: ctrl_link_iface 87 96 - const: stream_pixel 97 + - const: stream_1_pixel 98 + - const: stream_2_pixel 99 + - const: stream_3_pixel 88 100 89 101 phys: 90 102 maxItems: 1 ··· 178 166 allOf: 179 167 # AUX BUS does not exist on DP controllers 180 168 # Audio output also is present only on DP output 181 - # p1 regions is present on DP, but not on eDP 182 169 - if: 183 170 properties: 184 171 compatible: ··· 206 195 else: 207 196 properties: 208 197 aux-bus: false 209 - reg: 210 - minItems: 5 211 198 required: 212 199 - "#sound-dai-cells" 200 + 201 + - if: 202 + properties: 203 + compatible: 204 + contains: 205 + enum: 206 + # these platforms support SST only 207 + - qcom,sc7180-dp 208 + - qcom,sc7280-dp 209 + - qcom,sc7280-edp 210 + - qcom,sc8180x-edp 211 + - qcom,sc8280xp-edp 212 + then: 213 + properties: 214 + reg: 215 + minItems: 5 216 + maxItems: 5 217 + clocks: 218 + minItems: 5 219 + maxItems: 5 220 + clocks-names: 221 + minItems: 5 222 + maxItems: 5 223 + 224 + - if: 225 + properties: 226 + compatible: 227 + contains: 228 + enum: 229 + # these platforms support 2 streams MST on some interfaces, 230 + # others are SST only 231 + - qcom,sc8280xp-dp 232 + - qcom,x1e80100-dp 233 + then: 234 + properties: 235 + reg: 236 + minItems: 5 237 + maxItems: 5 238 + clocks: 239 + minItems: 5 240 + maxItems: 6 241 + clocks-names: 242 + minItems: 5 243 + maxItems: 6 244 + 245 + - if: 246 + properties: 247 + compatible: 248 + contains: 249 + # 2 streams MST 250 + enum: 251 + - qcom,sc8180x-dp 252 + - qcom,sdm845-dp 253 + - qcom,sm8350-dp 254 + - qcom,sm8650-dp 255 + then: 256 + properties: 257 + reg: 258 + minItems: 5 259 + maxItems: 5 260 + clocks: 261 + minItems: 6 262 + maxItems: 6 263 + clocks-names: 264 + minItems: 6 265 + maxItems: 6 266 + 267 + - if: 268 + properties: 269 + compatible: 270 + contains: 271 + enum: 272 + # these platforms support 4 stream MST on first DP, 273 + # 2 streams MST on the second one. 274 + - qcom,sa8775p-dp 275 + then: 276 + properties: 277 + reg: 278 + minItems: 9 279 + maxItems: 9 280 + clocks: 281 + minItems: 6 282 + maxItems: 8 283 + clocks-names: 284 + minItems: 6 285 + maxItems: 8 213 286 214 287 additionalProperties: false 215 288
+21 -5
Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml
··· 375 375 <0xaf54200 0x0c0>, 376 376 <0xaf55000 0x770>, 377 377 <0xaf56000 0x09c>, 378 - <0xaf57000 0x09c>; 378 + <0xaf57000 0x09c>, 379 + <0xaf58000 0x09c>, 380 + <0xaf59000 0x09c>, 381 + <0xaf5a000 0x23c>, 382 + <0xaf5b000 0x23c>; 379 383 380 384 interrupt-parent = <&mdss0>; 381 385 interrupts = <12>; ··· 388 384 <&dispcc_dptx0_aux_clk>, 389 385 <&dispcc_dptx0_link_clk>, 390 386 <&dispcc_dptx0_link_intf_clk>, 391 - <&dispcc_dptx0_pixel0_clk>; 387 + <&dispcc_dptx0_pixel0_clk>, 388 + <&dispcc_dptx0_pixel1_clk>, 389 + <&dispcc_dptx0_pixel2_clk>, 390 + <&dispcc_dptx0_pixel3_clk>; 392 391 clock-names = "core_iface", 393 392 "core_aux", 394 393 "ctrl_link", 395 394 "ctrl_link_iface", 396 - "stream_pixel"; 395 + "stream_pixel", 396 + "stream_1_pixel", 397 + "stream_2_pixel", 398 + "stream_3_pixel"; 397 399 398 400 assigned-clocks = <&dispcc_mdss_dptx0_link_clk_src>, 399 - <&dispcc_mdss_dptx0_pixel0_clk_src>; 400 - assigned-clock-parents = <&mdss0_dp0_phy 0>, <&mdss0_dp0_phy 1>; 401 + <&dispcc_mdss_dptx0_pixel0_clk_src>, 402 + <&dispcc_mdss_dptx0_pixel1_clk_src>, 403 + <&dispcc_mdss_dptx0_pixel2_clk_src>, 404 + <&dispcc_mdss_dptx0_pixel3_clk_src>; 405 + assigned-clock-parents = <&mdss0_dp0_phy 0>, 406 + <&mdss0_dp0_phy 1>, 407 + <&mdss0_dp0_phy 1>, 408 + <&mdss0_dp0_phy 1>; 401 409 402 410 phys = <&mdss0_dp0_phy>; 403 411 phy-names = "dp";
+7 -3
Documentation/devicetree/bindings/display/msm/qcom,sar2130p-mdss.yaml
··· 207 207 <&dispcc_disp_cc_mdss_dptx0_aux_clk>, 208 208 <&dispcc_disp_cc_mdss_dptx0_link_clk>, 209 209 <&dispcc_disp_cc_mdss_dptx0_link_intf_clk>, 210 - <&dispcc_disp_cc_mdss_dptx0_pixel0_clk>; 210 + <&dispcc_disp_cc_mdss_dptx0_pixel0_clk>, 211 + <&dispcc_disp_cc_mdss_dptx0_pixel1_clk>; 211 212 clock-names = "core_iface", 212 213 "core_aux", 213 214 "ctrl_link", 214 215 "ctrl_link_iface", 215 - "stream_pixel"; 216 + "stream_pixel", 217 + "stream_1_pixel"; 216 218 217 219 assigned-clocks = <&dispcc_disp_cc_mdss_dptx0_link_clk_src>, 218 - <&dispcc_disp_cc_mdss_dptx0_pixel0_clk_src>; 220 + <&dispcc_disp_cc_mdss_dptx0_pixel0_clk_src>, 221 + <&dispcc_disp_cc_mdss_dptx0_pixel1_clk_src>; 219 222 assigned-clock-parents = <&usb_dp_qmpphy_QMP_USB43DP_DP_LINK_CLK>, 223 + <&usb_dp_qmpphy_QMP_USB43DP_DP_VCO_DIV_CLK>, 220 224 <&usb_dp_qmpphy_QMP_USB43DP_DP_VCO_DIV_CLK>; 221 225 222 226 phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>;
+2 -1
Documentation/devicetree/bindings/display/msm/qcom,sc7280-mdss.yaml
··· 281 281 reg = <0xaea0000 0x200>, 282 282 <0xaea0200 0x200>, 283 283 <0xaea0400 0xc00>, 284 - <0xaea1000 0x400>; 284 + <0xaea1000 0x400>, 285 + <0xaea1400 0x400>; 285 286 286 287 interrupt-parent = <&mdss>; 287 288 interrupts = <14>;
+7 -3
Documentation/devicetree/bindings/display/msm/qcom,sm7150-mdss.yaml
··· 394 394 <&dispcc_mdss_dp_aux_clk>, 395 395 <&dispcc_mdss_dp_link_clk>, 396 396 <&dispcc_mdss_dp_link_intf_clk>, 397 - <&dispcc_mdss_dp_pixel_clk>; 397 + <&dispcc_mdss_dp_pixel_clk>, 398 + <&dispcc_mdss_dp_pixel1_clk>; 398 399 clock-names = "core_iface", 399 400 "core_aux", 400 401 "ctrl_link", 401 402 "ctrl_link_iface", 402 - "stream_pixel"; 403 + "stream_pixel", 404 + "stream_1_pixel"; 403 405 404 406 assigned-clocks = <&dispcc_mdss_dp_link_clk_src>, 405 - <&dispcc_mdss_dp_pixel_clk_src>; 407 + <&dispcc_mdss_dp_pixel_clk_src>, 408 + <&dispcc_mdss_dp_pixel1_clk_src>; 406 409 assigned-clock-parents = <&dp_phy 0>, 410 + <&dp_phy 1>, 407 411 <&dp_phy 1>; 408 412 409 413 operating-points-v2 = <&dp_opp_table>;
+7 -3
Documentation/devicetree/bindings/display/msm/qcom,sm8750-mdss.yaml
··· 401 401 <&disp_cc_mdss_dptx0_aux_clk>, 402 402 <&disp_cc_mdss_dptx0_link_clk>, 403 403 <&disp_cc_mdss_dptx0_link_intf_clk>, 404 - <&disp_cc_mdss_dptx0_pixel0_clk>; 404 + <&disp_cc_mdss_dptx0_pixel0_clk>, 405 + <&disp_cc_mdss_dptx0_pixel1_clk>; 405 406 clock-names = "core_iface", 406 407 "core_aux", 407 408 "ctrl_link", 408 409 "ctrl_link_iface", 409 - "stream_pixel"; 410 + "stream_pixel", 411 + "stream_1_pixel"; 410 412 411 413 assigned-clocks = <&disp_cc_mdss_dptx0_link_clk_src>, 412 - <&disp_cc_mdss_dptx0_pixel0_clk_src>; 414 + <&disp_cc_mdss_dptx0_pixel0_clk_src>, 415 + <&disp_cc_mdss_dptx0_pixel1_clk_src>; 413 416 assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, 417 + <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 414 418 <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 415 419 416 420 operating-points-v2 = <&dp_opp_table>;
+7 -3
Documentation/devicetree/bindings/display/msm/qcom,x1e80100-mdss.yaml
··· 183 183 <&dispcc_dptx0_aux_clk>, 184 184 <&dispcc_dptx0_link_clk>, 185 185 <&dispcc_dptx0_link_intf_clk>, 186 - <&dispcc_dptx0_pixel0_clk>; 186 + <&dispcc_dptx0_pixel0_clk>, 187 + <&dispcc_dptx0_pixel1_clk>; 187 188 clock-names = "core_iface", "core_aux", 188 189 "ctrl_link", 189 190 "ctrl_link_iface", 190 - "stream_pixel"; 191 + "stream_pixel", 192 + "stream_1_pixel"; 191 193 192 194 assigned-clocks = <&dispcc_mdss_dptx0_link_clk_src>, 193 - <&dispcc_mdss_dptx0_pixel0_clk_src>; 195 + <&dispcc_mdss_dptx0_pixel0_clk_src>, 196 + <&dispcc_mdss_dptx0_pixel1_clk_src>; 194 197 assigned-clock-parents = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>, 198 + <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 195 199 <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 196 200 197 201 operating-points-v2 = <&mdss_dp0_opp_table>;