tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

Merge tag 'renesas-clk-for-v6.9-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas

Pull more Renesas clk driver updates from Geert Uytterhoeven:

- Add Ethernet, SDHI, DMA, and HyperFLASH/QSPI (RPC-IF) clocks on
R-Car V4M
- Miscellaneous fixes and improvements

* tag 'renesas-clk-for-v6.9-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
clk: renesas: r8a779h0: Add RPC-IF clock
clk: renesas: r8a779h0: Add SYS-DMAC clocks
clk: renesas: r8a779h0: Add SDHI clock
clk: renesas: r8a779h0: Add EtherAVB clocks
clk: renesas: r9a07g04[34]: Fix typo for sel_shdi variable
clk: renesas: r9a07g04[34]: Use SEL_SDHI1_STS status configuration for SD1 mux
clk: renesas: r8a779f0: Correct PFC/GPIO parent clock
clk: renesas: r8a779g0: Correct PFC/GPIO parent clocks

Stephen Boyd 9bd5726f a24f93f1

+21 -12
+1 -1
drivers/clk/renesas/r8a779f0-cpg-mssr.c
··· 161 161 DEF_MOD("cmt1", 911, R8A779F0_CLK_R), 162 162 DEF_MOD("cmt2", 912, R8A779F0_CLK_R), 163 163 DEF_MOD("cmt3", 913, R8A779F0_CLK_R), 164 - DEF_MOD("pfc0", 915, R8A779F0_CLK_CL16M), 164 + DEF_MOD("pfc0", 915, R8A779F0_CLK_CPEX), 165 165 DEF_MOD("tsc", 919, R8A779F0_CLK_CL16M), 166 166 DEF_MOD("rswitch2", 1505, R8A779F0_CLK_RSW2), 167 167 DEF_MOD("ether-serdes", 1506, R8A779F0_CLK_S0D2_HSC),
+6 -5
drivers/clk/renesas/r8a779g0-cpg-mssr.c
··· 22 22 23 23 enum clk_ids { 24 24 /* Core Clock Outputs exported to DT */ 25 - LAST_DT_CORE_CLK = R8A779G0_CLK_R, 25 + LAST_DT_CORE_CLK = R8A779G0_CLK_CP, 26 26 27 27 /* External Input Clocks */ 28 28 CLK_EXTAL, ··· 141 141 DEF_FIXED("svd2_vip", R8A779G0_CLK_SVD2_VIP, CLK_SV_VIP, 2, 1), 142 142 DEF_FIXED("cbfusa", R8A779G0_CLK_CBFUSA, CLK_EXTAL, 2, 1), 143 143 DEF_FIXED("cpex", R8A779G0_CLK_CPEX, CLK_EXTAL, 2, 1), 144 + DEF_FIXED("cp", R8A779G0_CLK_CP, CLK_EXTAL, 2, 1), 144 145 DEF_FIXED("viobus", R8A779G0_CLK_VIOBUS, CLK_VIO, 1, 1), 145 146 DEF_FIXED("viobusd2", R8A779G0_CLK_VIOBUSD2, CLK_VIO, 2, 1), 146 147 DEF_FIXED("vcbus", R8A779G0_CLK_VCBUS, CLK_VC, 1, 1), ··· 233 232 DEF_MOD("cmt1", 911, R8A779G0_CLK_R), 234 233 DEF_MOD("cmt2", 912, R8A779G0_CLK_R), 235 234 DEF_MOD("cmt3", 913, R8A779G0_CLK_R), 236 - DEF_MOD("pfc0", 915, R8A779G0_CLK_CL16M), 237 - DEF_MOD("pfc1", 916, R8A779G0_CLK_CL16M), 238 - DEF_MOD("pfc2", 917, R8A779G0_CLK_CL16M), 239 - DEF_MOD("pfc3", 918, R8A779G0_CLK_CL16M), 235 + DEF_MOD("pfc0", 915, R8A779G0_CLK_CP), 236 + DEF_MOD("pfc1", 916, R8A779G0_CLK_CP), 237 + DEF_MOD("pfc2", 917, R8A779G0_CLK_CP), 238 + DEF_MOD("pfc3", 918, R8A779G0_CLK_CP), 240 239 DEF_MOD("tsc", 919, R8A779G0_CLK_CL16M), 241 240 DEF_MOD("tsn", 2723, R8A779G0_CLK_S0D4_HSC), 242 241 DEF_MOD("ssiu", 2926, R8A779G0_CLK_S0D6_PER),
+7
drivers/clk/renesas/r8a779h0-cpg-mssr.c
··· 173 173 }; 174 174 175 175 static const struct mssr_mod_clk r8a779h0_mod_clks[] = { 176 + DEF_MOD("avb0:rgmii0", 211, R8A779H0_CLK_S0D8_HSC), 177 + DEF_MOD("avb1:rgmii1", 212, R8A779H0_CLK_S0D8_HSC), 178 + DEF_MOD("avb2:rgmii2", 213, R8A779H0_CLK_S0D8_HSC), 176 179 DEF_MOD("hscif0", 514, R8A779H0_CLK_SASYNCPERD1), 177 180 DEF_MOD("hscif1", 515, R8A779H0_CLK_SASYNCPERD1), 178 181 DEF_MOD("hscif2", 516, R8A779H0_CLK_SASYNCPERD1), ··· 184 181 DEF_MOD("i2c1", 519, R8A779H0_CLK_S0D6_PER), 185 182 DEF_MOD("i2c2", 520, R8A779H0_CLK_S0D6_PER), 186 183 DEF_MOD("i2c3", 521, R8A779H0_CLK_S0D6_PER), 184 + DEF_MOD("rpc-if", 629, R8A779H0_CLK_RPCD2), 185 + DEF_MOD("sdhi0", 706, R8A779H0_CLK_SD0), 186 + DEF_MOD("sydm1", 709, R8A779H0_CLK_S0D6_PER), 187 + DEF_MOD("sydm2", 710, R8A779H0_CLK_S0D6_PER), 187 188 DEF_MOD("wdt1:wdt0", 907, R8A779H0_CLK_R), 188 189 DEF_MOD("pfc0", 915, R8A779H0_CLK_CP), 189 190 DEF_MOD("pfc1", 916, R8A779H0_CLK_CP),
+3 -3
drivers/clk/renesas/r9a07g043-cpg.c
··· 88 88 /* Mux clock tables */ 89 89 static const char * const sel_pll3_3[] = { ".pll3_533", ".pll3_400" }; 90 90 static const char * const sel_pll6_2[] = { ".pll6_250", ".pll5_250" }; 91 - static const char * const sel_shdi[] = { ".clk_533", ".clk_400", ".clk_266" }; 91 + static const char * const sel_sdhi[] = { ".clk_533", ".clk_400", ".clk_266" }; 92 92 93 93 static const u32 mtable_sdhi[] = { 1, 2, 3 }; 94 94 ··· 137 137 DEF_MUX("HP", R9A07G043_CLK_HP, SEL_PLL6_2, sel_pll6_2), 138 138 DEF_FIXED("SPI0", R9A07G043_CLK_SPI0, CLK_DIV_PLL3_C, 1, 2), 139 139 DEF_FIXED("SPI1", R9A07G043_CLK_SPI1, CLK_DIV_PLL3_C, 1, 4), 140 - DEF_SD_MUX("SD0", R9A07G043_CLK_SD0, SEL_SDHI0, SEL_SDHI0_STS, sel_shdi, 140 + DEF_SD_MUX("SD0", R9A07G043_CLK_SD0, SEL_SDHI0, SEL_SDHI0_STS, sel_sdhi, 141 141 mtable_sdhi, 0, rzg2l_cpg_sd_clk_mux_notifier), 142 - DEF_SD_MUX("SD1", R9A07G043_CLK_SD1, SEL_SDHI1, SEL_SDHI0_STS, sel_shdi, 142 + DEF_SD_MUX("SD1", R9A07G043_CLK_SD1, SEL_SDHI1, SEL_SDHI1_STS, sel_sdhi, 143 143 mtable_sdhi, 0, rzg2l_cpg_sd_clk_mux_notifier), 144 144 DEF_FIXED("SD0_DIV4", CLK_SD0_DIV4, R9A07G043_CLK_SD0, 1, 4), 145 145 DEF_FIXED("SD1_DIV4", CLK_SD1_DIV4, R9A07G043_CLK_SD1, 1, 4),
+3 -3
drivers/clk/renesas/r9a07g044-cpg.c
··· 106 106 static const char * const sel_pll3_3[] = { ".pll3_533", ".pll3_400" }; 107 107 static const char * const sel_pll5_4[] = { ".pll5_foutpostdiv", ".pll5_fout1ph0" }; 108 108 static const char * const sel_pll6_2[] = { ".pll6_250", ".pll5_250" }; 109 - static const char * const sel_shdi[] = { ".clk_533", ".clk_400", ".clk_266" }; 109 + static const char * const sel_sdhi[] = { ".clk_533", ".clk_400", ".clk_266" }; 110 110 static const char * const sel_gpu2[] = { ".pll6", ".pll3_div2_2" }; 111 111 112 112 static const u32 mtable_sdhi[] = { 1, 2, 3 }; ··· 176 176 DEF_MUX("HP", R9A07G044_CLK_HP, SEL_PLL6_2, sel_pll6_2), 177 177 DEF_FIXED("SPI0", R9A07G044_CLK_SPI0, CLK_DIV_PLL3_C, 1, 2), 178 178 DEF_FIXED("SPI1", R9A07G044_CLK_SPI1, CLK_DIV_PLL3_C, 1, 4), 179 - DEF_SD_MUX("SD0", R9A07G044_CLK_SD0, SEL_SDHI0, SEL_SDHI0_STS, sel_shdi, 179 + DEF_SD_MUX("SD0", R9A07G044_CLK_SD0, SEL_SDHI0, SEL_SDHI0_STS, sel_sdhi, 180 180 mtable_sdhi, 0, rzg2l_cpg_sd_clk_mux_notifier), 181 - DEF_SD_MUX("SD1", R9A07G044_CLK_SD1, SEL_SDHI1, SEL_SDHI0_STS, sel_shdi, 181 + DEF_SD_MUX("SD1", R9A07G044_CLK_SD1, SEL_SDHI1, SEL_SDHI1_STS, sel_sdhi, 182 182 mtable_sdhi, 0, rzg2l_cpg_sd_clk_mux_notifier), 183 183 DEF_FIXED("SD0_DIV4", CLK_SD0_DIV4, R9A07G044_CLK_SD0, 1, 4), 184 184 DEF_FIXED("SD1_DIV4", CLK_SD1_DIV4, R9A07G044_CLK_SD1, 1, 4),
+1
include/dt-bindings/clock/r8a779g0-cpg-mssr.h
··· 86 86 #define R8A779G0_CLK_CPEX 74 87 87 #define R8A779G0_CLK_CBFUSA 75 88 88 #define R8A779G0_CLK_R 76 89 + #define R8A779G0_CLK_CP 77 89 90 90 91 #endif /* __DT_BINDINGS_CLOCK_R8A779G0_CPG_MSSR_H__ */