tjh.dev / kernel
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kernel os linux
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dmaengine: sprd: Add interrupt support for 2-stage transfer

For 2-stage transfer, some users like Audio still need transaction interrupt
to notify when the 2-stage transfer is completed. Thus we should enable
2-stage transfer interrupt to support this feature.

Signed-off-by: Baolin Wang <baolin.wang@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Baolin Wang and committed by
Vinod Koul 9bb9fe0c c434e377

+21 -1
+21 -1
drivers/dma/sprd-dma.c
··· 62 62 /* SPRD_DMA_GLB_2STAGE_GRP register definition */ 63 63 #define SPRD_DMA_GLB_2STAGE_EN BIT(24) 64 64 #define SPRD_DMA_GLB_CHN_INT_MASK GENMASK(23, 20) 65 + #define SPRD_DMA_GLB_DEST_INT BIT(22) 66 + #define SPRD_DMA_GLB_SRC_INT BIT(20) 65 67 #define SPRD_DMA_GLB_LIST_DONE_TRG BIT(19) 66 68 #define SPRD_DMA_GLB_TRANS_DONE_TRG BIT(18) 67 69 #define SPRD_DMA_GLB_BLOCK_DONE_TRG BIT(17) ··· 137 135 /* define DMA channel mode & trigger mode mask */ 138 136 #define SPRD_DMA_CHN_MODE_MASK GENMASK(7, 0) 139 137 #define SPRD_DMA_TRG_MODE_MASK GENMASK(7, 0) 138 + #define SPRD_DMA_INT_TYPE_MASK GENMASK(7, 0) 140 139 141 140 /* define the DMA transfer step type */ 142 141 #define SPRD_DMA_NONE_STEP 0 ··· 193 190 u32 dev_id; 194 191 enum sprd_dma_chn_mode chn_mode; 195 192 enum sprd_dma_trg_mode trg_mode; 193 + enum sprd_dma_int_type int_type; 196 194 struct sprd_dma_desc *cur_desc; 197 195 }; 198 196 ··· 433 429 val = chn & SPRD_DMA_GLB_SRC_CHN_MASK; 434 430 val |= BIT(schan->trg_mode - 1) << SPRD_DMA_GLB_TRG_OFFSET; 435 431 val |= SPRD_DMA_GLB_2STAGE_EN; 432 + if (schan->int_type != SPRD_DMA_NO_INT) 433 + val |= SPRD_DMA_GLB_SRC_INT; 434 + 436 435 sprd_dma_glb_update(sdev, SPRD_DMA_GLB_2STAGE_GRP1, val, val); 437 436 break; 438 437 ··· 443 436 val = chn & SPRD_DMA_GLB_SRC_CHN_MASK; 444 437 val |= BIT(schan->trg_mode - 1) << SPRD_DMA_GLB_TRG_OFFSET; 445 438 val |= SPRD_DMA_GLB_2STAGE_EN; 439 + if (schan->int_type != SPRD_DMA_NO_INT) 440 + val |= SPRD_DMA_GLB_SRC_INT; 441 + 446 442 sprd_dma_glb_update(sdev, SPRD_DMA_GLB_2STAGE_GRP2, val, val); 447 443 break; 448 444 ··· 453 443 val = (chn << SPRD_DMA_GLB_DEST_CHN_OFFSET) & 454 444 SPRD_DMA_GLB_DEST_CHN_MASK; 455 445 val |= SPRD_DMA_GLB_2STAGE_EN; 446 + if (schan->int_type != SPRD_DMA_NO_INT) 447 + val |= SPRD_DMA_GLB_DEST_INT; 448 + 456 449 sprd_dma_glb_update(sdev, SPRD_DMA_GLB_2STAGE_GRP1, val, val); 457 450 break; 458 451 ··· 463 450 val = (chn << SPRD_DMA_GLB_DEST_CHN_OFFSET) & 464 451 SPRD_DMA_GLB_DEST_CHN_MASK; 465 452 val |= SPRD_DMA_GLB_2STAGE_EN; 453 + if (schan->int_type != SPRD_DMA_NO_INT) 454 + val |= SPRD_DMA_GLB_DEST_INT; 455 + 466 456 sprd_dma_glb_update(sdev, SPRD_DMA_GLB_2STAGE_GRP2, val, val); 467 457 break; 468 458 ··· 927 911 schan->linklist.virt_addr = 0; 928 912 } 929 913 930 - /* Set channel mode and trigger mode for 2-stage transfer */ 914 + /* 915 + * Set channel mode, interrupt mode and trigger mode for 2-stage 916 + * transfer. 917 + */ 931 918 schan->chn_mode = 932 919 (flags >> SPRD_DMA_CHN_MODE_SHIFT) & SPRD_DMA_CHN_MODE_MASK; 933 920 schan->trg_mode = 934 921 (flags >> SPRD_DMA_TRG_MODE_SHIFT) & SPRD_DMA_TRG_MODE_MASK; 922 + schan->int_type = flags & SPRD_DMA_INT_TYPE_MASK; 935 923 936 924 sdesc = kzalloc(sizeof(*sdesc), GFP_NOWAIT); 937 925 if (!sdesc)