Merge tag 'riscv-for-linus-5.19-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

Pull RISC-V fixes from Palmer Dabbelt:

- A fix to avoid printing a warning when modules do not exercise any
errata-dependent behavior and the SiFive errata are enabled.

- A fix to the Microchip PFSOC to attach the L2 cache to the CPU nodes.

* tag 'riscv-for-linus-5.19-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
riscv: don't warn for sifive erratas in modules
riscv: dts: microchip: hook up the mpfs' l2cache

Linus Torvalds 3 years ago 9b59ec8d a8ebfcd3

+6 -1

2 changed files

expand all

arch

riscv

boot

dts

microchip

mpfs.dtsi

errata

sifive

errata.c

arch/riscv/boot/dts/microchip/mpfs.dtsi

··· 50 50 riscv,isa = "rv64imafdc"; 51 51 clocks = <&clkcfg CLK_CPU>; 52 52 tlb-split; 53 + next-level-cache = <&cctrllr>; 53 54 status = "okay"; 54 55 55 56 cpu1_intc: interrupt-controller { ··· 78 77 riscv,isa = "rv64imafdc"; 79 78 clocks = <&clkcfg CLK_CPU>; 80 79 tlb-split; 80 + next-level-cache = <&cctrllr>; 81 81 status = "okay"; 82 82 83 83 cpu2_intc: interrupt-controller { ··· 106 104 riscv,isa = "rv64imafdc"; 107 105 clocks = <&clkcfg CLK_CPU>; 108 106 tlb-split; 107 + next-level-cache = <&cctrllr>; 109 108 status = "okay"; 110 109 111 110 cpu3_intc: interrupt-controller { ··· 134 131 riscv,isa = "rv64imafdc"; 135 132 clocks = <&clkcfg CLK_CPU>; 136 133 tlb-split; 134 + next-level-cache = <&cctrllr>; 137 135 status = "okay"; 138 136 cpu4_intc: interrupt-controller { 139 137 #interrupt-cells = <1>;

+2 -1

arch/riscv/errata/sifive/errata.c

··· 111 111 cpu_apply_errata |= tmp; 112 112 } 113 113 } 114 - if (cpu_apply_errata != cpu_req_errata) 114 + if (stage != RISCV_ALTERNATIVES_MODULE && 115 + cpu_apply_errata != cpu_req_errata) 115 116 warn_miss_errata(cpu_req_errata - cpu_apply_errata); 116 117 }