tjh.dev / kernel
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pinctrl: ingenic: Fix JZ4760 support

- JZ4760 and JZ4760B have a similar register layout as the JZ4740, and
don't use the new register layout, which was introduced with the
JZ4770 SoC and not the JZ4760 or JZ4760B SoCs.

- The JZ4740 code path only expected two function modes to be
configurable for each pin, and wouldn't work with more than two. Fix
it for the JZ4760, which has four configurable function modes.

Fixes: 0257595a5cf4 ("pinctrl: Ingenic: Add pinctrl driver for JZ4760 and JZ4760B.")
Cc: <stable@vger.kernel.org> # 5.3
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Link: https://lore.kernel.org/r/20201211232810.261565-1-paul@crapouillou.net
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

authored by

Paul Cercueil and committed by
Linus Walleij 9a85c09a 5c8fe583

+13 -13
+13 -13
drivers/pinctrl/pinctrl-ingenic.c
··· 1688 1688 static void ingenic_gpio_set_value(struct ingenic_gpio_chip *jzgc, 1689 1689 u8 offset, int value) 1690 1690 { 1691 - if (jzgc->jzpc->info->version >= ID_JZ4760) 1691 + if (jzgc->jzpc->info->version >= ID_JZ4770) 1692 1692 ingenic_gpio_set_bit(jzgc, JZ4760_GPIO_PAT0, offset, !!value); 1693 1693 else 1694 1694 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_DATA, offset, !!value); ··· 1718 1718 break; 1719 1719 } 1720 1720 1721 - if (jzgc->jzpc->info->version >= ID_JZ4760) { 1721 + if (jzgc->jzpc->info->version >= ID_JZ4770) { 1722 1722 reg1 = JZ4760_GPIO_PAT1; 1723 1723 reg2 = JZ4760_GPIO_PAT0; 1724 1724 } else { ··· 1758 1758 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 1759 1759 int irq = irqd->hwirq; 1760 1760 1761 - if (jzgc->jzpc->info->version >= ID_JZ4760) 1761 + if (jzgc->jzpc->info->version >= ID_JZ4770) 1762 1762 ingenic_gpio_set_bit(jzgc, JZ4760_GPIO_INT, irq, true); 1763 1763 else 1764 1764 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, true); ··· 1774 1774 1775 1775 ingenic_gpio_irq_mask(irqd); 1776 1776 1777 - if (jzgc->jzpc->info->version >= ID_JZ4760) 1777 + if (jzgc->jzpc->info->version >= ID_JZ4770) 1778 1778 ingenic_gpio_set_bit(jzgc, JZ4760_GPIO_INT, irq, false); 1779 1779 else 1780 1780 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, false); ··· 1799 1799 irq_set_type(jzgc, irq, IRQ_TYPE_LEVEL_HIGH); 1800 1800 } 1801 1801 1802 - if (jzgc->jzpc->info->version >= ID_JZ4760) 1802 + if (jzgc->jzpc->info->version >= ID_JZ4770) 1803 1803 ingenic_gpio_set_bit(jzgc, JZ4760_GPIO_FLAG, irq, false); 1804 1804 else 1805 1805 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_DATA, irq, true); ··· 1856 1856 1857 1857 chained_irq_enter(irq_chip, desc); 1858 1858 1859 - if (jzgc->jzpc->info->version >= ID_JZ4760) 1859 + if (jzgc->jzpc->info->version >= ID_JZ4770) 1860 1860 flag = ingenic_gpio_read_reg(jzgc, JZ4760_GPIO_FLAG); 1861 1861 else 1862 1862 flag = ingenic_gpio_read_reg(jzgc, JZ4740_GPIO_FLAG); ··· 1938 1938 struct ingenic_pinctrl *jzpc = jzgc->jzpc; 1939 1939 unsigned int pin = gc->base + offset; 1940 1940 1941 - if (jzpc->info->version >= ID_JZ4760) { 1941 + if (jzpc->info->version >= ID_JZ4770) { 1942 1942 if (ingenic_get_pin_config(jzpc, pin, JZ4760_GPIO_INT) || 1943 1943 ingenic_get_pin_config(jzpc, pin, JZ4760_GPIO_PAT1)) 1944 1944 return GPIO_LINE_DIRECTION_IN; ··· 1996 1996 ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_PAT1, func & 0x2); 1997 1997 ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_PAT0, func & 0x1); 1998 1998 ingenic_shadow_config_pin_load(jzpc, pin); 1999 - } else if (jzpc->info->version >= ID_JZ4760) { 1999 + } else if (jzpc->info->version >= ID_JZ4770) { 2000 2000 ingenic_config_pin(jzpc, pin, JZ4760_GPIO_INT, false); 2001 2001 ingenic_config_pin(jzpc, pin, GPIO_MSK, false); 2002 2002 ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PAT1, func & 0x2); ··· 2004 2004 } else { 2005 2005 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_FUNC, true); 2006 2006 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_TRIG, func & 0x2); 2007 - ingenic_config_pin(jzpc, pin, JZ4740_GPIO_SELECT, func > 0); 2007 + ingenic_config_pin(jzpc, pin, JZ4740_GPIO_SELECT, func & 0x1); 2008 2008 } 2009 2009 2010 2010 return 0; ··· 2061 2061 ingenic_shadow_config_pin(jzpc, pin, GPIO_MSK, true); 2062 2062 ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_PAT1, input); 2063 2063 ingenic_shadow_config_pin_load(jzpc, pin); 2064 - } else if (jzpc->info->version >= ID_JZ4760) { 2064 + } else if (jzpc->info->version >= ID_JZ4770) { 2065 2065 ingenic_config_pin(jzpc, pin, JZ4760_GPIO_INT, false); 2066 2066 ingenic_config_pin(jzpc, pin, GPIO_MSK, true); 2067 2067 ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PAT1, input); ··· 2091 2091 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 2092 2092 bool pull; 2093 2093 2094 - if (jzpc->info->version >= ID_JZ4760) 2094 + if (jzpc->info->version >= ID_JZ4770) 2095 2095 pull = !ingenic_get_pin_config(jzpc, pin, JZ4760_GPIO_PEN); 2096 2096 else 2097 2097 pull = !ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_PULL_DIS); ··· 2141 2141 REG_SET(X1830_GPIO_PEH), bias << idxh); 2142 2142 } 2143 2143 2144 - } else if (jzpc->info->version >= ID_JZ4760) { 2144 + } else if (jzpc->info->version >= ID_JZ4770) { 2145 2145 ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PEN, !bias); 2146 2146 } else { 2147 2147 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_PULL_DIS, !bias); ··· 2151 2151 static void ingenic_set_output_level(struct ingenic_pinctrl *jzpc, 2152 2152 unsigned int pin, bool high) 2153 2153 { 2154 - if (jzpc->info->version >= ID_JZ4760) 2154 + if (jzpc->info->version >= ID_JZ4770) 2155 2155 ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PAT0, high); 2156 2156 else 2157 2157 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_DATA, high);