ARM: dts: at91: sam9x60: Add missing flexcom definitions

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

Added the missing flexcom functions for all the flexcom nodes.

Signed-off-by: Manikandan Muralidharan <manikandan.m@microchip.com>
[durai.manickamkr@microchip.com: added missing UART compatibles]
Signed-off-by: Durai Manickam KR <durai.manickamkr@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20230207110651.197268-7-durai.manickamkr@microchip.com

authored by

Manikandan Muralidharan and committed by

Claudiu Beznea 3 years ago 99c80833 4be5375b

+545

1 changed file

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arch

arm

boot

dts

sam9x60.dtsi

+545

arch/arm/boot/dts/sam9x60.dtsi

··· 171 171 ranges = <0x0 0xf0000000 0x800>; 172 172 status = "disabled"; 173 173 174 + uart4: serial@200 { 175 + compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; 176 + reg = <0x200 0x200>; 177 + interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>; 178 + dmas = <&dma0 179 + (AT91_XDMAC_DT_MEM_IF(0) | 180 + AT91_XDMAC_DT_PER_IF(1) | 181 + AT91_XDMAC_DT_PERID(8))>, 182 + <&dma0 183 + (AT91_XDMAC_DT_MEM_IF(0) | 184 + AT91_XDMAC_DT_PER_IF(1) | 185 + AT91_XDMAC_DT_PERID(9))>; 186 + dma-names = "tx", "rx"; 187 + clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; 188 + clock-names = "usart"; 189 + atmel,use-dma-rx; 190 + atmel,use-dma-tx; 191 + atmel,fifo-size = <16>; 192 + status = "disabled"; 193 + }; 194 + 174 195 spi4: spi@400 { 175 196 compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi"; 176 197 reg = <0x400 0x200>; 177 198 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>; 178 199 clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; 179 200 clock-names = "spi_clk"; 201 + dmas = <&dma0 202 + (AT91_XDMAC_DT_MEM_IF(0) | 203 + AT91_XDMAC_DT_PER_IF(1) | 204 + AT91_XDMAC_DT_PERID(8))>, 205 + <&dma0 206 + (AT91_XDMAC_DT_MEM_IF(0) | 207 + AT91_XDMAC_DT_PER_IF(1) | 208 + AT91_XDMAC_DT_PERID(9))>; 209 + dma-names = "tx", "rx"; 210 + atmel,fifo-size = <16>; 211 + status = "disabled"; 212 + }; 213 + 214 + i2c4: i2c@600 { 215 + compatible = "microchip,sam9x60-i2c"; 216 + reg = <0x600 0x200>; 217 + interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>; 218 + clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; 180 219 dmas = <&dma0 181 220 (AT91_XDMAC_DT_MEM_IF(0) | 182 221 AT91_XDMAC_DT_PER_IF(1) | ··· 257 218 clock-names = "usart"; 258 219 atmel,use-dma-rx; 259 220 atmel,use-dma-tx; 221 + atmel,fifo-size = <16>; 222 + status = "disabled"; 223 + }; 224 + 225 + spi5: spi@400 { 226 + compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi"; 227 + reg = <0x400 0x200>; 228 + interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>; 229 + clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; 230 + clock-names = "spi_clk"; 231 + dmas = <&dma0 232 + (AT91_XDMAC_DT_MEM_IF(0) | 233 + AT91_XDMAC_DT_PER_IF(1) | 234 + AT91_XDMAC_DT_PERID(10))>, 235 + <&dma0 236 + (AT91_XDMAC_DT_MEM_IF(0) | 237 + AT91_XDMAC_DT_PER_IF(1) | 238 + AT91_XDMAC_DT_PERID(11))>; 239 + dma-names = "tx", "rx"; 240 + atmel,fifo-size = <16>; 241 + status = "disabled"; 242 + }; 243 + 244 + i2c5: i2c@600 { 245 + compatible = "microchip,sam9x60-i2c"; 246 + reg = <0x600 0x200>; 247 + interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>; 248 + clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; 249 + dmas = <&dma0 250 + (AT91_XDMAC_DT_MEM_IF(0) | 251 + AT91_XDMAC_DT_PER_IF(1) | 252 + AT91_XDMAC_DT_PERID(10))>, 253 + <&dma0 254 + (AT91_XDMAC_DT_MEM_IF(0) | 255 + AT91_XDMAC_DT_PER_IF(1) | 256 + AT91_XDMAC_DT_PERID(11))>; 257 + dma-names = "tx", "rx"; 260 258 atmel,fifo-size = <16>; 261 259 status = "disabled"; 262 260 }; ··· 368 292 #size-cells = <1>; 369 293 ranges = <0x0 0xf0020000 0x800>; 370 294 status = "disabled"; 295 + 296 + uart11: serial@200 { 297 + compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; 298 + reg = <0x200 0x200>; 299 + interrupts = <32 IRQ_TYPE_LEVEL_HIGH 7>; 300 + dmas = <&dma0 301 + (AT91_XDMAC_DT_MEM_IF(0) | 302 + AT91_XDMAC_DT_PER_IF(1) | 303 + AT91_XDMAC_DT_PERID(22))>, 304 + <&dma0 305 + (AT91_XDMAC_DT_MEM_IF(0) | 306 + AT91_XDMAC_DT_PER_IF(1) | 307 + AT91_XDMAC_DT_PERID(23))>; 308 + dma-names = "tx", "rx"; 309 + clocks = <&pmc PMC_TYPE_PERIPHERAL 32>; 310 + clock-names = "usart"; 311 + atmel,use-dma-rx; 312 + atmel,use-dma-tx; 313 + atmel,fifo-size = <16>; 314 + status = "disabled"; 315 + }; 316 + 317 + i2c11: i2c@600 { 318 + compatible = "microchip,sam9x60-i2c"; 319 + reg = <0x600 0x200>; 320 + interrupts = <32 IRQ_TYPE_LEVEL_HIGH 7>; 321 + clocks = <&pmc PMC_TYPE_PERIPHERAL 32>; 322 + dmas = <&dma0 323 + (AT91_XDMAC_DT_MEM_IF(0) | 324 + AT91_XDMAC_DT_PER_IF(1) | 325 + AT91_XDMAC_DT_PERID(22))>, 326 + <&dma0 327 + (AT91_XDMAC_DT_MEM_IF(0) | 328 + AT91_XDMAC_DT_PER_IF(1) | 329 + AT91_XDMAC_DT_PERID(23))>; 330 + dma-names = "tx", "rx"; 331 + atmel,fifo-size = <16>; 332 + status = "disabled"; 333 + }; 371 334 }; 372 335 373 336 flx12: flexcom@f0024000 { ··· 417 302 #size-cells = <1>; 418 303 ranges = <0x0 0xf0024000 0x800>; 419 304 status = "disabled"; 305 + 306 + uart12: serial@200 { 307 + compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; 308 + reg = <0x200 0x200>; 309 + interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>; 310 + dmas = <&dma0 311 + (AT91_XDMAC_DT_MEM_IF(0) | 312 + AT91_XDMAC_DT_PER_IF(1) | 313 + AT91_XDMAC_DT_PERID(24))>, 314 + <&dma0 315 + (AT91_XDMAC_DT_MEM_IF(0) | 316 + AT91_XDMAC_DT_PER_IF(1) | 317 + AT91_XDMAC_DT_PERID(25))>; 318 + dma-names = "tx", "rx"; 319 + clocks = <&pmc PMC_TYPE_PERIPHERAL 33>; 320 + clock-names = "usart"; 321 + atmel,use-dma-rx; 322 + atmel,use-dma-tx; 323 + atmel,fifo-size = <16>; 324 + status = "disabled"; 325 + }; 326 + 327 + i2c12: i2c@600 { 328 + compatible = "microchip,sam9x60-i2c"; 329 + reg = <0x600 0x200>; 330 + interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>; 331 + clocks = <&pmc PMC_TYPE_PERIPHERAL 33>; 332 + dmas = <&dma0 333 + (AT91_XDMAC_DT_MEM_IF(0) | 334 + AT91_XDMAC_DT_PER_IF(1) | 335 + AT91_XDMAC_DT_PERID(24))>, 336 + <&dma0 337 + (AT91_XDMAC_DT_MEM_IF(0) | 338 + AT91_XDMAC_DT_PER_IF(1) | 339 + AT91_XDMAC_DT_PERID(25))>; 340 + dma-names = "tx", "rx"; 341 + atmel,fifo-size = <16>; 342 + status = "disabled"; 343 + }; 420 344 }; 421 345 422 346 pit64b: timer@f0028000 { ··· 575 421 ranges = <0x0 0xf8010000 0x800>; 576 422 status = "disabled"; 577 423 424 + uart6: serial@200 { 425 + compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; 426 + reg = <0x200 0x200>; 427 + interrupts = <9 IRQ_TYPE_LEVEL_HIGH 7>; 428 + dmas = <&dma0 429 + (AT91_XDMAC_DT_MEM_IF(0) | 430 + AT91_XDMAC_DT_PER_IF(1) | 431 + AT91_XDMAC_DT_PERID(12))>, 432 + <&dma0 433 + (AT91_XDMAC_DT_MEM_IF(0) | 434 + AT91_XDMAC_DT_PER_IF(1) | 435 + AT91_XDMAC_DT_PERID(13))>; 436 + dma-names = "tx", "rx"; 437 + clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; 438 + clock-names = "usart"; 439 + atmel,use-dma-rx; 440 + atmel,use-dma-tx; 441 + atmel,fifo-size = <16>; 442 + status = "disabled"; 443 + }; 444 + 578 445 i2c6: i2c@600 { 579 446 compatible = "microchip,sam9x60-i2c"; 580 447 reg = <0x600 0x200>; ··· 623 448 #size-cells = <1>; 624 449 ranges = <0x0 0xf8014000 0x800>; 625 450 status = "disabled"; 451 + 452 + uart7: serial@200 { 453 + compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; 454 + reg = <0x200 0x200>; 455 + interrupts = <10 IRQ_TYPE_LEVEL_HIGH 7>; 456 + dmas = <&dma0 457 + (AT91_XDMAC_DT_MEM_IF(0) | 458 + AT91_XDMAC_DT_PER_IF(1) | 459 + AT91_XDMAC_DT_PERID(14))>, 460 + <&dma0 461 + (AT91_XDMAC_DT_MEM_IF(0) | 462 + AT91_XDMAC_DT_PER_IF(1) | 463 + AT91_XDMAC_DT_PERID(15))>; 464 + dma-names = "tx", "rx"; 465 + clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; 466 + clock-names = "usart"; 467 + atmel,use-dma-rx; 468 + atmel,use-dma-tx; 469 + atmel,fifo-size = <16>; 470 + status = "disabled"; 471 + }; 472 + 473 + i2c7: i2c@600 { 474 + compatible = "microchip,sam9x60-i2c"; 475 + reg = <0x600 0x200>; 476 + interrupts = <10 IRQ_TYPE_LEVEL_HIGH 7>; 477 + clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; 478 + dmas = <&dma0 479 + (AT91_XDMAC_DT_MEM_IF(0) | 480 + AT91_XDMAC_DT_PER_IF(1) | 481 + AT91_XDMAC_DT_PERID(14))>, 482 + <&dma0 483 + (AT91_XDMAC_DT_MEM_IF(0) | 484 + AT91_XDMAC_DT_PER_IF(1) | 485 + AT91_XDMAC_DT_PERID(15))>; 486 + dma-names = "tx", "rx"; 487 + atmel,fifo-size = <16>; 488 + status = "disabled"; 489 + }; 626 490 }; 627 491 628 492 flx8: flexcom@f8018000 { ··· 672 458 #size-cells = <1>; 673 459 ranges = <0x0 0xf8018000 0x800>; 674 460 status = "disabled"; 461 + 462 + uart8: serial@200 { 463 + compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; 464 + reg = <0x200 0x200>; 465 + interrupts = <11 IRQ_TYPE_LEVEL_HIGH 7>; 466 + dmas = <&dma0 467 + (AT91_XDMAC_DT_MEM_IF(0) | 468 + AT91_XDMAC_DT_PER_IF(1) | 469 + AT91_XDMAC_DT_PERID(16))>, 470 + <&dma0 471 + (AT91_XDMAC_DT_MEM_IF(0) | 472 + AT91_XDMAC_DT_PER_IF(1) | 473 + AT91_XDMAC_DT_PERID(17))>; 474 + dma-names = "tx", "rx"; 475 + clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; 476 + clock-names = "usart"; 477 + atmel,use-dma-rx; 478 + atmel,use-dma-tx; 479 + atmel,fifo-size = <16>; 480 + status = "disabled"; 481 + }; 482 + 483 + i2c8: i2c@600 { 484 + compatible = "microchip,sam9x60-i2c"; 485 + reg = <0x600 0x200>; 486 + interrupts = <11 IRQ_TYPE_LEVEL_HIGH 7>; 487 + clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; 488 + dmas = <&dma0 489 + (AT91_XDMAC_DT_MEM_IF(0) | 490 + AT91_XDMAC_DT_PER_IF(1) | 491 + AT91_XDMAC_DT_PERID(16))>, 492 + <&dma0 493 + (AT91_XDMAC_DT_MEM_IF(0) | 494 + AT91_XDMAC_DT_PER_IF(1) | 495 + AT91_XDMAC_DT_PERID(17))>; 496 + dma-names = "tx", "rx"; 497 + atmel,fifo-size = <16>; 498 + status = "disabled"; 499 + }; 675 500 }; 676 501 677 502 flx0: flexcom@f801c000 { ··· 721 468 #size-cells = <1>; 722 469 ranges = <0x0 0xf801c000 0x800>; 723 470 status = "disabled"; 471 + 472 + uart0: serial@200 { 473 + compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; 474 + reg = <0x200 0x200>; 475 + interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>; 476 + dmas = <&dma0 477 + (AT91_XDMAC_DT_MEM_IF(0) | 478 + AT91_XDMAC_DT_PER_IF(1) | 479 + AT91_XDMAC_DT_PERID(0))>, 480 + <&dma0 481 + (AT91_XDMAC_DT_MEM_IF(0) | 482 + AT91_XDMAC_DT_PER_IF(1) | 483 + AT91_XDMAC_DT_PERID(1))>; 484 + dma-names = "tx", "rx"; 485 + clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; 486 + clock-names = "usart"; 487 + atmel,use-dma-rx; 488 + atmel,use-dma-tx; 489 + atmel,fifo-size = <16>; 490 + status = "disabled"; 491 + }; 492 + 493 + spi0: spi@400 { 494 + compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi"; 495 + reg = <0x400 0x200>; 496 + interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>; 497 + clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; 498 + clock-names = "spi_clk"; 499 + dmas = <&dma0 500 + (AT91_XDMAC_DT_MEM_IF(0) | 501 + AT91_XDMAC_DT_PER_IF(1) | 502 + AT91_XDMAC_DT_PERID(0))>, 503 + <&dma0 504 + (AT91_XDMAC_DT_MEM_IF(0) | 505 + AT91_XDMAC_DT_PER_IF(1) | 506 + AT91_XDMAC_DT_PERID(1))>; 507 + dma-names = "tx", "rx"; 508 + atmel,fifo-size = <16>; 509 + status = "disabled"; 510 + }; 724 511 725 512 i2c0: i2c@600 { 726 513 compatible = "microchip,sam9x60-i2c"; ··· 789 496 #size-cells = <1>; 790 497 ranges = <0x0 0xf8020000 0x800>; 791 498 status = "disabled"; 499 + 500 + uart1: serial@200 { 501 + compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; 502 + reg = <0x200 0x200>; 503 + interrupts = <6 IRQ_TYPE_LEVEL_HIGH 7>; 504 + dmas = <&dma0 505 + (AT91_XDMAC_DT_MEM_IF(0) | 506 + AT91_XDMAC_DT_PER_IF(1) | 507 + AT91_XDMAC_DT_PERID(2))>, 508 + <&dma0 509 + (AT91_XDMAC_DT_MEM_IF(0) | 510 + AT91_XDMAC_DT_PER_IF(1) | 511 + AT91_XDMAC_DT_PERID(3))>; 512 + dma-names = "tx", "rx"; 513 + clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; 514 + clock-names = "usart"; 515 + atmel,use-dma-rx; 516 + atmel,use-dma-tx; 517 + atmel,fifo-size = <16>; 518 + status = "disabled"; 519 + }; 520 + 521 + spi1: spi@400 { 522 + compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi"; 523 + reg = <0x400 0x200>; 524 + interrupts = <6 IRQ_TYPE_LEVEL_HIGH 7>; 525 + clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; 526 + clock-names = "spi_clk"; 527 + dmas = <&dma0 528 + (AT91_XDMAC_DT_MEM_IF(0) | 529 + AT91_XDMAC_DT_PER_IF(1) | 530 + AT91_XDMAC_DT_PERID(2))>, 531 + <&dma0 532 + (AT91_XDMAC_DT_MEM_IF(0) | 533 + AT91_XDMAC_DT_PER_IF(1) | 534 + AT91_XDMAC_DT_PERID(3))>; 535 + dma-names = "tx", "rx"; 536 + atmel,fifo-size = <16>; 537 + status = "disabled"; 538 + }; 539 + 540 + i2c1: i2c@600 { 541 + compatible = "microchip,sam9x60-i2c"; 542 + reg = <0x600 0x200>; 543 + interrupts = <6 IRQ_TYPE_LEVEL_HIGH 7>; 544 + clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; 545 + dmas = <&dma0 546 + (AT91_XDMAC_DT_MEM_IF(0) | 547 + AT91_XDMAC_DT_PER_IF(1) | 548 + AT91_XDMAC_DT_PERID(2))>, 549 + <&dma0 550 + (AT91_XDMAC_DT_MEM_IF(0) | 551 + AT91_XDMAC_DT_PER_IF(1) | 552 + AT91_XDMAC_DT_PERID(3))>; 553 + dma-names = "tx", "rx"; 554 + atmel,fifo-size = <16>; 555 + status = "disabled"; 556 + }; 792 557 }; 793 558 794 559 flx2: flexcom@f8024000 { ··· 857 506 #size-cells = <1>; 858 507 ranges = <0x0 0xf8024000 0x800>; 859 508 status = "disabled"; 509 + 510 + uart2: serial@200 { 511 + compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; 512 + reg = <0x200 0x200>; 513 + interrupts = <7 IRQ_TYPE_LEVEL_HIGH 7>; 514 + dmas = <&dma0 515 + (AT91_XDMAC_DT_MEM_IF(0) | 516 + AT91_XDMAC_DT_PER_IF(1) | 517 + AT91_XDMAC_DT_PERID(4))>, 518 + <&dma0 519 + (AT91_XDMAC_DT_MEM_IF(0) | 520 + AT91_XDMAC_DT_PER_IF(1) | 521 + AT91_XDMAC_DT_PERID(5))>; 522 + dma-names = "tx", "rx"; 523 + clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; 524 + clock-names = "usart"; 525 + atmel,use-dma-rx; 526 + atmel,use-dma-tx; 527 + atmel,fifo-size = <16>; 528 + status = "disabled"; 529 + }; 530 + 531 + spi2: spi@400 { 532 + compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi"; 533 + reg = <0x400 0x200>; 534 + interrupts = <7 IRQ_TYPE_LEVEL_HIGH 7>; 535 + clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; 536 + clock-names = "spi_clk"; 537 + dmas = <&dma0 538 + (AT91_XDMAC_DT_MEM_IF(0) | 539 + AT91_XDMAC_DT_PER_IF(1) | 540 + AT91_XDMAC_DT_PERID(4))>, 541 + <&dma0 542 + (AT91_XDMAC_DT_MEM_IF(0) | 543 + AT91_XDMAC_DT_PER_IF(1) | 544 + AT91_XDMAC_DT_PERID(5))>; 545 + dma-names = "tx", "rx"; 546 + atmel,fifo-size = <16>; 547 + status = "disabled"; 548 + }; 549 + 550 + i2c2: i2c@600 { 551 + compatible = "microchip,sam9x60-i2c"; 552 + reg = <0x600 0x200>; 553 + interrupts = <7 IRQ_TYPE_LEVEL_HIGH 7>; 554 + clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; 555 + dmas = <&dma0 556 + (AT91_XDMAC_DT_MEM_IF(0) | 557 + AT91_XDMAC_DT_PER_IF(1) | 558 + AT91_XDMAC_DT_PERID(4))>, 559 + <&dma0 560 + (AT91_XDMAC_DT_MEM_IF(0) | 561 + AT91_XDMAC_DT_PER_IF(1) | 562 + AT91_XDMAC_DT_PERID(5))>; 563 + dma-names = "tx", "rx"; 564 + atmel,fifo-size = <16>; 565 + status = "disabled"; 566 + }; 860 567 }; 861 568 862 569 flx3: flexcom@f8028000 { ··· 925 516 #size-cells = <1>; 926 517 ranges = <0x0 0xf8028000 0x800>; 927 518 status = "disabled"; 519 + 520 + uart3: serial@200 { 521 + compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; 522 + reg = <0x200 0x200>; 523 + interrupts = <8 IRQ_TYPE_LEVEL_HIGH 7>; 524 + dmas = <&dma0 525 + (AT91_XDMAC_DT_MEM_IF(0) | 526 + AT91_XDMAC_DT_PER_IF(1) | 527 + AT91_XDMAC_DT_PERID(6))>, 528 + <&dma0 529 + (AT91_XDMAC_DT_MEM_IF(0) | 530 + AT91_XDMAC_DT_PER_IF(1) | 531 + AT91_XDMAC_DT_PERID(7))>; 532 + dma-names = "tx", "rx"; 533 + clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; 534 + clock-names = "usart"; 535 + atmel,use-dma-rx; 536 + atmel,use-dma-tx; 537 + atmel,fifo-size = <16>; 538 + status = "disabled"; 539 + }; 540 + 541 + spi3: spi@400 { 542 + compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi"; 543 + reg = <0x400 0x200>; 544 + interrupts = <8 IRQ_TYPE_LEVEL_HIGH 7>; 545 + clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; 546 + clock-names = "spi_clk"; 547 + dmas = <&dma0 548 + (AT91_XDMAC_DT_MEM_IF(0) | 549 + AT91_XDMAC_DT_PER_IF(1) | 550 + AT91_XDMAC_DT_PERID(6))>, 551 + <&dma0 552 + (AT91_XDMAC_DT_MEM_IF(0) | 553 + AT91_XDMAC_DT_PER_IF(1) | 554 + AT91_XDMAC_DT_PERID(7))>; 555 + dma-names = "tx", "rx"; 556 + atmel,fifo-size = <16>; 557 + status = "disabled"; 558 + }; 559 + 560 + i2c3: i2c@600 { 561 + compatible = "microchip,sam9x60-i2c"; 562 + reg = <0x600 0x200>; 563 + interrupts = <8 IRQ_TYPE_LEVEL_HIGH 7>; 564 + clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; 565 + dmas = <&dma0 566 + (AT91_XDMAC_DT_MEM_IF(0) | 567 + AT91_XDMAC_DT_PER_IF(1) | 568 + AT91_XDMAC_DT_PERID(6))>, 569 + <&dma0 570 + (AT91_XDMAC_DT_MEM_IF(0) | 571 + AT91_XDMAC_DT_PER_IF(1) | 572 + AT91_XDMAC_DT_PERID(7))>; 573 + dma-names = "tx", "rx"; 574 + atmel,fifo-size = <16>; 575 + status = "disabled"; 576 + }; 928 577 }; 929 578 930 579 macb0: ethernet@f802c000 { ··· 1048 581 #size-cells = <1>; 1049 582 ranges = <0x0 0xf8040000 0x800>; 1050 583 status = "disabled"; 584 + 585 + uart9: serial@200 { 586 + compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; 587 + reg = <0x200 0x200>; 588 + interrupts = <15 IRQ_TYPE_LEVEL_HIGH 7>; 589 + dmas = <&dma0 590 + (AT91_XDMAC_DT_MEM_IF(0) | 591 + AT91_XDMAC_DT_PER_IF(1) | 592 + AT91_XDMAC_DT_PERID(18))>, 593 + <&dma0 594 + (AT91_XDMAC_DT_MEM_IF(0) | 595 + AT91_XDMAC_DT_PER_IF(1) | 596 + AT91_XDMAC_DT_PERID(19))>; 597 + dma-names = "tx", "rx"; 598 + clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; 599 + clock-names = "usart"; 600 + atmel,use-dma-rx; 601 + atmel,use-dma-tx; 602 + atmel,fifo-size = <16>; 603 + status = "disabled"; 604 + }; 605 + 606 + i2c9: i2c@600 { 607 + compatible = "microchip,sam9x60-i2c"; 608 + reg = <0x600 0x200>; 609 + interrupts = <15 IRQ_TYPE_LEVEL_HIGH 7>; 610 + clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; 611 + dmas = <&dma0 612 + (AT91_XDMAC_DT_MEM_IF(0) | 613 + AT91_XDMAC_DT_PER_IF(1) | 614 + AT91_XDMAC_DT_PERID(18))>, 615 + <&dma0 616 + (AT91_XDMAC_DT_MEM_IF(0) | 617 + AT91_XDMAC_DT_PER_IF(1) | 618 + AT91_XDMAC_DT_PERID(19))>; 619 + dma-names = "tx", "rx"; 620 + atmel,fifo-size = <16>; 621 + status = "disabled"; 622 + }; 1051 623 }; 1052 624 1053 625 flx10: flexcom@f8044000 { ··· 1097 591 #size-cells = <1>; 1098 592 ranges = <0x0 0xf8044000 0x800>; 1099 593 status = "disabled"; 594 + 595 + uart10: serial@200 { 596 + compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; 597 + reg = <0x200 0x200>; 598 + interrupts = <16 IRQ_TYPE_LEVEL_HIGH 7>; 599 + dmas = <&dma0 600 + (AT91_XDMAC_DT_MEM_IF(0) | 601 + AT91_XDMAC_DT_PER_IF(1) | 602 + AT91_XDMAC_DT_PERID(20))>, 603 + <&dma0 604 + (AT91_XDMAC_DT_MEM_IF(0) | 605 + AT91_XDMAC_DT_PER_IF(1) | 606 + AT91_XDMAC_DT_PERID(21))>; 607 + dma-names = "tx", "rx"; 608 + clocks = <&pmc PMC_TYPE_PERIPHERAL 16>; 609 + clock-names = "usart"; 610 + atmel,use-dma-rx; 611 + atmel,use-dma-tx; 612 + atmel,fifo-size = <16>; 613 + status = "disabled"; 614 + }; 615 + 616 + i2c10: i2c@600 { 617 + compatible = "microchip,sam9x60-i2c"; 618 + reg = <0x600 0x200>; 619 + interrupts = <16 IRQ_TYPE_LEVEL_HIGH 7>; 620 + clocks = <&pmc PMC_TYPE_PERIPHERAL 16>; 621 + dmas = <&dma0 622 + (AT91_XDMAC_DT_MEM_IF(0) | 623 + AT91_XDMAC_DT_PER_IF(1) | 624 + AT91_XDMAC_DT_PERID(20))>, 625 + <&dma0 626 + (AT91_XDMAC_DT_MEM_IF(0) | 627 + AT91_XDMAC_DT_PER_IF(1) | 628 + AT91_XDMAC_DT_PERID(21))>; 629 + dma-names = "tx", "rx"; 630 + atmel,fifo-size = <16>; 631 + status = "disabled"; 632 + }; 1100 633 }; 1101 634 1102 635 isi: isi@f8048000 {