net: airoha: Remove code duplication in airoha_regs.h

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

This patch does not introduce any logical change, it just removes
duplicated code in airoha_regs.h.
Fix naming conventions in airoha_regs.h.

Reviewed-by: Simon Horman <horms@kernel.org>
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
Link: https://patch.msgid.link/20251022-airoha-regs-cosmetics-v2-1-e0425b3f2c2c@kernel.org
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

authored by

Lorenzo Bianconi and committed by

Jakub Kicinski 5 months ago 99ad2b68 2b7553db

+100 -111

2 changed files

expand all

drivers

net

ethernet

airoha

airoha_eth.c

airoha_regs.h

+51 -51

drivers/net/ethernet/airoha/airoha_eth.c

··· 137 137 138 138 for (p = 1; p <= ARRAY_SIZE(eth->ports); p++) 139 139 airoha_fe_set(eth, REG_GDM_FWD_CFG(p), 140 - GDM_TCP_CKSUM | GDM_UDP_CKSUM | GDM_IP4_CKSUM | 141 - GDM_DROP_CRC_ERR); 140 + GDM_TCP_CKSUM_MASK | GDM_UDP_CKSUM_MASK | 141 + GDM_IP4_CKSUM_MASK | GDM_DROP_CRC_ERR_MASK); 142 142 143 - airoha_fe_rmw(eth, REG_CDM1_VLAN_CTRL, CDM1_VLAN_MASK, 144 - FIELD_PREP(CDM1_VLAN_MASK, 0x8100)); 143 + airoha_fe_rmw(eth, REG_CDM_VLAN_CTRL(1), CDM_VLAN_MASK, 144 + FIELD_PREP(CDM_VLAN_MASK, 0x8100)); 145 145 146 146 airoha_fe_set(eth, REG_FE_CPORT_CFG, FE_CPORT_PAD); 147 147 } ··· 403 403 static void airoha_fe_crsn_qsel_init(struct airoha_eth *eth) 404 404 { 405 405 /* CDM1_CRSN_QSEL */ 406 - airoha_fe_rmw(eth, REG_CDM1_CRSN_QSEL(CRSN_22 >> 2), 407 - CDM1_CRSN_QSEL_REASON_MASK(CRSN_22), 408 - FIELD_PREP(CDM1_CRSN_QSEL_REASON_MASK(CRSN_22), 406 + airoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(1, CRSN_22 >> 2), 407 + CDM_CRSN_QSEL_REASON_MASK(CRSN_22), 408 + FIELD_PREP(CDM_CRSN_QSEL_REASON_MASK(CRSN_22), 409 409 CDM_CRSN_QSEL_Q1)); 410 - airoha_fe_rmw(eth, REG_CDM1_CRSN_QSEL(CRSN_08 >> 2), 411 - CDM1_CRSN_QSEL_REASON_MASK(CRSN_08), 412 - FIELD_PREP(CDM1_CRSN_QSEL_REASON_MASK(CRSN_08), 410 + airoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(1, CRSN_08 >> 2), 411 + CDM_CRSN_QSEL_REASON_MASK(CRSN_08), 412 + FIELD_PREP(CDM_CRSN_QSEL_REASON_MASK(CRSN_08), 413 413 CDM_CRSN_QSEL_Q1)); 414 - airoha_fe_rmw(eth, REG_CDM1_CRSN_QSEL(CRSN_21 >> 2), 415 - CDM1_CRSN_QSEL_REASON_MASK(CRSN_21), 416 - FIELD_PREP(CDM1_CRSN_QSEL_REASON_MASK(CRSN_21), 414 + airoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(1, CRSN_21 >> 2), 415 + CDM_CRSN_QSEL_REASON_MASK(CRSN_21), 416 + FIELD_PREP(CDM_CRSN_QSEL_REASON_MASK(CRSN_21), 417 417 CDM_CRSN_QSEL_Q1)); 418 - airoha_fe_rmw(eth, REG_CDM1_CRSN_QSEL(CRSN_24 >> 2), 419 - CDM1_CRSN_QSEL_REASON_MASK(CRSN_24), 420 - FIELD_PREP(CDM1_CRSN_QSEL_REASON_MASK(CRSN_24), 418 + airoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(1, CRSN_24 >> 2), 419 + CDM_CRSN_QSEL_REASON_MASK(CRSN_24), 420 + FIELD_PREP(CDM_CRSN_QSEL_REASON_MASK(CRSN_24), 421 421 CDM_CRSN_QSEL_Q6)); 422 - airoha_fe_rmw(eth, REG_CDM1_CRSN_QSEL(CRSN_25 >> 2), 423 - CDM1_CRSN_QSEL_REASON_MASK(CRSN_25), 424 - FIELD_PREP(CDM1_CRSN_QSEL_REASON_MASK(CRSN_25), 422 + airoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(1, CRSN_25 >> 2), 423 + CDM_CRSN_QSEL_REASON_MASK(CRSN_25), 424 + FIELD_PREP(CDM_CRSN_QSEL_REASON_MASK(CRSN_25), 425 425 CDM_CRSN_QSEL_Q1)); 426 426 /* CDM2_CRSN_QSEL */ 427 - airoha_fe_rmw(eth, REG_CDM2_CRSN_QSEL(CRSN_08 >> 2), 428 - CDM2_CRSN_QSEL_REASON_MASK(CRSN_08), 429 - FIELD_PREP(CDM2_CRSN_QSEL_REASON_MASK(CRSN_08), 427 + airoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(2, CRSN_08 >> 2), 428 + CDM_CRSN_QSEL_REASON_MASK(CRSN_08), 429 + FIELD_PREP(CDM_CRSN_QSEL_REASON_MASK(CRSN_08), 430 430 CDM_CRSN_QSEL_Q1)); 431 - airoha_fe_rmw(eth, REG_CDM2_CRSN_QSEL(CRSN_21 >> 2), 432 - CDM2_CRSN_QSEL_REASON_MASK(CRSN_21), 433 - FIELD_PREP(CDM2_CRSN_QSEL_REASON_MASK(CRSN_21), 431 + airoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(2, CRSN_21 >> 2), 432 + CDM_CRSN_QSEL_REASON_MASK(CRSN_21), 433 + FIELD_PREP(CDM_CRSN_QSEL_REASON_MASK(CRSN_21), 434 434 CDM_CRSN_QSEL_Q1)); 435 - airoha_fe_rmw(eth, REG_CDM2_CRSN_QSEL(CRSN_22 >> 2), 436 - CDM2_CRSN_QSEL_REASON_MASK(CRSN_22), 437 - FIELD_PREP(CDM2_CRSN_QSEL_REASON_MASK(CRSN_22), 435 + airoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(2, CRSN_22 >> 2), 436 + CDM_CRSN_QSEL_REASON_MASK(CRSN_22), 437 + FIELD_PREP(CDM_CRSN_QSEL_REASON_MASK(CRSN_22), 438 438 CDM_CRSN_QSEL_Q1)); 439 - airoha_fe_rmw(eth, REG_CDM2_CRSN_QSEL(CRSN_24 >> 2), 440 - CDM2_CRSN_QSEL_REASON_MASK(CRSN_24), 441 - FIELD_PREP(CDM2_CRSN_QSEL_REASON_MASK(CRSN_24), 439 + airoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(2, CRSN_24 >> 2), 440 + CDM_CRSN_QSEL_REASON_MASK(CRSN_24), 441 + FIELD_PREP(CDM_CRSN_QSEL_REASON_MASK(CRSN_24), 442 442 CDM_CRSN_QSEL_Q6)); 443 - airoha_fe_rmw(eth, REG_CDM2_CRSN_QSEL(CRSN_25 >> 2), 444 - CDM2_CRSN_QSEL_REASON_MASK(CRSN_25), 445 - FIELD_PREP(CDM2_CRSN_QSEL_REASON_MASK(CRSN_25), 443 + airoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(2, CRSN_25 >> 2), 444 + CDM_CRSN_QSEL_REASON_MASK(CRSN_25), 445 + FIELD_PREP(CDM_CRSN_QSEL_REASON_MASK(CRSN_25), 446 446 CDM_CRSN_QSEL_Q1)); 447 447 } 448 448 ··· 462 462 airoha_fe_wr(eth, REG_FE_PCE_CFG, 463 463 PCE_DPI_EN_MASK | PCE_KA_EN_MASK | PCE_MC_EN_MASK); 464 464 /* set vip queue selection to ring 1 */ 465 - airoha_fe_rmw(eth, REG_CDM1_FWD_CFG, CDM1_VIP_QSEL_MASK, 466 - FIELD_PREP(CDM1_VIP_QSEL_MASK, 0x4)); 467 - airoha_fe_rmw(eth, REG_CDM2_FWD_CFG, CDM2_VIP_QSEL_MASK, 468 - FIELD_PREP(CDM2_VIP_QSEL_MASK, 0x4)); 465 + airoha_fe_rmw(eth, REG_CDM_FWD_CFG(1), CDM_VIP_QSEL_MASK, 466 + FIELD_PREP(CDM_VIP_QSEL_MASK, 0x4)); 467 + airoha_fe_rmw(eth, REG_CDM_FWD_CFG(2), CDM_VIP_QSEL_MASK, 468 + FIELD_PREP(CDM_VIP_QSEL_MASK, 0x4)); 469 469 /* set GDM4 source interface offset to 8 */ 470 - airoha_fe_rmw(eth, REG_GDM4_SRC_PORT_SET, 471 - GDM4_SPORT_OFF2_MASK | 472 - GDM4_SPORT_OFF1_MASK | 473 - GDM4_SPORT_OFF0_MASK, 474 - FIELD_PREP(GDM4_SPORT_OFF2_MASK, 8) | 475 - FIELD_PREP(GDM4_SPORT_OFF1_MASK, 8) | 476 - FIELD_PREP(GDM4_SPORT_OFF0_MASK, 8)); 470 + airoha_fe_rmw(eth, REG_GDM_SRC_PORT_SET(4), 471 + GDM_SPORT_OFF2_MASK | 472 + GDM_SPORT_OFF1_MASK | 473 + GDM_SPORT_OFF0_MASK, 474 + FIELD_PREP(GDM_SPORT_OFF2_MASK, 8) | 475 + FIELD_PREP(GDM_SPORT_OFF1_MASK, 8) | 476 + FIELD_PREP(GDM_SPORT_OFF0_MASK, 8)); 477 477 478 478 /* set PSE Page as 128B */ 479 479 airoha_fe_rmw(eth, REG_FE_DMA_GLO_CFG, ··· 499 499 airoha_fe_set(eth, REG_GDM_MISC_CFG, 500 500 GDM2_RDM_ACK_WAIT_PREF_MASK | 501 501 GDM2_CHN_VLD_MODE_MASK); 502 - airoha_fe_rmw(eth, REG_CDM2_FWD_CFG, CDM2_OAM_QSEL_MASK, 503 - FIELD_PREP(CDM2_OAM_QSEL_MASK, 15)); 502 + airoha_fe_rmw(eth, REG_CDM_FWD_CFG(2), CDM_OAM_QSEL_MASK, 503 + FIELD_PREP(CDM_OAM_QSEL_MASK, 15)); 504 504 505 505 /* init fragment and assemble Force Port */ 506 506 /* NPU Core-3, NPU Bridge Channel-3 */ ··· 514 514 FIELD_PREP(IP_ASSEMBLE_PORT_MASK, 0) | 515 515 FIELD_PREP(IP_ASSEMBLE_NBQ_MASK, 22)); 516 516 517 - airoha_fe_set(eth, REG_GDM3_FWD_CFG, GDM3_PAD_EN_MASK); 518 - airoha_fe_set(eth, REG_GDM4_FWD_CFG, GDM4_PAD_EN_MASK); 517 + airoha_fe_set(eth, REG_GDM_FWD_CFG(3), GDM_PAD_EN_MASK); 518 + airoha_fe_set(eth, REG_GDM_FWD_CFG(4), GDM_PAD_EN_MASK); 519 519 520 520 airoha_fe_crsn_qsel_init(eth); 521 521 ··· 523 523 airoha_fe_set(eth, REG_FE_CPORT_CFG, FE_CPORT_PORT_XFC_MASK); 524 524 525 525 /* default aging mode for mbi unlock issue */ 526 - airoha_fe_rmw(eth, REG_GDM2_CHN_RLS, 526 + airoha_fe_rmw(eth, REG_GDM_CHN_RLS(2), 527 527 MBI_RX_AGE_SEL_MASK | MBI_TX_AGE_SEL_MASK, 528 528 FIELD_PREP(MBI_RX_AGE_SEL_MASK, 3) | 529 529 FIELD_PREP(MBI_TX_AGE_SEL_MASK, 3)); ··· 1692 1692 pse_port = port->id == AIROHA_GDM3_IDX ? FE_PSE_PORT_GDM3 1693 1693 : FE_PSE_PORT_GDM4; 1694 1694 airoha_set_gdm_port_fwd_cfg(eth, REG_GDM_FWD_CFG(2), pse_port); 1695 - airoha_fe_clear(eth, REG_GDM_FWD_CFG(2), GDM_STRIP_CRC); 1695 + airoha_fe_clear(eth, REG_GDM_FWD_CFG(2), GDM_STRIP_CRC_MASK); 1696 1696 1697 1697 /* Enable GDM2 loopback */ 1698 1698 airoha_fe_wr(eth, REG_GDM_TXCHN_EN(2), 0xffffffff);

+49 -60

drivers/net/ethernet/airoha/airoha_regs.h

··· 23 23 #define GDM3_BASE 0x1100 24 24 #define GDM4_BASE 0x2500 25 25 26 + #define CDM_BASE(_n) \ 27 + ((_n) == 2 ? CDM2_BASE : CDM1_BASE) 26 28 #define GDM_BASE(_n) \ 27 29 ((_n) == 4 ? GDM4_BASE : \ 28 30 (_n) == 3 ? GDM3_BASE : \ ··· 111 109 #define PATN_DP_MASK GENMASK(31, 16) 112 110 #define PATN_SP_MASK GENMASK(15, 0) 113 111 114 - #define REG_CDM1_VLAN_CTRL CDM1_BASE 115 - #define CDM1_VLAN_MASK GENMASK(31, 16) 112 + #define REG_CDM_VLAN_CTRL(_n) CDM_BASE(_n) 113 + #define CDM_VLAN_MASK GENMASK(31, 16) 116 114 117 - #define REG_CDM1_FWD_CFG (CDM1_BASE + 0x08) 118 - #define CDM1_VIP_QSEL_MASK GENMASK(24, 20) 115 + #define REG_CDM_FWD_CFG(_n) (CDM_BASE(_n) + 0x08) 116 + #define CDM_OAM_QSEL_MASK GENMASK(31, 27) 117 + #define CDM_VIP_QSEL_MASK GENMASK(24, 20) 119 118 120 - #define REG_CDM1_CRSN_QSEL(_n) (CDM1_BASE + 0x10 + ((_n) << 2)) 121 - #define CDM1_CRSN_QSEL_REASON_MASK(_n) \ 122 - GENMASK(4 + (((_n) % 4) << 3), (((_n) % 4) << 3)) 123 - 124 - #define REG_CDM2_FWD_CFG (CDM2_BASE + 0x08) 125 - #define CDM2_OAM_QSEL_MASK GENMASK(31, 27) 126 - #define CDM2_VIP_QSEL_MASK GENMASK(24, 20) 127 - 128 - #define REG_CDM2_CRSN_QSEL(_n) (CDM2_BASE + 0x10 + ((_n) << 2)) 129 - #define CDM2_CRSN_QSEL_REASON_MASK(_n) \ 119 + #define REG_CDM_CRSN_QSEL(_n, _m) (CDM_BASE(_n) + 0x10 + ((_m) << 2)) 120 + #define CDM_CRSN_QSEL_REASON_MASK(_n) \ 130 121 GENMASK(4 + (((_n) % 4) << 3), (((_n) % 4) << 3)) 131 122 132 123 #define REG_GDM_FWD_CFG(_n) GDM_BASE(_n) 133 - #define GDM_DROP_CRC_ERR BIT(23) 134 - #define GDM_IP4_CKSUM BIT(22) 135 - #define GDM_TCP_CKSUM BIT(21) 136 - #define GDM_UDP_CKSUM BIT(20) 137 - #define GDM_STRIP_CRC BIT(16) 124 + #define GDM_PAD_EN_MASK BIT(28) 125 + #define GDM_DROP_CRC_ERR_MASK BIT(23) 126 + #define GDM_IP4_CKSUM_MASK BIT(22) 127 + #define GDM_TCP_CKSUM_MASK BIT(21) 128 + #define GDM_UDP_CKSUM_MASK BIT(20) 129 + #define GDM_STRIP_CRC_MASK BIT(16) 138 130 #define GDM_UCFQ_MASK GENMASK(15, 12) 139 131 #define GDM_BCFQ_MASK GENMASK(11, 8) 140 132 #define GDM_MCFQ_MASK GENMASK(7, 4) ··· 152 156 #define LBK_CHAN_MODE_MASK BIT(1) 153 157 #define LPBK_EN_MASK BIT(0) 154 158 159 + #define REG_GDM_CHN_RLS(_n) (GDM_BASE(_n) + 0x20) 160 + #define MBI_RX_AGE_SEL_MASK GENMASK(26, 25) 161 + #define MBI_TX_AGE_SEL_MASK GENMASK(18, 17) 162 + 155 163 #define REG_GDM_TXCHN_EN(_n) (GDM_BASE(_n) + 0x24) 156 164 #define REG_GDM_RXCHN_EN(_n) (GDM_BASE(_n) + 0x28) 157 165 ··· 168 168 #define FE_GDM_MIB_RX_CLEAR_MASK BIT(1) 169 169 #define FE_GDM_MIB_TX_CLEAR_MASK BIT(0) 170 170 171 - #define REG_FE_GDM1_MIB_CFG (GDM1_BASE + 0xf4) 171 + #define REG_FE_GDM_MIB_CFG(_n) (GDM_BASE(_n) + 0xf4) 172 172 #define FE_STRICT_RFC2819_MODE_MASK BIT(31) 173 - #define FE_GDM1_TX_MIB_SPLIT_EN_MASK BIT(17) 174 - #define FE_GDM1_RX_MIB_SPLIT_EN_MASK BIT(16) 173 + #define FE_GDM_TX_MIB_SPLIT_EN_MASK BIT(17) 174 + #define FE_GDM_RX_MIB_SPLIT_EN_MASK BIT(16) 175 175 #define FE_TX_MIB_ID_MASK GENMASK(15, 8) 176 176 #define FE_RX_MIB_ID_MASK GENMASK(7, 0) 177 177 ··· 213 213 #define REG_FE_GDM_RX_ETH_L255_CNT_L(_n) (GDM_BASE(_n) + 0x194) 214 214 #define REG_FE_GDM_RX_ETH_L511_CNT_L(_n) (GDM_BASE(_n) + 0x198) 215 215 #define REG_FE_GDM_RX_ETH_L1023_CNT_L(_n) (GDM_BASE(_n) + 0x19c) 216 + 217 + #define REG_GDM_SRC_PORT_SET(_n) (GDM_BASE(_n) + 0x23c) 218 + #define GDM_SPORT_OFF2_MASK GENMASK(19, 16) 219 + #define GDM_SPORT_OFF1_MASK GENMASK(15, 12) 220 + #define GDM_SPORT_OFF0_MASK GENMASK(11, 8) 221 + 222 + #define REG_FE_GDM_TX_OK_PKT_CNT_H(_n) (GDM_BASE(_n) + 0x280) 223 + #define REG_FE_GDM_TX_OK_BYTE_CNT_H(_n) (GDM_BASE(_n) + 0x284) 224 + #define REG_FE_GDM_TX_ETH_PKT_CNT_H(_n) (GDM_BASE(_n) + 0x288) 225 + #define REG_FE_GDM_TX_ETH_BYTE_CNT_H(_n) (GDM_BASE(_n) + 0x28c) 226 + 227 + #define REG_FE_GDM_RX_OK_PKT_CNT_H(_n) (GDM_BASE(_n) + 0x290) 228 + #define REG_FE_GDM_RX_OK_BYTE_CNT_H(_n) (GDM_BASE(_n) + 0x294) 229 + #define REG_FE_GDM_RX_ETH_PKT_CNT_H(_n) (GDM_BASE(_n) + 0x298) 230 + #define REG_FE_GDM_RX_ETH_BYTE_CNT_H(_n) (GDM_BASE(_n) + 0x29c) 231 + #define REG_FE_GDM_TX_ETH_E64_CNT_H(_n) (GDM_BASE(_n) + 0x2b8) 232 + #define REG_FE_GDM_TX_ETH_L64_CNT_H(_n) (GDM_BASE(_n) + 0x2bc) 233 + #define REG_FE_GDM_TX_ETH_L127_CNT_H(_n) (GDM_BASE(_n) + 0x2c0) 234 + #define REG_FE_GDM_TX_ETH_L255_CNT_H(_n) (GDM_BASE(_n) + 0x2c4) 235 + #define REG_FE_GDM_TX_ETH_L511_CNT_H(_n) (GDM_BASE(_n) + 0x2c8) 236 + #define REG_FE_GDM_TX_ETH_L1023_CNT_H(_n) (GDM_BASE(_n) + 0x2cc) 237 + #define REG_FE_GDM_RX_ETH_E64_CNT_H(_n) (GDM_BASE(_n) + 0x2e8) 238 + #define REG_FE_GDM_RX_ETH_L64_CNT_H(_n) (GDM_BASE(_n) + 0x2ec) 239 + #define REG_FE_GDM_RX_ETH_L127_CNT_H(_n) (GDM_BASE(_n) + 0x2f0) 240 + #define REG_FE_GDM_RX_ETH_L255_CNT_H(_n) (GDM_BASE(_n) + 0x2f4) 241 + #define REG_FE_GDM_RX_ETH_L511_CNT_H(_n) (GDM_BASE(_n) + 0x2f8) 242 + #define REG_FE_GDM_RX_ETH_L1023_CNT_H(_n) (GDM_BASE(_n) + 0x2fc) 216 243 217 244 #define REG_PPE_GLO_CFG(_n) (((_n) ? PPE2_BASE : PPE1_BASE) + 0x200) 218 245 #define PPE_GLO_CFG_BUSY_MASK BIT(31) ··· 352 325 #define PPE_UPDMEM_REQ_MASK BIT(0) 353 326 354 327 #define REG_UPDMEM_DATA(_n) (((_n) ? PPE2_BASE : PPE1_BASE) + 0x374) 355 - 356 - #define REG_FE_GDM_TX_OK_PKT_CNT_H(_n) (GDM_BASE(_n) + 0x280) 357 - #define REG_FE_GDM_TX_OK_BYTE_CNT_H(_n) (GDM_BASE(_n) + 0x284) 358 - #define REG_FE_GDM_TX_ETH_PKT_CNT_H(_n) (GDM_BASE(_n) + 0x288) 359 - #define REG_FE_GDM_TX_ETH_BYTE_CNT_H(_n) (GDM_BASE(_n) + 0x28c) 360 - 361 - #define REG_FE_GDM_RX_OK_PKT_CNT_H(_n) (GDM_BASE(_n) + 0x290) 362 - #define REG_FE_GDM_RX_OK_BYTE_CNT_H(_n) (GDM_BASE(_n) + 0x294) 363 - #define REG_FE_GDM_RX_ETH_PKT_CNT_H(_n) (GDM_BASE(_n) + 0x298) 364 - #define REG_FE_GDM_RX_ETH_BYTE_CNT_H(_n) (GDM_BASE(_n) + 0x29c) 365 - #define REG_FE_GDM_TX_ETH_E64_CNT_H(_n) (GDM_BASE(_n) + 0x2b8) 366 - #define REG_FE_GDM_TX_ETH_L64_CNT_H(_n) (GDM_BASE(_n) + 0x2bc) 367 - #define REG_FE_GDM_TX_ETH_L127_CNT_H(_n) (GDM_BASE(_n) + 0x2c0) 368 - #define REG_FE_GDM_TX_ETH_L255_CNT_H(_n) (GDM_BASE(_n) + 0x2c4) 369 - #define REG_FE_GDM_TX_ETH_L511_CNT_H(_n) (GDM_BASE(_n) + 0x2c8) 370 - #define REG_FE_GDM_TX_ETH_L1023_CNT_H(_n) (GDM_BASE(_n) + 0x2cc) 371 - #define REG_FE_GDM_RX_ETH_E64_CNT_H(_n) (GDM_BASE(_n) + 0x2e8) 372 - #define REG_FE_GDM_RX_ETH_L64_CNT_H(_n) (GDM_BASE(_n) + 0x2ec) 373 - #define REG_FE_GDM_RX_ETH_L127_CNT_H(_n) (GDM_BASE(_n) + 0x2f0) 374 - #define REG_FE_GDM_RX_ETH_L255_CNT_H(_n) (GDM_BASE(_n) + 0x2f4) 375 - #define REG_FE_GDM_RX_ETH_L511_CNT_H(_n) (GDM_BASE(_n) + 0x2f8) 376 - #define REG_FE_GDM_RX_ETH_L1023_CNT_H(_n) (GDM_BASE(_n) + 0x2fc) 377 - 378 - #define REG_GDM2_CHN_RLS (GDM2_BASE + 0x20) 379 - #define MBI_RX_AGE_SEL_MASK GENMASK(26, 25) 380 - #define MBI_TX_AGE_SEL_MASK GENMASK(18, 17) 381 - 382 - #define REG_GDM3_FWD_CFG GDM3_BASE 383 - #define GDM3_PAD_EN_MASK BIT(28) 384 - 385 - #define REG_GDM4_FWD_CFG GDM4_BASE 386 - #define GDM4_PAD_EN_MASK BIT(28) 387 - #define GDM4_SPORT_OFFSET0_MASK GENMASK(11, 8) 388 - 389 - #define REG_GDM4_SRC_PORT_SET (GDM4_BASE + 0x23c) 390 - #define GDM4_SPORT_OFF2_MASK GENMASK(19, 16) 391 - #define GDM4_SPORT_OFF1_MASK GENMASK(15, 12) 392 - #define GDM4_SPORT_OFF0_MASK GENMASK(11, 8) 393 328 394 329 #define REG_IP_FRAG_FP 0x2010 395 330 #define IP_ASSEMBLE_PORT_MASK GENMASK(24, 21)