ARM: dts: sunxi: Move wakeup-capable IRQs to r_intc

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

All IRQs that can be used to wake up the system must be routed through
r_intc, so they are visible to firmware while the system is suspended.

In addition to the external NMI input, which is already routed through
r_intc, these include PIO and R_PIO (gpio-keys), the LRADC, and the RTC.

Acked-by: Maxime Ripard <mripard@kernel.org>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>

authored by

Samuel Holland and committed by

Chen-Yu Tsai 5 years ago 994e5818 3fb01ded

+14

4 changed files

expand all

arch

arm

boot

dts

sun6i-a31.dtsi

sun8i-a23-a33.dtsi

sun8i-a83t.dtsi

sunxi-h3-h5.dtsi

arch/arm/boot/dts/sun6i-a31.dtsi

··· 611 611 pio: pinctrl@1c20800 { 612 612 compatible = "allwinner,sun6i-a31-pinctrl"; 613 613 reg = <0x01c20800 0x400>; 614 + interrupt-parent = <&r_intc>; 614 615 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 615 616 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 616 617 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, ··· 803 802 lradc: lradc@1c22800 { 804 803 compatible = "allwinner,sun4i-a10-lradc-keys"; 805 804 reg = <0x01c22800 0x100>; 805 + interrupt-parent = <&r_intc>; 806 806 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 807 807 status = "disabled"; 808 808 }; ··· 1301 1299 #clock-cells = <1>; 1302 1300 compatible = "allwinner,sun6i-a31-rtc"; 1303 1301 reg = <0x01f00000 0x54>; 1302 + interrupt-parent = <&r_intc>; 1304 1303 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 1305 1304 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 1306 1305 clocks = <&osc32k>; ··· 1386 1383 r_pio: pinctrl@1f02c00 { 1387 1384 compatible = "allwinner,sun6i-a31-r-pinctrl"; 1388 1385 reg = <0x01f02c00 0x400>; 1386 + interrupt-parent = <&r_intc>; 1389 1387 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 1390 1388 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 1391 1389 clocks = <&apb0_gates 0>, <&osc24M>, <&rtc 0>;

arch/arm/boot/dts/sun8i-a23-a33.dtsi

··· 338 338 pio: pinctrl@1c20800 { 339 339 /* compatible gets set in SoC specific dtsi file */ 340 340 reg = <0x01c20800 0x400>; 341 + interrupt-parent = <&r_intc>; 341 342 /* interrupts get set in SoC specific dtsi file */ 342 343 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>; 343 344 clock-names = "apb", "hosc", "losc"; ··· 474 473 lradc: lradc@1c22800 { 475 474 compatible = "allwinner,sun4i-a10-lradc-keys"; 476 475 reg = <0x01c22800 0x100>; 476 + interrupt-parent = <&r_intc>; 477 477 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 478 478 status = "disabled"; 479 479 }; ··· 711 709 rtc: rtc@1f00000 { 712 710 compatible = "allwinner,sun8i-a23-rtc"; 713 711 reg = <0x01f00000 0x400>; 712 + interrupt-parent = <&r_intc>; 714 713 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 715 714 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 716 715 clock-output-names = "osc32k", "osc32k-out"; ··· 808 805 r_pio: pinctrl@1f02c00 { 809 806 compatible = "allwinner,sun8i-a23-r-pinctrl"; 810 807 reg = <0x01f02c00 0x400>; 808 + interrupt-parent = <&r_intc>; 811 809 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 812 810 clocks = <&apb0_gates 0>, <&osc24M>, <&rtc 0>; 813 811 clock-names = "apb", "hosc", "losc";

arch/arm/boot/dts/sun8i-a83t.dtsi

··· 708 708 709 709 pio: pinctrl@1c20800 { 710 710 compatible = "allwinner,sun8i-a83t-pinctrl"; 711 + interrupt-parent = <&r_intc>; 711 712 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 712 713 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 713 714 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; ··· 1148 1147 r_lradc: lradc@1f03c00 { 1149 1148 compatible = "allwinner,sun8i-a83t-r-lradc"; 1150 1149 reg = <0x01f03c00 0x100>; 1150 + interrupt-parent = <&r_intc>; 1151 1151 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 1152 1152 status = "disabled"; 1153 1153 }; ··· 1156 1154 r_pio: pinctrl@1f02c00 { 1157 1155 compatible = "allwinner,sun8i-a83t-r-pinctrl"; 1158 1156 reg = <0x01f02c00 0x400>; 1157 + interrupt-parent = <&r_intc>; 1159 1158 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1160 1159 clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, 1161 1160 <&osc16Md512>;

arch/arm/boot/dts/sunxi-h3-h5.dtsi

··· 395 395 pio: pinctrl@1c20800 { 396 396 /* compatible is in per SoC .dtsi file */ 397 397 reg = <0x01c20800 0x400>; 398 + interrupt-parent = <&r_intc>; 398 399 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 399 400 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 400 401 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>; ··· 853 852 rtc: rtc@1f00000 { 854 853 /* compatible is in per SoC .dtsi file */ 855 854 reg = <0x01f00000 0x400>; 855 + interrupt-parent = <&r_intc>; 856 856 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 857 857 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 858 858 clock-output-names = "osc32k", "osc32k-out", "iosc"; ··· 911 909 r_pio: pinctrl@1f02c00 { 912 910 compatible = "allwinner,sun8i-h3-r-pinctrl"; 913 911 reg = <0x01f02c00 0x400>; 912 + interrupt-parent = <&r_intc>; 914 913 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 915 914 clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&rtc 0>; 916 915 clock-names = "apb", "hosc", "losc";