tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
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drm/amdgpu: Use FW addr returned by PSP for VF MM

One Vega10 SR-IOV VF, the FW address returned by PSP should be
set into the init table, while not the original BO mc address.
otherwise, UVD and VCE IB test will fail under Vega10 SR-IOV

reference:
commit bfcea5204287 ("drm/amdgpu:change VEGA booting with firmware loaded by PSP")
commit aa5873dca463 ("drm/amdgpu: Change VCE booting with firmware loaded by PSP")

Signed-off-by: Trigger Huang <Trigger.Huang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Trigger Huang and committed by
Alex Deucher 992fbe8c 570c91d5

+21 -12
+10 -6
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
··· 787 787 0xFFFFFFFF, 0x00000004); 788 788 /* mc resume*/ 789 789 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 790 - MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 791 - lower_32_bits(adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].mc_addr)); 792 - MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 793 - upper_32_bits(adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].mc_addr)); 790 + MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, 791 + mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 792 + adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].tmr_mc_addr_lo); 793 + MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, 794 + mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 795 + adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].tmr_mc_addr_hi); 796 + MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0); 794 797 offset = 0; 795 798 } else { 796 799 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), ··· 801 798 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 802 799 upper_32_bits(adev->uvd.inst[i].gpu_addr)); 803 800 offset = size; 801 + MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 802 + AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 803 + 804 804 } 805 805 806 - MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET0), 807 - AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 808 806 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE0), size); 809 807 810 808 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
+11 -6
drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
··· 244 244 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_SWAP_CNTL1), 0); 245 245 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VM_CTRL), 0); 246 246 247 + offset = AMDGPU_VCE_FIRMWARE_OFFSET; 247 248 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 249 + uint32_t low = adev->firmware.ucode[AMDGPU_UCODE_ID_VCE].tmr_mc_addr_lo; 250 + uint32_t hi = adev->firmware.ucode[AMDGPU_UCODE_ID_VCE].tmr_mc_addr_hi; 251 + uint64_t tmr_mc_addr = (uint64_t)(hi) << 32 | low; 252 + 248 253 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, 249 - mmVCE_LMI_VCPU_CACHE_40BIT_BAR0), 250 - adev->firmware.ucode[AMDGPU_UCODE_ID_VCE].mc_addr >> 8); 254 + mmVCE_LMI_VCPU_CACHE_40BIT_BAR0), tmr_mc_addr >> 8); 251 255 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, 252 256 mmVCE_LMI_VCPU_CACHE_64BIT_BAR0), 253 - (adev->firmware.ucode[AMDGPU_UCODE_ID_VCE].mc_addr >> 40) & 0xff); 257 + (tmr_mc_addr >> 40) & 0xff); 258 + MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET0), 0); 254 259 } else { 255 260 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, 256 261 mmVCE_LMI_VCPU_CACHE_40BIT_BAR0), ··· 263 258 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, 264 259 mmVCE_LMI_VCPU_CACHE_64BIT_BAR0), 265 260 (adev->vce.gpu_addr >> 40) & 0xff); 261 + MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET0), 262 + offset & ~0x0f000000); 263 + 266 264 } 267 265 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, 268 266 mmVCE_LMI_VCPU_CACHE_40BIT_BAR1), ··· 280 272 mmVCE_LMI_VCPU_CACHE_64BIT_BAR2), 281 273 (adev->vce.gpu_addr >> 40) & 0xff); 282 274 283 - offset = AMDGPU_VCE_FIRMWARE_OFFSET; 284 275 size = VCE_V4_0_FW_SIZE; 285 - MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET0), 286 - offset & ~0x0f000000); 287 276 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_SIZE0), size); 288 277 289 278 offset = (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) ? offset + size : 0;