tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
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drm/amd/display: log additional register state for debug

[Why & How]
Extend existing state collection functions to add some additional
registers useful for debug, and add state collection function for DC
hubbub

Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Josip Pavic <Josip.Pavic@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Josip Pavic and committed by
Alex Deucher 98e95e4f 97b9c006

+175 -18
+17 -1
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
··· 121 121 uint32_t DCN_VM_AGP_BASE; 122 122 uint32_t DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB; 123 123 uint32_t DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB; 124 + uint32_t DCN_VM_FAULT_ADDR_MSB; 125 + uint32_t DCN_VM_FAULT_ADDR_LSB; 126 + uint32_t DCN_VM_FAULT_CNTL; 127 + uint32_t DCN_VM_FAULT_STATUS; 124 128 uint32_t DCHUBBUB_ARB_FRAC_URG_BW_NOM_A; 125 129 uint32_t DCHUBBUB_ARB_FRAC_URG_BW_NOM_B; 126 130 uint32_t DCHUBBUB_ARB_FRAC_URG_BW_NOM_C; ··· 237 233 type DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C;\ 238 234 type DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D;\ 239 235 type DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB;\ 240 - type DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB 236 + type DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB;\ 237 + type DCN_VM_FAULT_ADDR_MSB;\ 238 + type DCN_VM_FAULT_ADDR_LSB;\ 239 + type DCN_VM_ERROR_STATUS_CLEAR;\ 240 + type DCN_VM_ERROR_STATUS_MODE;\ 241 + type DCN_VM_ERROR_INTERRUPT_ENABLE;\ 242 + type DCN_VM_RANGE_FAULT_DISABLE;\ 243 + type DCN_VM_PRQ_FAULT_DISABLE;\ 244 + type DCN_VM_ERROR_STATUS;\ 245 + type DCN_VM_ERROR_VMID;\ 246 + type DCN_VM_ERROR_TABLE_LEVEL;\ 247 + type DCN_VM_ERROR_PIPE;\ 248 + type DCN_VM_ERROR_INTERRUPT_STATUS 241 249 242 250 #define HUBBUB_STUTTER_REG_FIELD_LIST(type) \ 243 251 type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A;\
+29
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
··· 871 871 struct _vcs_dpi_display_dlg_regs_st *dlg_attr = &s->dlg_attr; 872 872 struct _vcs_dpi_display_ttu_regs_st *ttu_attr = &s->ttu_attr; 873 873 struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs; 874 + uint32_t aperture_low_msb, aperture_low_lsb; 875 + uint32_t aperture_high_msb, aperture_high_lsb; 874 876 875 877 /* Requester */ 876 878 REG_GET(HUBPRET_CONTROL, ··· 882 880 PRQ_EXPANSION_MODE, &rq_regs->prq_expansion_mode, 883 881 MRQ_EXPANSION_MODE, &rq_regs->mrq_expansion_mode, 884 882 CRQ_EXPANSION_MODE, &rq_regs->crq_expansion_mode); 883 + 884 + REG_GET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, 885 + MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, &aperture_low_msb); 886 + 887 + REG_GET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, 888 + MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, &aperture_low_lsb); 889 + 890 + REG_GET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, 891 + MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, &aperture_high_msb); 892 + 893 + REG_GET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, 894 + MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, &aperture_high_lsb); 895 + 896 + // On DCN1, aperture is broken down into MSB and LSB; only keep bits [47:18] to match later DCN format 897 + rq_regs->aperture_low_addr = (aperture_low_msb << 26) | (aperture_low_lsb >> 6); 898 + rq_regs->aperture_high_addr = (aperture_high_msb << 26) | (aperture_high_lsb >> 6); 885 899 886 900 /* DLG - Per hubp */ 887 901 REG_GET_2(BLANK_OFFSET_0, ··· 1055 1037 QoS_LEVEL_LOW_WM, &s->qos_level_low_wm, 1056 1038 QoS_LEVEL_HIGH_WM, &s->qos_level_high_wm); 1057 1039 1040 + REG_GET(DCSURF_PRIMARY_SURFACE_ADDRESS, 1041 + PRIMARY_SURFACE_ADDRESS, &s->primary_surface_addr_lo); 1042 + 1043 + REG_GET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 1044 + PRIMARY_SURFACE_ADDRESS, &s->primary_surface_addr_hi); 1045 + 1046 + REG_GET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 1047 + PRIMARY_META_SURFACE_ADDRESS, &s->primary_meta_addr_lo); 1048 + 1049 + REG_GET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 1050 + PRIMARY_META_SURFACE_ADDRESS, &s->primary_meta_addr_hi); 1058 1051 } 1059 1052 1060 1053 void hubp1_read_state(struct hubp *hubp)
+4
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
··· 682 682 uint32_t min_ttu_vblank; 683 683 uint32_t qos_level_low_wm; 684 684 uint32_t qos_level_high_wm; 685 + uint32_t primary_surface_addr_lo; 686 + uint32_t primary_surface_addr_hi; 687 + uint32_t primary_meta_addr_lo; 688 + uint32_t primary_meta_addr_hi; 685 689 }; 686 690 687 691 struct dcn10_hubp {
+6
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
··· 1388 1388 1389 1389 REG_GET(OPTC_INPUT_GLOBAL_CONTROL, 1390 1390 OPTC_UNDERFLOW_OCCURRED_STATUS, &s->underflow_occurred_status); 1391 + 1392 + REG_GET(OTG_VERTICAL_INTERRUPT2_CONTROL, 1393 + OTG_VERTICAL_INTERRUPT2_INT_ENABLE, &s->vertical_interrupt2_en); 1394 + 1395 + REG_GET(OTG_VERTICAL_INTERRUPT2_POSITION, 1396 + OTG_VERTICAL_INTERRUPT2_LINE_START, &s->vertical_interrupt2_line); 1391 1397 } 1392 1398 1393 1399 bool optc1_get_otg_active_size(struct timing_generator *optc,
+2
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
··· 578 578 uint32_t underflow_occurred_status; 579 579 uint32_t otg_enabled; 580 580 uint32_t blank_enabled; 581 + uint32_t vertical_interrupt2_en; 582 + uint32_t vertical_interrupt2_line; 581 583 }; 582 584 583 585 void optc1_read_otg_state(struct optc *optc1,
+21
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c
··· 605 605 return wm_pending; 606 606 } 607 607 608 + void hubbub2_read_state(struct hubbub *hubbub, struct dcn_hubbub_state *hubbub_state) 609 + { 610 + struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub); 611 + 612 + if (REG(DCN_VM_FAULT_ADDR_MSB)) 613 + hubbub_state->vm_fault_addr_msb = REG_READ(DCN_VM_FAULT_ADDR_MSB); 614 + 615 + if (REG(DCN_VM_FAULT_ADDR_LSB)) 616 + hubbub_state->vm_fault_addr_msb = REG_READ(DCN_VM_FAULT_ADDR_LSB); 617 + 618 + if (REG(DCN_VM_FAULT_CNTL)) 619 + REG_GET(DCN_VM_FAULT_CNTL, DCN_VM_ERROR_STATUS_MODE, &hubbub_state->vm_error_mode); 620 + 621 + if (REG(DCN_VM_FAULT_STATUS)) { 622 + REG_GET(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_STATUS, &hubbub_state->vm_error_status); 623 + REG_GET(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_VMID, &hubbub_state->vm_error_vmid); 624 + REG_GET(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_PIPE, &hubbub_state->vm_error_pipe); 625 + } 626 + } 627 + 608 628 static const struct hubbub_funcs hubbub2_funcs = { 609 629 .update_dchub = hubbub2_update_dchub, 610 630 .init_dchub_sys_ctx = hubbub2_init_dchub_sys_ctx, ··· 637 617 .program_watermarks = hubbub2_program_watermarks, 638 618 .is_allow_self_refresh_enabled = hubbub1_is_allow_self_refresh_enabled, 639 619 .allow_self_refresh_control = hubbub1_allow_self_refresh_control, 620 + .hubbub_read_state = hubbub2_read_state, 640 621 }; 641 622 642 623 void hubbub2_construct(struct dcn20_hubbub *hubbub,
+21 -12
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h
··· 29 29 #include "dcn10/dcn10_hubbub.h" 30 30 #include "dcn20_vmid.h" 31 31 32 - #define HUBBUB_REG_LIST_DCN20_COMMON()\ 33 - HUBBUB_REG_LIST_DCN_COMMON(), \ 34 - SR(DCHUBBUB_CRC_CTRL), \ 35 - SR(DCN_VM_FB_LOCATION_BASE),\ 36 - SR(DCN_VM_FB_LOCATION_TOP),\ 37 - SR(DCN_VM_FB_OFFSET),\ 38 - SR(DCN_VM_AGP_BOT),\ 39 - SR(DCN_VM_AGP_TOP),\ 40 - SR(DCN_VM_AGP_BASE) 41 - 42 32 #define TO_DCN20_HUBBUB(hubbub)\ 43 33 container_of(hubbub, struct dcn20_hubbub, base) 44 34 ··· 40 50 SR(DCN_VM_FB_OFFSET),\ 41 51 SR(DCN_VM_AGP_BOT),\ 42 52 SR(DCN_VM_AGP_TOP),\ 43 - SR(DCN_VM_AGP_BASE) 53 + SR(DCN_VM_AGP_BASE),\ 54 + SR(DCN_VM_FAULT_ADDR_MSB), \ 55 + SR(DCN_VM_FAULT_ADDR_LSB), \ 56 + SR(DCN_VM_FAULT_CNTL), \ 57 + SR(DCN_VM_FAULT_STATUS) 44 58 45 59 #define HUBBUB_REG_LIST_DCN20(id)\ 46 60 HUBBUB_REG_LIST_DCN20_COMMON(), \ ··· 65 71 HUBBUB_SF(DCN_VM_AGP_TOP, AGP_TOP, mask_sh), \ 66 72 HUBBUB_SF(DCN_VM_AGP_BASE, AGP_BASE, mask_sh), \ 67 73 HUBBUB_SF(DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB, DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB, mask_sh), \ 68 - HUBBUB_SF(DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB, DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB, mask_sh) 74 + HUBBUB_SF(DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB, DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB, mask_sh), \ 75 + HUBBUB_SF(DCN_VM_FAULT_ADDR_MSB, DCN_VM_FAULT_ADDR_MSB, mask_sh), \ 76 + HUBBUB_SF(DCN_VM_FAULT_ADDR_LSB, DCN_VM_FAULT_ADDR_LSB, mask_sh), \ 77 + HUBBUB_SF(DCN_VM_FAULT_CNTL, DCN_VM_ERROR_STATUS_CLEAR, mask_sh), \ 78 + HUBBUB_SF(DCN_VM_FAULT_CNTL, DCN_VM_ERROR_STATUS_MODE, mask_sh), \ 79 + HUBBUB_SF(DCN_VM_FAULT_CNTL, DCN_VM_ERROR_INTERRUPT_ENABLE, mask_sh), \ 80 + HUBBUB_SF(DCN_VM_FAULT_CNTL, DCN_VM_RANGE_FAULT_DISABLE, mask_sh), \ 81 + HUBBUB_SF(DCN_VM_FAULT_CNTL, DCN_VM_PRQ_FAULT_DISABLE, mask_sh), \ 82 + HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_STATUS, mask_sh), \ 83 + HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_VMID, mask_sh), \ 84 + HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_TABLE_LEVEL, mask_sh), \ 85 + HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_PIPE, mask_sh), \ 86 + HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_INTERRUPT_STATUS, mask_sh) 69 87 70 88 struct dcn20_hubbub { 71 89 struct hubbub base; ··· 136 130 137 131 void hubbub2_wm_read_state(struct hubbub *hubbub, 138 132 struct dcn_hubbub_wm *wm); 133 + 134 + void hubbub2_read_state(struct hubbub *hubbub, 135 + struct dcn_hubbub_state *hubbub_state); 139 136 140 137 #endif
+17
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
··· 1080 1080 MRQ_EXPANSION_MODE, &rq_regs->mrq_expansion_mode, 1081 1081 CRQ_EXPANSION_MODE, &rq_regs->crq_expansion_mode); 1082 1082 1083 + REG_GET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, 1084 + MC_VM_SYSTEM_APERTURE_HIGH_ADDR, &rq_regs->aperture_high_addr); 1085 + 1086 + REG_GET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, 1087 + MC_VM_SYSTEM_APERTURE_LOW_ADDR, &rq_regs->aperture_low_addr); 1088 + 1083 1089 /* DLG - Per hubp */ 1084 1090 REG_GET_2(BLANK_OFFSET_0, 1085 1091 REFCYC_H_BLANK_END, &dlg_attr->refcyc_h_blank_end, ··· 1242 1236 QoS_LEVEL_LOW_WM, &s->qos_level_low_wm, 1243 1237 QoS_LEVEL_HIGH_WM, &s->qos_level_high_wm); 1244 1238 1239 + REG_GET(DCSURF_PRIMARY_SURFACE_ADDRESS, 1240 + PRIMARY_SURFACE_ADDRESS, &s->primary_surface_addr_lo); 1241 + 1242 + REG_GET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 1243 + PRIMARY_SURFACE_ADDRESS, &s->primary_surface_addr_hi); 1244 + 1245 + REG_GET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 1246 + PRIMARY_META_SURFACE_ADDRESS, &s->primary_meta_addr_lo); 1247 + 1248 + REG_GET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 1249 + PRIMARY_META_SURFACE_ADDRESS, &s->primary_meta_addr_hi); 1245 1250 } 1246 1251 1247 1252 void hubp2_read_state(struct hubp *hubp)
+1
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
··· 701 701 .program_watermarks = hubbub21_program_watermarks, 702 702 .allow_self_refresh_control = hubbub1_allow_self_refresh_control, 703 703 .apply_DEDCN21_147_wa = hubbub21_apply_DEDCN21_147_wa, 704 + .hubbub_read_state = hubbub2_read_state, 704 705 }; 705 706 706 707 void hubbub21_construct(struct dcn20_hubbub *hubbub,
+13 -1
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h
··· 108 108 HUBBUB_SF(DCN_VM_FB_OFFSET, FB_OFFSET, mask_sh), \ 109 109 HUBBUB_SF(DCN_VM_AGP_BOT, AGP_BOT, mask_sh), \ 110 110 HUBBUB_SF(DCN_VM_AGP_TOP, AGP_TOP, mask_sh), \ 111 - HUBBUB_SF(DCN_VM_AGP_BASE, AGP_BASE, mask_sh) 111 + HUBBUB_SF(DCN_VM_AGP_BASE, AGP_BASE, mask_sh), \ 112 + HUBBUB_SF(DCN_VM_FAULT_ADDR_MSB, DCN_VM_FAULT_ADDR_MSB, mask_sh), \ 113 + HUBBUB_SF(DCN_VM_FAULT_ADDR_LSB, DCN_VM_FAULT_ADDR_LSB, mask_sh), \ 114 + HUBBUB_SF(DCN_VM_FAULT_CNTL, DCN_VM_ERROR_STATUS_CLEAR, mask_sh), \ 115 + HUBBUB_SF(DCN_VM_FAULT_CNTL, DCN_VM_ERROR_STATUS_MODE, mask_sh), \ 116 + HUBBUB_SF(DCN_VM_FAULT_CNTL, DCN_VM_ERROR_INTERRUPT_ENABLE, mask_sh), \ 117 + HUBBUB_SF(DCN_VM_FAULT_CNTL, DCN_VM_RANGE_FAULT_DISABLE, mask_sh), \ 118 + HUBBUB_SF(DCN_VM_FAULT_CNTL, DCN_VM_PRQ_FAULT_DISABLE, mask_sh), \ 119 + HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_STATUS, mask_sh), \ 120 + HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_VMID, mask_sh), \ 121 + HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_TABLE_LEVEL, mask_sh), \ 122 + HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_PIPE, mask_sh), \ 123 + HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_INTERRUPT_STATUS, mask_sh) 112 124 113 125 void dcn21_dchvm_init(struct hubbub *hubbub); 114 126 int hubbub21_init_dchub(struct hubbub *hubbub,
+1 -1
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c
··· 833 833 .dmdata_set_attributes = hubp2_dmdata_set_attributes, 834 834 .dmdata_load = hubp2_dmdata_load, 835 835 .dmdata_status_done = hubp2_dmdata_status_done, 836 - .hubp_read_state = hubp1_read_state, 836 + .hubp_read_state = hubp2_read_state, 837 837 .hubp_clear_underflow = hubp1_clear_underflow, 838 838 .hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl, 839 839 .hubp_init = hubp21_init,
+1
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubbub.c
··· 451 451 .force_wm_propagate_to_pipes = hubbub3_force_wm_propagate_to_pipes, 452 452 .force_pstate_change_control = hubbub3_force_pstate_change_control, 453 453 .init_watermarks = hubbub3_init_watermarks, 454 + .hubbub_read_state = hubbub2_read_state, 454 455 }; 455 456 456 457 void hubbub3_construct(struct dcn20_hubbub *hubbub3,
+13 -1
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubbub.h
··· 87 87 HUBBUB_SF(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, mask_sh), \ 88 88 HUBBUB_SF(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, mask_sh), \ 89 89 HUBBUB_SF(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, mask_sh), \ 90 - HUBBUB_SF(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, mask_sh) 90 + HUBBUB_SF(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, mask_sh), \ 91 + HUBBUB_SF(DCN_VM_FAULT_ADDR_MSB, DCN_VM_FAULT_ADDR_MSB, mask_sh), \ 92 + HUBBUB_SF(DCN_VM_FAULT_ADDR_LSB, DCN_VM_FAULT_ADDR_LSB, mask_sh), \ 93 + HUBBUB_SF(DCN_VM_FAULT_CNTL, DCN_VM_ERROR_STATUS_CLEAR, mask_sh), \ 94 + HUBBUB_SF(DCN_VM_FAULT_CNTL, DCN_VM_ERROR_STATUS_MODE, mask_sh), \ 95 + HUBBUB_SF(DCN_VM_FAULT_CNTL, DCN_VM_ERROR_INTERRUPT_ENABLE, mask_sh), \ 96 + HUBBUB_SF(DCN_VM_FAULT_CNTL, DCN_VM_RANGE_FAULT_DISABLE, mask_sh), \ 97 + HUBBUB_SF(DCN_VM_FAULT_CNTL, DCN_VM_PRQ_FAULT_DISABLE, mask_sh), \ 98 + HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_STATUS, mask_sh), \ 99 + HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_VMID, mask_sh), \ 100 + HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_TABLE_LEVEL, mask_sh), \ 101 + HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_PIPE, mask_sh), \ 102 + HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_INTERRUPT_STATUS, mask_sh) 91 103 92 104 void hubbub3_construct(struct dcn20_hubbub *hubbub3, 93 105 struct dc_context *ctx,
+1
drivers/gpu/drm/amd/display/dc/dcn301/dcn301_hubbub.c
··· 62 62 .is_allow_self_refresh_enabled = hubbub1_is_allow_self_refresh_enabled, 63 63 .force_wm_propagate_to_pipes = hubbub3_force_wm_propagate_to_pipes, 64 64 .force_pstate_change_control = hubbub3_force_pstate_change_control, 65 + .hubbub_read_state = hubbub2_read_state, 65 66 }; 66 67 67 68 void hubbub301_construct(struct dcn20_hubbub *hubbub3,
+2 -1
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubbub.c
··· 934 934 .is_allow_self_refresh_enabled = hubbub1_is_allow_self_refresh_enabled, 935 935 .program_det_size = dcn31_program_det_size, 936 936 .program_compbuf_size = dcn31_program_compbuf_size, 937 - .init_crb = dcn31_init_crb 937 + .init_crb = dcn31_init_crb, 938 + .hubbub_read_state = hubbub2_read_state, 938 939 }; 939 940 940 941 void hubbub31_construct(struct dcn20_hubbub *hubbub31,
+13 -1
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubbub.h
··· 107 107 HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A, mask_sh), \ 108 108 HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B, mask_sh), \ 109 109 HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C, mask_sh), \ 110 - HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D, mask_sh) 110 + HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D, mask_sh), \ 111 + HUBBUB_SF(DCN_VM_FAULT_ADDR_MSB, DCN_VM_FAULT_ADDR_MSB, mask_sh), \ 112 + HUBBUB_SF(DCN_VM_FAULT_ADDR_LSB, DCN_VM_FAULT_ADDR_LSB, mask_sh), \ 113 + HUBBUB_SF(DCN_VM_FAULT_CNTL, DCN_VM_ERROR_STATUS_CLEAR, mask_sh), \ 114 + HUBBUB_SF(DCN_VM_FAULT_CNTL, DCN_VM_ERROR_STATUS_MODE, mask_sh), \ 115 + HUBBUB_SF(DCN_VM_FAULT_CNTL, DCN_VM_ERROR_INTERRUPT_ENABLE, mask_sh), \ 116 + HUBBUB_SF(DCN_VM_FAULT_CNTL, DCN_VM_RANGE_FAULT_DISABLE, mask_sh), \ 117 + HUBBUB_SF(DCN_VM_FAULT_CNTL, DCN_VM_PRQ_FAULT_DISABLE, mask_sh), \ 118 + HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_STATUS, mask_sh), \ 119 + HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_VMID, mask_sh), \ 120 + HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_TABLE_LEVEL, mask_sh), \ 121 + HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_PIPE, mask_sh), \ 122 + HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_INTERRUPT_STATUS, mask_sh) 111 123 112 124 113 125 void hubbub31_construct(struct dcn20_hubbub *hubbub3,
+2
drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
··· 536 536 unsigned int mrq_expansion_mode; 537 537 unsigned int crq_expansion_mode; 538 538 unsigned int plane1_base_address; 539 + unsigned int aperture_low_addr; // bits [47:18] 540 + unsigned int aperture_high_addr; // bits [47:18] 539 541 }; 540 542 541 543 struct _vcs_dpi_display_dlg_sys_params_st {
+11
drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
··· 102 102 } default_addrs; 103 103 }; 104 104 105 + struct dcn_hubbub_state { 106 + uint32_t vm_fault_addr_msb; 107 + uint32_t vm_fault_addr_lsb; 108 + uint32_t vm_error_status; 109 + uint32_t vm_error_vmid; 110 + uint32_t vm_error_pipe; 111 + uint32_t vm_error_mode; 112 + }; 113 + 105 114 struct hubbub_funcs { 106 115 void (*update_dchub)( 107 116 struct hubbub *hubbub, ··· 157 148 void (*apply_DEDCN21_147_wa)(struct hubbub *hubbub); 158 149 159 150 void (*force_wm_propagate_to_pipes)(struct hubbub *hubbub); 151 + 152 + void (*hubbub_read_state)(struct hubbub *hubbub, struct dcn_hubbub_state *hubbub_state); 160 153 161 154 void (*force_pstate_change_control)(struct hubbub *hubbub, bool force, bool allow); 162 155