tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

Merge tag 'perf_urgent_for_v5.14' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull perf fixes from Borislav Petkov:

- Prevent the amd/power module from being removed while in use

- Mark AMD IBS as not supporting content exclusion

- Add a workaround for AMD erratum #1197 where IBS registers might not
be restored properly after exiting CC6 state

- Fix a potential truncation of a 32-bit variable due to shifting

- Read the correct bits describing the number of configurable address
ranges on Intel PT

* tag 'perf_urgent_for_v5.14' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
perf/x86/amd/power: Assign pmu.module
perf/x86/amd/ibs: Extend PERF_PMU_CAP_NO_EXCLUDE to IBS Op
perf/x86/amd/ibs: Work around erratum #1197
perf/x86/intel/uncore: Fix integer overflow on 23 bit left shift of a u32
perf/x86/intel/pt: Fix mask of num_address_ranges

Linus Torvalds 98d006eb 072a2767

options
unified split
Changed files
+12 -2
arch
x86
events
amd
ibs.c
power.c
intel
pt.c
uncore_snbep.c
+9
arch/x86/events/amd/ibs.c
··· 90 90 unsigned long offset_mask[1]; 91 91 int offset_max; 92 92 unsigned int fetch_count_reset_broken : 1; 93 + unsigned int fetch_ignore_if_zero_rip : 1; 93 94 struct cpu_perf_ibs __percpu *pcpu; 94 95 95 96 struct attribute **format_attrs; ··· 571 570 .start = perf_ibs_start, 572 571 .stop = perf_ibs_stop, 573 572 .read = perf_ibs_read, 573 + .capabilities = PERF_PMU_CAP_NO_EXCLUDE, 574 574 }, 575 575 .msr = MSR_AMD64_IBSOPCTL, 576 576 .config_mask = IBS_OP_CONFIG_MASK, ··· 674 672 if (check_rip && (ibs_data.regs[2] & IBS_RIP_INVALID)) { 675 673 regs.flags &= ~PERF_EFLAGS_EXACT; 676 674 } else { 675 + /* Workaround for erratum #1197 */ 676 + if (perf_ibs->fetch_ignore_if_zero_rip && !(ibs_data.regs[1])) 677 + goto out; 678 + 677 679 set_linear_ip(&regs, ibs_data.regs[1]); 678 680 regs.flags |= PERF_EFLAGS_EXACT; 679 681 } ··· 774 768 */ 775 769 if (boot_cpu_data.x86 >= 0x16 && boot_cpu_data.x86 <= 0x18) 776 770 perf_ibs_fetch.fetch_count_reset_broken = 1; 771 + 772 + if (boot_cpu_data.x86 == 0x19 && boot_cpu_data.x86_model < 0x10) 773 + perf_ibs_fetch.fetch_ignore_if_zero_rip = 1; 777 774 778 775 perf_ibs_pmu_init(&perf_ibs_fetch, "ibs_fetch"); 779 776
+1
arch/x86/events/amd/power.c
··· 213 213 .stop = pmu_event_stop, 214 214 .read = pmu_event_read, 215 215 .capabilities = PERF_PMU_CAP_NO_EXCLUDE, 216 + .module = THIS_MODULE, 216 217 }; 217 218 218 219 static int power_cpu_exit(unsigned int cpu)
+1 -1
arch/x86/events/intel/pt.c
··· 62 62 PT_CAP(single_range_output, 0, CPUID_ECX, BIT(2)), 63 63 PT_CAP(output_subsys, 0, CPUID_ECX, BIT(3)), 64 64 PT_CAP(payloads_lip, 0, CPUID_ECX, BIT(31)), 65 - PT_CAP(num_address_ranges, 1, CPUID_EAX, 0x3), 65 + PT_CAP(num_address_ranges, 1, CPUID_EAX, 0x7), 66 66 PT_CAP(mtc_periods, 1, CPUID_EAX, 0xffff0000), 67 67 PT_CAP(cycle_thresholds, 1, CPUID_EBX, 0xffff), 68 68 PT_CAP(psb_periods, 1, CPUID_EBX, 0xffff0000),
+1 -1
arch/x86/events/intel/uncore_snbep.c
··· 4811 4811 return; 4812 4812 4813 4813 pci_read_config_dword(pdev, SNR_IMC_MMIO_BASE_OFFSET, &pci_dword); 4814 - addr = (pci_dword & SNR_IMC_MMIO_BASE_MASK) << 23; 4814 + addr = ((resource_size_t)pci_dword & SNR_IMC_MMIO_BASE_MASK) << 23; 4815 4815 4816 4816 pci_read_config_dword(pdev, mem_offset, &pci_dword); 4817 4817 addr |= (pci_dword & SNR_IMC_MMIO_MEM0_MASK) << 12;