tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amdgpu: add mmhub v3_0 ip block
Add support for mmhub v3.0
Signed-off-by: Tianci.Yin <tianci.yin@amd.com>
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Tianci.Yin
and committed by
Alex Deucher
98a0f868
9f99d983
+607
-1
+1
-1
drivers/gpu/drm/amd/amdgpu/Makefile
+1
-1
drivers/gpu/drm/amd/amdgpu/Makefile
+1
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+1
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+1
drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h
+1
drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h
···
27
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struct amdgpu_mmhub_funcs {
29
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u64 (*get_fb_location)(struct amdgpu_device *adev);
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+
u64 (*get_mc_fb_offset)(struct amdgpu_device *adev);
30
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void (*init)(struct amdgpu_device *adev);
31
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int (*gart_enable)(struct amdgpu_device *adev);
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void (*set_fault_enable_default)(struct amdgpu_device *adev,
+576
drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c
+576
drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c
···
1
+
/*
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* Copyright 2021 Advanced Micro Devices, Inc.
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+
*
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* Permission is hereby granted, free of charge, to any person obtaining a
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+
* copy of this software and associated documentation files (the "Software"),
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+
* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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+
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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+
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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+
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#include "amdgpu.h"
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#include "mmhub_v3_0.h"
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+
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#include "mmhub/mmhub_3_0_0_offset.h"
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#include "mmhub/mmhub_3_0_0_sh_mask.h"
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#include "navi10_enum.h"
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+
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#include "soc15_common.h"
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+
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#define regMMVM_L2_CNTL3_DEFAULT 0x80100007
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#define regMMVM_L2_CNTL4_DEFAULT 0x000000c1
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#define regMMVM_L2_CNTL5_DEFAULT 0x00003fe0
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+
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static const char *mmhub_client_ids_v3_0_0[][2] = {
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[0][0] = "VMC",
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[4][0] = "DCEDMC",
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[5][0] = "DCEVGA",
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[6][0] = "MP0",
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[7][0] = "MP1",
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[8][0] = "MPIO",
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[16][0] = "HDP",
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[17][0] = "LSDMA",
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[18][0] = "JPEG",
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[19][0] = "VCNU0",
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[21][0] = "VSCH",
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[22][0] = "VCNU1",
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[23][0] = "VCN1",
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[32+20][0] = "VCN0",
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[2][1] = "DBGUNBIO",
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[3][1] = "DCEDWB",
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[4][1] = "DCEDMC",
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[5][1] = "DCEVGA",
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[6][1] = "MP0",
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[7][1] = "MP1",
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[8][1] = "MPIO",
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[10][1] = "DBGU0",
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[11][1] = "DBGU1",
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[12][1] = "DBGU2",
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[13][1] = "DBGU3",
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[14][1] = "XDP",
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[15][1] = "OSSSYS",
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[16][1] = "HDP",
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[17][1] = "LSDMA",
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[18][1] = "JPEG",
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[19][1] = "VCNU0",
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[20][1] = "VCN0",
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[21][1] = "VSCH",
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[22][1] = "VCNU1",
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[23][1] = "VCN1",
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};
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+
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static uint32_t mmhub_v3_0_get_invalidate_req(unsigned int vmid,
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+
uint32_t flush_type)
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+
{
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u32 req = 0;
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+
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/* invalidate using legacy mode on vmid*/
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req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ,
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PER_VMID_INVALIDATE_REQ, 1 << vmid);
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req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);
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req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
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req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
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req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
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req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
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req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
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req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ,
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CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
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+
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return req;
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}
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+
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static void
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mmhub_v3_0_print_l2_protection_fault_status(struct amdgpu_device *adev,
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uint32_t status)
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+
{
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uint32_t cid, rw;
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const char *mmhub_cid = NULL;
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cid = REG_GET_FIELD(status,
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MMVM_L2_PROTECTION_FAULT_STATUS, CID);
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rw = REG_GET_FIELD(status,
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MMVM_L2_PROTECTION_FAULT_STATUS, RW);
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+
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dev_err(adev->dev,
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"MMVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
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status);
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switch (adev->ip_versions[MMHUB_HWIP][0]) {
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case IP_VERSION(3, 0, 0):
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mmhub_cid = mmhub_client_ids_v3_0_0[cid][rw];
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break;
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default:
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mmhub_cid = NULL;
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break;
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}
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dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n",
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mmhub_cid ? mmhub_cid : "unknown", cid);
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dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",
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REG_GET_FIELD(status,
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MMVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS));
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dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n",
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REG_GET_FIELD(status,
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MMVM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR));
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dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n",
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REG_GET_FIELD(status,
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MMVM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS));
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dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n",
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REG_GET_FIELD(status,
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MMVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR));
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dev_err(adev->dev, "\t RW: 0x%x\n", rw);
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}
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+
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static void mmhub_v3_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
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uint64_t page_table_base)
137
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{
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struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
139
+
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WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
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hub->ctx_addr_distance * vmid,
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lower_32_bits(page_table_base));
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+
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WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
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hub->ctx_addr_distance * vmid,
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upper_32_bits(page_table_base));
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}
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+
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static void mmhub_v3_0_init_gart_aperture_regs(struct amdgpu_device *adev)
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{
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uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
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+
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mmhub_v3_0_setup_vm_pt_regs(adev, 0, pt_base);
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+
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WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
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(u32)(adev->gmc.gart_start >> 12));
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WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
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(u32)(adev->gmc.gart_start >> 44));
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+
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WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
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(u32)(adev->gmc.gart_end >> 12));
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WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
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(u32)(adev->gmc.gart_end >> 44));
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}
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+
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static void mmhub_v3_0_init_system_aperture_regs(struct amdgpu_device *adev)
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{
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uint64_t value;
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uint32_t tmp;
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+
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/* Disable AGP. */
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WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BASE, 0);
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WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP, 0);
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WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT, 0x00FFFFFF);
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+
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if (!amdgpu_sriov_vf(adev)) {
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/*
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* the new L1 policy will block SRIOV guest from writing
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* these regs, and they will be programed at host.
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* so skip programing these regs.
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*/
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/* Program the system aperture low logical page number. */
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WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR,
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adev->gmc.vram_start >> 18);
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WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
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adev->gmc.vram_end >> 18);
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}
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+
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/* Set default page address. */
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value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start +
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adev->vm_manager.vram_base_offset;
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WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
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(u32)(value >> 12));
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WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
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(u32)(value >> 44));
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+
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/* Program "protection fault". */
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WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
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(u32)(adev->dummy_page_addr >> 12));
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WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
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(u32)((u64)adev->dummy_page_addr >> 44));
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+
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tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2);
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tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2,
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ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
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WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2, tmp);
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+
}
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+
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static void mmhub_v3_0_init_tlb_regs(struct amdgpu_device *adev)
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{
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uint32_t tmp;
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+
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/* Setup TLB control */
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tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL);
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+
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tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
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tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
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+
tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
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ENABLE_ADVANCED_DRIVER_MODEL, 1);
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tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
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SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
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tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
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tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
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MTYPE, MTYPE_UC); /* UC, uncached */
225
+
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WREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL, tmp);
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}
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+
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static void mmhub_v3_0_init_cache_regs(struct amdgpu_device *adev)
230
+
{
231
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uint32_t tmp;
232
+
233
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/* These registers are not accessible to VF-SRIOV.
234
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* The PF will program them instead.
235
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*/
236
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if (amdgpu_sriov_vf(adev))
237
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return;
238
+
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/* Setup L2 cache */
240
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tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL);
241
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tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1);
242
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tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);
243
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tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL,
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ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
245
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/* XXX for emulation, Refer to closed source code.*/
246
+
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
247
+
0);
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tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
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tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
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+
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
251
+
WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL, tmp);
252
+
253
+
tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2);
254
+
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
255
+
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
256
+
WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2, tmp);
257
+
258
+
tmp = regMMVM_L2_CNTL3_DEFAULT;
259
+
if (adev->gmc.translate_further) {
260
+
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12);
261
+
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,
262
+
L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
263
+
} else {
264
+
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9);
265
+
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,
266
+
L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
267
+
}
268
+
WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL3, tmp);
269
+
270
+
tmp = regMMVM_L2_CNTL4_DEFAULT;
271
+
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
272
+
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
273
+
WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL4, tmp);
274
+
275
+
tmp = regMMVM_L2_CNTL5_DEFAULT;
276
+
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);
277
+
WREG32_SOC15(GC, 0, regMMVM_L2_CNTL5, tmp);
278
+
}
279
+
280
+
static void mmhub_v3_0_enable_system_domain(struct amdgpu_device *adev)
281
+
{
282
+
uint32_t tmp;
283
+
284
+
tmp = RREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL);
285
+
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
286
+
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
287
+
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL,
288
+
RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
289
+
WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL, tmp);
290
+
}
291
+
292
+
static void mmhub_v3_0_disable_identity_aperture(struct amdgpu_device *adev)
293
+
{
294
+
/* These registers are not accessible to VF-SRIOV.
295
+
* The PF will program them instead.
296
+
*/
297
+
if (amdgpu_sriov_vf(adev))
298
+
return;
299
+
300
+
WREG32_SOC15(MMHUB, 0,
301
+
regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
302
+
0xFFFFFFFF);
303
+
WREG32_SOC15(MMHUB, 0,
304
+
regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
305
+
0x0000000F);
306
+
307
+
WREG32_SOC15(MMHUB, 0,
308
+
regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 0);
309
+
WREG32_SOC15(MMHUB, 0,
310
+
regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 0);
311
+
312
+
WREG32_SOC15(MMHUB, 0, regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32,
313
+
0);
314
+
WREG32_SOC15(MMHUB, 0, regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32,
315
+
0);
316
+
}
317
+
318
+
static void mmhub_v3_0_setup_vmid_config(struct amdgpu_device *adev)
319
+
{
320
+
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
321
+
int i;
322
+
uint32_t tmp;
323
+
324
+
for (i = 0; i <= 14; i++) {
325
+
tmp = RREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL, i);
326
+
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
327
+
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
328
+
adev->vm_manager.num_level);
329
+
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
330
+
RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
331
+
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
332
+
DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT,
333
+
1);
334
+
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
335
+
PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
336
+
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
337
+
VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
338
+
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
339
+
READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
340
+
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
341
+
WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
342
+
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
343
+
EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
344
+
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
345
+
PAGE_TABLE_BLOCK_SIZE,
346
+
adev->vm_manager.block_size - 9);
347
+
/* Send no-retry XNACK on fault to suppress VM fault storm. */
348
+
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
349
+
RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
350
+
!amdgpu_noretry);
351
+
WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL,
352
+
i * hub->ctx_distance, tmp);
353
+
WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,
354
+
i * hub->ctx_addr_distance, 0);
355
+
WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,
356
+
i * hub->ctx_addr_distance, 0);
357
+
WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,
358
+
i * hub->ctx_addr_distance,
359
+
lower_32_bits(adev->vm_manager.max_pfn - 1));
360
+
WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
361
+
i * hub->ctx_addr_distance,
362
+
upper_32_bits(adev->vm_manager.max_pfn - 1));
363
+
}
364
+
}
365
+
366
+
static void mmhub_v3_0_program_invalidation(struct amdgpu_device *adev)
367
+
{
368
+
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
369
+
unsigned i;
370
+
371
+
for (i = 0; i < 18; ++i) {
372
+
WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
373
+
i * hub->eng_addr_distance, 0xffffffff);
374
+
WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
375
+
i * hub->eng_addr_distance, 0x1f);
376
+
}
377
+
}
378
+
379
+
static int mmhub_v3_0_gart_enable(struct amdgpu_device *adev)
380
+
{
381
+
/* GART Enable. */
382
+
mmhub_v3_0_init_gart_aperture_regs(adev);
383
+
mmhub_v3_0_init_system_aperture_regs(adev);
384
+
mmhub_v3_0_init_tlb_regs(adev);
385
+
mmhub_v3_0_init_cache_regs(adev);
386
+
387
+
mmhub_v3_0_enable_system_domain(adev);
388
+
mmhub_v3_0_disable_identity_aperture(adev);
389
+
mmhub_v3_0_setup_vmid_config(adev);
390
+
mmhub_v3_0_program_invalidation(adev);
391
+
392
+
return 0;
393
+
}
394
+
395
+
static void mmhub_v3_0_gart_disable(struct amdgpu_device *adev)
396
+
{
397
+
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
398
+
u32 tmp;
399
+
u32 i;
400
+
401
+
/* Disable all tables */
402
+
for (i = 0; i < 16; i++)
403
+
WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_CNTL,
404
+
i * hub->ctx_distance, 0);
405
+
406
+
/* Setup TLB control */
407
+
tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL);
408
+
tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
409
+
tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
410
+
ENABLE_ADVANCED_DRIVER_MODEL, 0);
411
+
WREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL, tmp);
412
+
413
+
/* Setup L2 cache */
414
+
tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL);
415
+
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0);
416
+
WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL, tmp);
417
+
WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL3, 0);
418
+
}
419
+
420
+
/**
421
+
* mmhub_v3_0_set_fault_enable_default - update GART/VM fault handling
422
+
*
423
+
* @adev: amdgpu_device pointer
424
+
* @value: true redirects VM faults to the default page
425
+
*/
426
+
static void mmhub_v3_0_set_fault_enable_default(struct amdgpu_device *adev, bool value)
427
+
{
428
+
u32 tmp;
429
+
430
+
/* These registers are not accessible to VF-SRIOV.
431
+
* The PF will program them instead.
432
+
*/
433
+
if (amdgpu_sriov_vf(adev))
434
+
return;
435
+
436
+
tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL);
437
+
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
438
+
RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
439
+
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
440
+
PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
441
+
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
442
+
PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);
443
+
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
444
+
PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);
445
+
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
446
+
TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
447
+
value);
448
+
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
449
+
NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);
450
+
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
451
+
DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
452
+
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
453
+
VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
454
+
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
455
+
READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
456
+
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
457
+
WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
458
+
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
459
+
EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
460
+
if (!value) {
461
+
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
462
+
CRASH_ON_NO_RETRY_FAULT, 1);
463
+
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
464
+
CRASH_ON_RETRY_FAULT, 1);
465
+
}
466
+
WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL, tmp);
467
+
}
468
+
469
+
static const struct amdgpu_vmhub_funcs mmhub_v3_0_vmhub_funcs = {
470
+
.print_l2_protection_fault_status = mmhub_v3_0_print_l2_protection_fault_status,
471
+
.get_invalidate_req = mmhub_v3_0_get_invalidate_req,
472
+
};
473
+
474
+
static void mmhub_v3_0_init(struct amdgpu_device *adev)
475
+
{
476
+
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
477
+
478
+
hub->ctx0_ptb_addr_lo32 =
479
+
SOC15_REG_OFFSET(MMHUB, 0,
480
+
regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);
481
+
hub->ctx0_ptb_addr_hi32 =
482
+
SOC15_REG_OFFSET(MMHUB, 0,
483
+
regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
484
+
hub->vm_inv_eng0_sem =
485
+
SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_SEM);
486
+
hub->vm_inv_eng0_req =
487
+
SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_REQ);
488
+
hub->vm_inv_eng0_ack =
489
+
SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ACK);
490
+
hub->vm_context0_cntl =
491
+
SOC15_REG_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_CNTL);
492
+
hub->vm_l2_pro_fault_status =
493
+
SOC15_REG_OFFSET(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_STATUS);
494
+
hub->vm_l2_pro_fault_cntl =
495
+
SOC15_REG_OFFSET(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL);
496
+
497
+
hub->ctx_distance = regMMVM_CONTEXT1_CNTL - regMMVM_CONTEXT0_CNTL;
498
+
hub->ctx_addr_distance = regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 -
499
+
regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
500
+
hub->eng_distance = regMMVM_INVALIDATE_ENG1_REQ -
501
+
regMMVM_INVALIDATE_ENG0_REQ;
502
+
hub->eng_addr_distance = regMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 -
503
+
regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32;
504
+
505
+
hub->vm_cntx_cntl_vm_fault = MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
506
+
MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
507
+
MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
508
+
MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
509
+
MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
510
+
MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
511
+
MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
512
+
513
+
hub->vm_l2_bank_select_reserved_cid2 =
514
+
SOC15_REG_OFFSET(MMHUB, 0, regMMVM_L2_BANK_SELECT_RESERVED_CID2);
515
+
516
+
hub->vmhub_funcs = &mmhub_v3_0_vmhub_funcs;
517
+
}
518
+
519
+
static u64 mmhub_v3_0_get_fb_location(struct amdgpu_device *adev)
520
+
{
521
+
u64 base;
522
+
523
+
base = RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_LOCATION_BASE);
524
+
525
+
base &= MMMC_VM_FB_LOCATION_BASE__FB_BASE_MASK;
526
+
base <<= 24;
527
+
528
+
return base;
529
+
}
530
+
531
+
static u64 mmhub_v3_0_get_mc_fb_offset(struct amdgpu_device *adev)
532
+
{
533
+
return (u64)RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_OFFSET) << 24;
534
+
}
535
+
536
+
static void mmhub_v3_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
537
+
bool enable)
538
+
{
539
+
//TODO
540
+
}
541
+
542
+
static void mmhub_v3_0_update_medium_grain_light_sleep(struct amdgpu_device *adev,
543
+
bool enable)
544
+
{
545
+
//TODO
546
+
}
547
+
548
+
static int mmhub_v3_0_set_clockgating(struct amdgpu_device *adev,
549
+
enum amd_clockgating_state state)
550
+
{
551
+
if (amdgpu_sriov_vf(adev))
552
+
return 0;
553
+
554
+
mmhub_v3_0_update_medium_grain_clock_gating(adev,
555
+
state == AMD_CG_STATE_GATE);
556
+
mmhub_v3_0_update_medium_grain_light_sleep(adev,
557
+
state == AMD_CG_STATE_GATE);
558
+
return 0;
559
+
}
560
+
561
+
static void mmhub_v3_0_get_clockgating(struct amdgpu_device *adev, u64 *flags)
562
+
{
563
+
//TODO
564
+
}
565
+
566
+
const struct amdgpu_mmhub_funcs mmhub_v3_0_funcs = {
567
+
.init = mmhub_v3_0_init,
568
+
.get_fb_location = mmhub_v3_0_get_fb_location,
569
+
.get_mc_fb_offset = mmhub_v3_0_get_mc_fb_offset,
570
+
.gart_enable = mmhub_v3_0_gart_enable,
571
+
.set_fault_enable_default = mmhub_v3_0_set_fault_enable_default,
572
+
.gart_disable = mmhub_v3_0_gart_disable,
573
+
.set_clockgating = mmhub_v3_0_set_clockgating,
574
+
.get_clockgating = mmhub_v3_0_get_clockgating,
575
+
.setup_vm_pt_regs = mmhub_v3_0_setup_vm_pt_regs,
576
+
};
+28
drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.h
+28
drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.h
···
1
+
/*
2
+
* Copyright 2021 Advanced Micro Devices, Inc.
3
+
*
4
+
* Permission is hereby granted, free of charge, to any person obtaining a
5
+
* copy of this software and associated documentation files (the "Software"),
6
+
* to deal in the Software without restriction, including without limitation
7
+
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8
+
* and/or sell copies of the Software, and to permit persons to whom the
9
+
* Software is furnished to do so, subject to the following conditions:
10
+
*
11
+
* The above copyright notice and this permission notice shall be included in
12
+
* all copies or substantial portions of the Software.
13
+
*
14
+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15
+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16
+
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17
+
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18
+
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19
+
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20
+
* OTHER DEALINGS IN THE SOFTWARE.
21
+
*
22
+
*/
23
+
#ifndef __MMHUB_V3_0_H__
24
+
#define __MMHUB_V3_0_H__
25
+
26
+
extern const struct amdgpu_mmhub_funcs mmhub_v3_0_funcs;
27
+
28
+
#endif