tjh.dev / kernel
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drm/msm/dpu1: Rename sm8150_dspp_blk to sdm845_dspp_blk

SDM845 was the first SoC to include both PCC v4 and GC v1.8.
We don't currently support any other blocks but the common config
for these two can be reused for a large amount of SoCs.

Rename it to indicate the origin of that combo.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/533003/
Link: https://lore.kernel.org/r/20230420-topic-dpu_gc-v1-1-d9d1a5e40917@linaro.org
[DB: also applied to new catalog files]
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

authored by

Konrad Dybcio and committed by
Dmitry Baryshkov 9891b3df cd036d54

+39 -39
+4 -4
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
··· 111 111 112 112 static const struct dpu_dspp_cfg sdm845_dspp[] = { 113 113 DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, 114 - &sm8150_dspp_sblk), 114 + &sdm845_dspp_sblk), 115 115 DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK, 116 - &sm8150_dspp_sblk), 116 + &sdm845_dspp_sblk), 117 117 DSPP_BLK("dspp_2", DSPP_2, 0x58000, DSPP_SC7180_MASK, 118 - &sm8150_dspp_sblk), 118 + &sdm845_dspp_sblk), 119 119 DSPP_BLK("dspp_3", DSPP_3, 0x5a000, DSPP_SC7180_MASK, 120 - &sm8150_dspp_sblk), 120 + &sdm845_dspp_sblk), 121 121 }; 122 122 123 123 static const struct dpu_pingpong_cfg sdm845_pp[] = {
+4 -4
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
··· 118 118 119 119 static const struct dpu_dspp_cfg sm8150_dspp[] = { 120 120 DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, 121 - &sm8150_dspp_sblk), 121 + &sdm845_dspp_sblk), 122 122 DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK, 123 - &sm8150_dspp_sblk), 123 + &sdm845_dspp_sblk), 124 124 DSPP_BLK("dspp_2", DSPP_2, 0x58000, DSPP_SC7180_MASK, 125 - &sm8150_dspp_sblk), 125 + &sdm845_dspp_sblk), 126 126 DSPP_BLK("dspp_3", DSPP_3, 0x5a000, DSPP_SC7180_MASK, 127 - &sm8150_dspp_sblk), 127 + &sdm845_dspp_sblk), 128 128 }; 129 129 130 130 static const struct dpu_pingpong_cfg sm8150_pp[] = {
+4 -4
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
··· 117 117 118 118 static const struct dpu_dspp_cfg sc8180x_dspp[] = { 119 119 DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, 120 - &sm8150_dspp_sblk), 120 + &sdm845_dspp_sblk), 121 121 DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK, 122 - &sm8150_dspp_sblk), 122 + &sdm845_dspp_sblk), 123 123 DSPP_BLK("dspp_2", DSPP_2, 0x58000, DSPP_SC7180_MASK, 124 - &sm8150_dspp_sblk), 124 + &sdm845_dspp_sblk), 125 125 DSPP_BLK("dspp_3", DSPP_3, 0x5a000, DSPP_SC7180_MASK, 126 - &sm8150_dspp_sblk), 126 + &sdm845_dspp_sblk), 127 127 }; 128 128 129 129 static const struct dpu_pingpong_cfg sc8180x_pp[] = {
+4 -4
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
··· 119 119 120 120 static const struct dpu_dspp_cfg sm8250_dspp[] = { 121 121 DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, 122 - &sm8150_dspp_sblk), 122 + &sdm845_dspp_sblk), 123 123 DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK, 124 - &sm8150_dspp_sblk), 124 + &sdm845_dspp_sblk), 125 125 DSPP_BLK("dspp_2", DSPP_2, 0x58000, DSPP_SC7180_MASK, 126 - &sm8150_dspp_sblk), 126 + &sdm845_dspp_sblk), 127 127 DSPP_BLK("dspp_3", DSPP_3, 0x5a000, DSPP_SC7180_MASK, 128 - &sm8150_dspp_sblk), 128 + &sdm845_dspp_sblk), 129 129 }; 130 130 131 131 static const struct dpu_pingpong_cfg sm8250_pp[] = {
+1 -1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
··· 76 76 77 77 static const struct dpu_dspp_cfg sc7180_dspp[] = { 78 78 DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, 79 - &sm8150_dspp_sblk), 79 + &sdm845_dspp_sblk), 80 80 }; 81 81 82 82 static const struct dpu_pingpong_cfg sc7180_pp[] = {
+1 -1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
··· 56 56 57 57 static const struct dpu_dspp_cfg sm6115_dspp[] = { 58 58 DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, 59 - &sm8150_dspp_sblk), 59 + &sdm845_dspp_sblk), 60 60 }; 61 61 62 62 static const struct dpu_pingpong_cfg sm6115_pp[] = {
+1 -1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
··· 85 85 86 86 static const struct dpu_dspp_cfg sm6350_dspp[] = { 87 87 DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, 88 - &sm8150_dspp_sblk), 88 + &sdm845_dspp_sblk), 89 89 }; 90 90 91 91 static struct dpu_pingpong_cfg sm6350_pp[] = {
+1 -1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
··· 53 53 54 54 static const struct dpu_dspp_cfg qcm2290_dspp[] = { 55 55 DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, 56 - &sm8150_dspp_sblk), 56 + &sdm845_dspp_sblk), 57 57 }; 58 58 59 59 static const struct dpu_pingpong_cfg qcm2290_pp[] = {
+1 -1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
··· 57 57 58 58 static const struct dpu_dspp_cfg sm6375_dspp[] = { 59 59 DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, 60 - &sm8150_dspp_sblk), 60 + &sdm845_dspp_sblk), 61 61 }; 62 62 63 63 static const struct dpu_pingpong_cfg sm6375_pp[] = {
+4 -4
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
··· 117 117 118 118 static const struct dpu_dspp_cfg sm8350_dspp[] = { 119 119 DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, 120 - &sm8150_dspp_sblk), 120 + &sdm845_dspp_sblk), 121 121 DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK, 122 - &sm8150_dspp_sblk), 122 + &sdm845_dspp_sblk), 123 123 DSPP_BLK("dspp_2", DSPP_2, 0x58000, DSPP_SC7180_MASK, 124 - &sm8150_dspp_sblk), 124 + &sdm845_dspp_sblk), 125 125 DSPP_BLK("dspp_3", DSPP_3, 0x5a000, DSPP_SC7180_MASK, 126 - &sm8150_dspp_sblk), 126 + &sdm845_dspp_sblk), 127 127 }; 128 128 129 129 static const struct dpu_pingpong_cfg sm8350_pp[] = {
+1 -1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
··· 84 84 85 85 static const struct dpu_dspp_cfg sc7280_dspp[] = { 86 86 DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, 87 - &sm8150_dspp_sblk), 87 + &sdm845_dspp_sblk), 88 88 }; 89 89 90 90 static const struct dpu_pingpong_cfg sc7280_pp[] = {
+4 -4
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
··· 112 112 113 113 static const struct dpu_dspp_cfg sc8280xp_dspp[] = { 114 114 DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, 115 - &sm8150_dspp_sblk), 115 + &sdm845_dspp_sblk), 116 116 DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK, 117 - &sm8150_dspp_sblk), 117 + &sdm845_dspp_sblk), 118 118 DSPP_BLK("dspp_2", DSPP_2, 0x58000, DSPP_SC7180_MASK, 119 - &sm8150_dspp_sblk), 119 + &sdm845_dspp_sblk), 120 120 DSPP_BLK("dspp_3", DSPP_3, 0x5a000, DSPP_SC7180_MASK, 121 - &sm8150_dspp_sblk), 121 + &sdm845_dspp_sblk), 122 122 }; 123 123 124 124 static const struct dpu_pingpong_cfg sc8280xp_pp[] = {
+4 -4
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
··· 118 118 119 119 static const struct dpu_dspp_cfg sm8450_dspp[] = { 120 120 DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, 121 - &sm8150_dspp_sblk), 121 + &sdm845_dspp_sblk), 122 122 DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK, 123 - &sm8150_dspp_sblk), 123 + &sdm845_dspp_sblk), 124 124 DSPP_BLK("dspp_2", DSPP_2, 0x58000, DSPP_SC7180_MASK, 125 - &sm8150_dspp_sblk), 125 + &sdm845_dspp_sblk), 126 126 DSPP_BLK("dspp_3", DSPP_3, 0x5a000, DSPP_SC7180_MASK, 127 - &sm8150_dspp_sblk), 127 + &sdm845_dspp_sblk), 128 128 }; 129 129 130 130 static const struct dpu_pingpong_cfg sm8450_pp[] = {
+4 -4
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
··· 123 123 124 124 static const struct dpu_dspp_cfg sm8550_dspp[] = { 125 125 DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, 126 - &sm8150_dspp_sblk), 126 + &sdm845_dspp_sblk), 127 127 DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK, 128 - &sm8150_dspp_sblk), 128 + &sdm845_dspp_sblk), 129 129 DSPP_BLK("dspp_2", DSPP_2, 0x58000, DSPP_SC7180_MASK, 130 - &sm8150_dspp_sblk), 130 + &sdm845_dspp_sblk), 131 131 DSPP_BLK("dspp_3", DSPP_3, 0x5a000, DSPP_SC7180_MASK, 132 - &sm8150_dspp_sblk), 132 + &sdm845_dspp_sblk), 133 133 }; 134 134 static const struct dpu_pingpong_cfg sm8550_pp[] = { 135 135 PP_BLK_DITHER("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sc7280_pp_sblk,
+1 -1
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
··· 448 448 .len = 0x90, .version = 0x10007}, 449 449 }; 450 450 451 - static const struct dpu_dspp_sub_blks sm8150_dspp_sblk = { 451 + static const struct dpu_dspp_sub_blks sdm845_dspp_sblk = { 452 452 .pcc = {.id = DPU_DSPP_PCC, .base = 0x1700, 453 453 .len = 0x90, .version = 0x40000}, 454 454 };