tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

drm/amdgpu: Add a noverbose flag to psp_wait_for

For extended wait with retries on a PSP register value, add a noverbose
flag to avoid excessive error messages on each timeout.

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Asad Kamal <asad.kamal@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Lijo Lazar and committed by
Alex Deucher 9888f736 a54e4639

+130 -118
+8 -5
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
··· 575 575 return 0; 576 576 } 577 577 578 - int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 579 - uint32_t reg_val, uint32_t mask, bool check_changed) 578 + int psp_wait_for(struct psp_context *psp, uint32_t reg_index, uint32_t reg_val, 579 + uint32_t mask, uint32_t flags) 580 580 { 581 + bool check_changed = flags & PSP_WAITREG_CHANGED; 582 + bool verbose = !(flags & PSP_WAITREG_NOVERBOSE); 581 583 uint32_t val; 582 584 int i; 583 585 struct amdgpu_device *adev = psp->adev; ··· 599 597 udelay(1); 600 598 } 601 599 602 - dev_err(adev->dev, 603 - "psp reg (0x%x) wait timed out, mask: %x, read: %x exp: %x", 604 - reg_index, mask, val, reg_val); 600 + if (verbose) 601 + dev_err(adev->dev, 602 + "psp reg (0x%x) wait timed out, mask: %x, read: %x exp: %x", 603 + reg_index, mask, val, reg_val); 605 604 606 605 return -ETIME; 607 606 }
+5 -2
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
··· 134 134 PSP_REG_LAST 135 135 }; 136 136 137 + #define PSP_WAITREG_CHANGED BIT(0) /* check if the value has changed */ 138 + #define PSP_WAITREG_NOVERBOSE BIT(1) /* No error verbose */ 139 + 137 140 struct psp_funcs { 138 141 int (*init_microcode)(struct psp_context *psp); 139 142 int (*wait_for_bootloader)(struct psp_context *psp); ··· 535 532 extern const struct amdgpu_ip_block_version psp_v13_0_4_ip_block; 536 533 extern const struct amdgpu_ip_block_version psp_v14_0_ip_block; 537 534 538 - extern int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 539 - uint32_t field_val, uint32_t mask, bool check_changed); 535 + int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 536 + uint32_t field_val, uint32_t mask, uint32_t flags); 540 537 extern int psp_wait_for_spirom_update(struct psp_context *psp, uint32_t reg_index, 541 538 uint32_t field_val, uint32_t mask, uint32_t msec_timeout); 542 539
+2 -2
drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
··· 94 94 95 95 /* Wait for response flag (bit 31) in C2PMSG_64 */ 96 96 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 97 - MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false); 97 + MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0); 98 98 99 99 return ret; 100 100 } ··· 115 115 116 116 /* Wait for response flag (bit 31) in C2PMSG_64 */ 117 117 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 118 - MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false); 118 + MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0); 119 119 120 120 return ret; 121 121 }
+17 -18
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
··· 152 152 for (retry_loop = 0; retry_loop < 10; retry_loop++) { 153 153 /* Wait for bootloader to signify that is 154 154 ready having bit 31 of C2PMSG_35 set to 1 */ 155 - ret = psp_wait_for(psp, 156 - SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 157 - 0x80000000, 158 - 0x80000000, 159 - false); 155 + ret = psp_wait_for( 156 + psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 157 + 0x80000000, 0x80000000, PSP_WAITREG_NOVERBOSE); 160 158 161 159 if (ret == 0) 162 160 return 0; ··· 250 252 /* there might be handshake issue with hardware which needs delay */ 251 253 mdelay(20); 252 254 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81), 253 - RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81), 254 - 0, true); 255 + RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81), 0, 256 + PSP_WAITREG_CHANGED); 255 257 256 258 return ret; 257 259 } ··· 277 279 if (amdgpu_sriov_vf(adev)) 278 280 ret = psp_wait_for( 279 281 psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), 280 - MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false); 282 + MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0); 281 283 else 282 284 ret = psp_wait_for( 283 285 psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 284 - MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false); 286 + MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0); 285 287 286 288 return ret; 287 289 } ··· 319 321 /* Wait for response flag (bit 31) in C2PMSG_101 */ 320 322 ret = psp_wait_for( 321 323 psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), 322 - MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false); 324 + MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0); 323 325 324 326 } else { 325 327 /* Wait for sOS ready for ring creation */ 326 328 ret = psp_wait_for( 327 329 psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 328 - MBOX_TOS_READY_FLAG, MBOX_TOS_READY_MASK, false); 330 + MBOX_TOS_READY_FLAG, MBOX_TOS_READY_MASK, 0); 329 331 if (ret) { 330 332 DRM_ERROR("Failed to wait for sOS ready for ring creation\n"); 331 333 return ret; ··· 351 353 /* Wait for response flag (bit 31) in C2PMSG_64 */ 352 354 ret = psp_wait_for( 353 355 psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 354 - MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false); 356 + MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0); 355 357 } 356 358 357 359 return ret; ··· 385 387 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64); 386 388 387 389 ret = psp_wait_for(psp, offset, MBOX_TOS_READY_FLAG, 388 - MBOX_TOS_READY_MASK, false); 390 + MBOX_TOS_READY_MASK, 0); 389 391 390 392 if (ret) { 391 393 DRM_INFO("psp is not working correctly before mode1 reset!\n"); ··· 400 402 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33); 401 403 402 404 ret = psp_wait_for(psp, offset, MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 403 - false); 405 + 0); 404 406 405 407 if (ret) { 406 408 DRM_INFO("psp mode 1 reset failed!\n"); ··· 426 428 427 429 max_wait = MEM_TRAIN_SEND_MSG_TIMEOUT_US / adev->usec_timeout; 428 430 for (i = 0; i < max_wait; i++) { 429 - ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 430 - 0x80000000, 0x80000000, false); 431 + ret = psp_wait_for( 432 + psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 433 + 0x80000000, 0x80000000, PSP_WAITREG_NOVERBOSE); 431 434 if (ret == 0) 432 435 break; 433 436 } ··· 607 608 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, (fw_pri_mc_addr >> 20)); 608 609 609 610 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 610 - 0x80000000, 0x80000000, false); 611 + 0x80000000, 0x80000000, 0); 611 612 if (ret) 612 613 return ret; 613 614 ··· 644 645 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, C2PMSG_CMD_GFX_USB_PD_FW_VER); 645 646 646 647 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 647 - 0x80000000, 0x80000000, false); 648 + 0x80000000, 0x80000000, 0); 648 649 if (!ret) 649 650 *fw_ver = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36); 650 651
+5 -5
drivers/gpu/drm/amd/amdgpu/psp_v11_0_8.c
··· 43 43 /* Wait for response flag (bit 31) */ 44 44 ret = psp_wait_for( 45 45 psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), 46 - MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false); 46 + MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0); 47 47 } else { 48 48 /* Write the ring destroy command*/ 49 49 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, ··· 53 53 /* Wait for response flag (bit 31) */ 54 54 ret = psp_wait_for( 55 55 psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 56 - MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false); 56 + MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0); 57 57 } 58 58 59 59 return ret; ··· 91 91 /* Wait for response flag (bit 31) in C2PMSG_101 */ 92 92 ret = psp_wait_for( 93 93 psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), 94 - MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false); 94 + MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0); 95 95 96 96 } else { 97 97 /* Wait for sOS ready for ring creation */ 98 98 ret = psp_wait_for( 99 99 psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 100 - MBOX_TOS_READY_FLAG, MBOX_TOS_READY_MASK, false); 100 + MBOX_TOS_READY_FLAG, MBOX_TOS_READY_MASK, 0); 101 101 if (ret) { 102 102 DRM_ERROR("Failed to wait for trust OS ready for ring creation\n"); 103 103 return ret; ··· 123 123 /* Wait for response flag (bit 31) in C2PMSG_64 */ 124 124 ret = psp_wait_for( 125 125 psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 126 - MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false); 126 + MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0); 127 127 } 128 128 129 129 return ret;
+10 -10
drivers/gpu/drm/amd/amdgpu/psp_v12_0.c
··· 82 82 83 83 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */ 84 84 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 85 - 0x80000000, 0x80000000, false); 85 + 0x80000000, 0x80000000, 0); 86 86 if (ret) 87 87 return ret; 88 88 ··· 97 97 psp_gfxdrv_command_reg); 98 98 99 99 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 100 - 0x80000000, 0x80000000, false); 100 + 0x80000000, 0x80000000, 0); 101 101 102 102 return ret; 103 103 } ··· 118 118 119 119 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */ 120 120 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 121 - 0x80000000, 0x80000000, false); 121 + 0x80000000, 0x80000000, 0); 122 122 if (ret) 123 123 return ret; 124 124 ··· 133 133 psp_gfxdrv_command_reg); 134 134 135 135 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81), 136 - RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81), 137 - 0, true); 136 + RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81), 0, 137 + PSP_WAITREG_CHANGED); 138 138 139 139 return ret; 140 140 } ··· 163 163 164 164 /* Wait for response flag (bit 31) in C2PMSG_64 */ 165 165 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 166 - MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false); 166 + MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0); 167 167 168 168 return ret; 169 169 } ··· 186 186 if (amdgpu_sriov_vf(adev)) 187 187 ret = psp_wait_for( 188 188 psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), 189 - MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false); 189 + MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0); 190 190 else 191 191 ret = psp_wait_for( 192 192 psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 193 - MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false); 193 + MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0); 194 194 195 195 return ret; 196 196 } ··· 222 222 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64); 223 223 224 224 ret = psp_wait_for(psp, offset, MBOX_TOS_READY_FLAG, 225 - MBOX_TOS_READY_MASK, false); 225 + MBOX_TOS_READY_MASK, 0); 226 226 227 227 if (ret) { 228 228 DRM_INFO("psp is not working correctly before mode1 reset!\n"); ··· 237 237 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33); 238 238 239 239 ret = psp_wait_for(psp, offset, MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 240 - false); 240 + 0); 241 241 242 242 if (ret) { 243 243 DRM_INFO("psp mode 1 reset failed!\n");
+22 -19
drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
··· 182 182 ready having bit 31 of C2PMSG_33 set to 1 */ 183 183 ret = psp_wait_for( 184 184 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_33), 185 - 0x80000000, 0xffffffff, false); 185 + 0x80000000, 0xffffffff, PSP_WAITREG_NOVERBOSE); 186 186 187 187 if (ret == 0) 188 188 break; ··· 213 213 for (retry_loop = 0; retry_loop < retry_cnt; retry_loop++) { 214 214 ret = psp_wait_for( 215 215 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 216 - 0x80000000, 0xffffffff, false); 216 + 0x80000000, 0xffffffff, PSP_WAITREG_NOVERBOSE); 217 217 218 218 if (ret == 0) 219 219 return 0; ··· 362 362 /* there might be handshake issue with hardware which needs delay */ 363 363 mdelay(20); 364 364 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_81), 365 - RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81), 366 - 0, true); 365 + RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81), 0, 366 + PSP_WAITREG_CHANGED); 367 367 368 368 if (!ret) 369 369 psp_v13_0_init_sos_version(psp); ··· 386 386 /* Wait for response flag (bit 31) */ 387 387 ret = psp_wait_for( 388 388 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101), 389 - MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false); 389 + MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0); 390 390 } else { 391 391 /* Write the ring destroy command*/ 392 392 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, ··· 396 396 /* Wait for response flag (bit 31) */ 397 397 ret = psp_wait_for( 398 398 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), 399 - MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false); 399 + MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0); 400 400 } 401 401 402 402 return ret; ··· 434 434 /* Wait for response flag (bit 31) in C2PMSG_101 */ 435 435 ret = psp_wait_for( 436 436 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101), 437 - MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false); 437 + MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0); 438 438 439 439 } else { 440 440 /* Wait for sOS ready for ring creation */ 441 441 ret = psp_wait_for( 442 442 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), 443 - MBOX_TOS_READY_FLAG, MBOX_TOS_READY_MASK, false); 443 + MBOX_TOS_READY_FLAG, MBOX_TOS_READY_MASK, 0); 444 444 if (ret) { 445 445 DRM_ERROR("Failed to wait for trust OS ready for ring creation\n"); 446 446 return ret; ··· 466 466 /* Wait for response flag (bit 31) in C2PMSG_64 */ 467 467 ret = psp_wait_for( 468 468 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), 469 - MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false); 469 + MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0); 470 470 } 471 471 472 472 return ret; ··· 529 529 530 530 max_wait = MEM_TRAIN_SEND_MSG_TIMEOUT_US / adev->usec_timeout; 531 531 for (i = 0; i < max_wait; i++) { 532 - ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 533 - 0x80000000, 0x80000000, false); 532 + ret = psp_wait_for( 533 + psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 534 + 0x80000000, 0x80000000, PSP_WAITREG_NOVERBOSE); 534 535 if (ret == 0) 535 536 break; 536 537 } ··· 683 682 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, (fw_pri_mc_addr >> 20)); 684 683 685 684 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 686 - 0x80000000, 0x80000000, false); 685 + 0x80000000, 0x80000000, 0); 687 686 if (ret) 688 687 return ret; 689 688 ··· 720 719 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, C2PMSG_CMD_GFX_USB_PD_FW_VER); 721 720 722 721 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 723 - 0x80000000, 0x80000000, false); 722 + 0x80000000, 0x80000000, 0); 724 723 if (!ret) 725 724 *fw_ver = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36); 726 725 ··· 745 744 ret = psp_wait_for_spirom_update(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115), 746 745 MBOX_READY_FLAG, MBOX_READY_MASK, PSP_SPIROM_UPDATE_TIMEOUT); 747 746 else 748 - ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115), 749 - MBOX_READY_FLAG, MBOX_READY_MASK, false); 747 + ret = psp_wait_for( 748 + psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115), 749 + MBOX_READY_FLAG, MBOX_READY_MASK, 0); 750 750 if (ret) { 751 751 dev_err(adev->dev, "SPI cmd %x timed out, ret = %d", cmd, ret); 752 752 return ret; ··· 771 769 772 770 /* Confirm PSP is ready to start */ 773 771 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115), 774 - MBOX_READY_FLAG, MBOX_READY_MASK, false); 772 + MBOX_READY_FLAG, MBOX_READY_MASK, 0); 775 773 if (ret) { 776 774 dev_err(adev->dev, "PSP Not ready to start processing, ret = %d", ret); 777 775 return ret; ··· 806 804 807 805 /* Confirm PSP is ready to start */ 808 806 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115), 809 - MBOX_READY_FLAG, MBOX_READY_MASK, false); 807 + MBOX_READY_FLAG, MBOX_READY_MASK, 0); 810 808 if (ret) { 811 809 dev_err(adev->dev, "PSP Not ready to start processing, ret = %d", ret); 812 810 return ret; ··· 933 931 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, id); 934 932 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_103, val); 935 933 936 - ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101), 937 - 0x80000000, 0x80000000, false); 934 + ret = psp_wait_for( 935 + psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101), 936 + 0x80000000, 0x80000000, 0); 938 937 } 939 938 940 939 return ret;
+10 -12
drivers/gpu/drm/amd/amdgpu/psp_v13_0_4.c
··· 76 76 for (retry_loop = 0; retry_loop < 10; retry_loop++) { 77 77 /* Wait for bootloader to signify that is 78 78 ready having bit 31 of C2PMSG_35 set to 1 */ 79 - ret = psp_wait_for(psp, 80 - SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 81 - 0x80000000, 82 - 0x80000000, 83 - false); 79 + ret = psp_wait_for( 80 + psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 81 + 0x80000000, 0x80000000, PSP_WAITREG_NOVERBOSE); 84 82 85 83 if (ret == 0) 86 84 return 0; ··· 183 185 /* there might be handshake issue with hardware which needs delay */ 184 186 mdelay(20); 185 187 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_81), 186 - RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81), 187 - 0, true); 188 + RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81), 0, 189 + PSP_WAITREG_CHANGED); 188 190 189 191 return ret; 190 192 } ··· 204 206 /* Wait for response flag (bit 31) */ 205 207 ret = psp_wait_for( 206 208 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101), 207 - MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false); 209 + MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0); 208 210 } else { 209 211 /* Write the ring destroy command*/ 210 212 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, ··· 214 216 /* Wait for response flag (bit 31) */ 215 217 ret = psp_wait_for( 216 218 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), 217 - MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false); 219 + MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0); 218 220 } 219 221 220 222 return ret; ··· 252 254 /* Wait for response flag (bit 31) in C2PMSG_101 */ 253 255 ret = psp_wait_for( 254 256 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101), 255 - MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false); 257 + MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0); 256 258 257 259 } else { 258 260 /* Wait for sOS ready for ring creation */ 259 261 ret = psp_wait_for( 260 262 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), 261 - MBOX_TOS_READY_FLAG, MBOX_TOS_READY_MASK, false); 263 + MBOX_TOS_READY_FLAG, MBOX_TOS_READY_MASK, 0); 262 264 if (ret) { 263 265 DRM_ERROR("Failed to wait for trust OS ready for ring creation\n"); 264 266 return ret; ··· 284 286 /* Wait for response flag (bit 31) in C2PMSG_64 */ 285 287 ret = psp_wait_for( 286 288 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), 287 - MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false); 289 + MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0); 288 290 } 289 291 290 292 return ret;
+30 -25
drivers/gpu/drm/amd/amdgpu/psp_v14_0.c
··· 109 109 for (retry_loop = 0; retry_loop < 10; retry_loop++) { 110 110 /* Wait for bootloader to signify that is 111 111 ready having bit 31 of C2PMSG_35 set to 1 */ 112 - ret = psp_wait_for(psp, 113 - SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_35), 114 - 0x80000000, 115 - 0x80000000, 116 - false); 112 + ret = psp_wait_for( 113 + psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_35), 114 + 0x80000000, 0x80000000, PSP_WAITREG_NOVERBOSE); 117 115 118 116 if (ret == 0) 119 117 return 0; ··· 226 228 227 229 /* there might be handshake issue with hardware which needs delay */ 228 230 mdelay(20); 229 - ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_81), 230 - RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_81), 231 - 0, true); 231 + ret = psp_wait_for(psp, 232 + SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_81), 233 + RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_81), 0, 234 + PSP_WAITREG_CHANGED); 232 235 233 236 return ret; 234 237 } ··· 249 250 /* Wait for response flag (bit 31) */ 250 251 ret = psp_wait_for( 251 252 psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_101), 252 - MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false); 253 + MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0); 253 254 } else { 254 255 /* Write the ring destroy command*/ 255 256 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_64, ··· 259 260 /* Wait for response flag (bit 31) */ 260 261 ret = psp_wait_for( 261 262 psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64), 262 - MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false); 263 + MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0); 263 264 } 264 265 265 266 return ret; ··· 297 298 /* Wait for response flag (bit 31) in C2PMSG_101 */ 298 299 ret = psp_wait_for( 299 300 psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_101), 300 - MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false); 301 + MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0); 301 302 302 303 } else { 303 304 /* Wait for sOS ready for ring creation */ 304 305 ret = psp_wait_for( 305 306 psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64), 306 - MBOX_TOS_READY_FLAG, MBOX_TOS_READY_MASK, false); 307 + MBOX_TOS_READY_FLAG, MBOX_TOS_READY_MASK, 0); 307 308 if (ret) { 308 309 DRM_ERROR("Failed to wait for trust OS ready for ring creation\n"); 309 310 return ret; ··· 329 330 /* Wait for response flag (bit 31) in C2PMSG_64 */ 330 331 ret = psp_wait_for( 331 332 psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64), 332 - MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false); 333 + MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0); 333 334 } 334 335 335 336 return ret; ··· 392 393 393 394 max_wait = MEM_TRAIN_SEND_MSG_TIMEOUT_US / adev->usec_timeout; 394 395 for (i = 0; i < max_wait; i++) { 395 - ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_35), 396 - 0x80000000, 0x80000000, false); 396 + ret = psp_wait_for( 397 + psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_35), 398 + 0x80000000, 0x80000000, PSP_WAITREG_NOVERBOSE); 397 399 if (ret == 0) 398 400 break; 399 401 } ··· 545 545 */ 546 546 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_36, (fw_pri_mc_addr >> 20)); 547 547 548 - ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_35), 549 - 0x80000000, 0x80000000, false); 548 + ret = psp_wait_for(psp, 549 + SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_35), 550 + 0x80000000, 0x80000000, 0); 550 551 if (ret) 551 552 return ret; 552 553 ··· 583 582 584 583 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_35, C2PMSG_CMD_GFX_USB_PD_FW_VER); 585 584 586 - ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_35), 587 - 0x80000000, 0x80000000, false); 585 + ret = psp_wait_for(psp, 586 + SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_35), 587 + 0x80000000, 0x80000000, 0); 588 588 if (!ret) 589 589 *fw_ver = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_36); 590 590 ··· 609 607 ret = psp_wait_for_spirom_update(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_115), 610 608 MBOX_READY_FLAG, MBOX_READY_MASK, PSP_SPIROM_UPDATE_TIMEOUT); 611 609 else 612 - ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_115), 613 - MBOX_READY_FLAG, MBOX_READY_MASK, false); 610 + ret = psp_wait_for( 611 + psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_115), 612 + MBOX_READY_FLAG, MBOX_READY_MASK, 0); 614 613 615 - ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_115), 616 - MBOX_READY_FLAG, MBOX_READY_MASK, false); 614 + ret = psp_wait_for(psp, 615 + SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_115), 616 + MBOX_READY_FLAG, MBOX_READY_MASK, 0); 617 617 if (ret) { 618 618 dev_err(adev->dev, "SPI cmd %x timed out, ret = %d", cmd, ret); 619 619 return ret; ··· 638 634 int ret; 639 635 640 636 /* Confirm PSP is ready to start */ 641 - ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_115), 642 - MBOX_READY_FLAG, MBOX_READY_MASK, false); 637 + ret = psp_wait_for(psp, 638 + SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_115), 639 + MBOX_READY_FLAG, MBOX_READY_MASK, 0); 643 640 if (ret) { 644 641 dev_err(adev->dev, "PSP Not ready to start processing, ret = %d", ret); 645 642 return ret;
+21 -20
drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
··· 91 91 92 92 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */ 93 93 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 94 - 0x80000000, 0x80000000, false); 94 + 0x80000000, 0x80000000, 0); 95 95 if (ret) 96 96 return ret; 97 97 ··· 109 109 mdelay(20); 110 110 111 111 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 112 - 0x80000000, 0x80000000, false); 112 + 0x80000000, 0x80000000, 0); 113 113 114 114 return ret; 115 115 } ··· 130 130 131 131 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */ 132 132 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 133 - 0x80000000, 0x80000000, false); 133 + 0x80000000, 0x80000000, 0); 134 134 if (ret) 135 135 return ret; 136 136 ··· 147 147 /* there might be handshake issue with hardware which needs delay */ 148 148 mdelay(20); 149 149 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81), 150 - RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81), 151 - 0, true); 150 + RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81), 0, 151 + PSP_WAITREG_CHANGED); 152 152 return ret; 153 153 } 154 154 ··· 168 168 169 169 mdelay(20); 170 170 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 171 - 0x80000000, 0x8000FFFF, false); 171 + 0x80000000, 0x8000FFFF, 0); 172 172 173 173 /* Change IH ring for UMC */ 174 174 tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1216b); ··· 180 180 181 181 mdelay(20); 182 182 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 183 - 0x80000000, 0x8000FFFF, false); 183 + 0x80000000, 0x8000FFFF, 0); 184 184 } 185 185 186 186 static int psp_v3_1_ring_create(struct psp_context *psp, ··· 217 217 mdelay(20); 218 218 219 219 /* Wait for response flag (bit 31) in C2PMSG_101 */ 220 - ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, 221 - mmMP0_SMN_C2PMSG_101), 0x80000000, 222 - 0x8000FFFF, false); 220 + ret = psp_wait_for( 221 + psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), 222 + 0x80000000, 0x8000FFFF, 0); 223 223 } else { 224 224 225 225 /* Write low address of the ring to C2PMSG_69 */ ··· 240 240 mdelay(20); 241 241 242 242 /* Wait for response flag (bit 31) in C2PMSG_64 */ 243 - ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, 244 - mmMP0_SMN_C2PMSG_64), 0x80000000, 245 - 0x8000FFFF, false); 246 - 243 + ret = psp_wait_for( 244 + psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 245 + 0x80000000, 0x8000FFFF, 0); 247 246 } 248 247 return ret; 249 248 } ··· 266 267 267 268 /* Wait for response flag (bit 31) */ 268 269 if (amdgpu_sriov_vf(adev)) 269 - ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), 270 - 0x80000000, 0x80000000, false); 270 + ret = psp_wait_for( 271 + psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), 272 + 0x80000000, 0x80000000, 0); 271 273 else 272 - ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 273 - 0x80000000, 0x80000000, false); 274 + ret = psp_wait_for( 275 + psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 276 + 0x80000000, 0x80000000, 0); 274 277 275 278 return ret; 276 279 } ··· 312 311 313 312 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64); 314 313 315 - ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false); 314 + ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, 0); 316 315 317 316 if (ret) { 318 317 DRM_INFO("psp is not working correctly before mode1 reset!\n"); ··· 326 325 327 326 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33); 328 327 329 - ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false); 328 + ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, 0); 330 329 331 330 if (ret) { 332 331 DRM_INFO("psp mode 1 reset failed!\n");