Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

ARM: dts: imx6qdl: Add imx6qdl-pico support

Add support for all the imx6qdl-pico variants.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

authored by

Fabio Estevam and committed by
Shawn Guo
98670a0b 47246faf

+928
+8
arch/arm/boot/dts/Makefile
··· 446 446 imx6dl-nitrogen6x.dtb \ 447 447 imx6dl-phytec-mira-rdk-nand.dtb \ 448 448 imx6dl-phytec-pbab01.dtb \ 449 + imx6dl-pico-dwarf.dtb \ 450 + imx6dl-pico-hobbit.dtb \ 451 + imx6dl-pico-nymph.dtb \ 452 + imx6dl-pico-pi.dtb \ 449 453 imx6dl-rex-basic.dtb \ 450 454 imx6dl-riotboard.dtb \ 451 455 imx6dl-sabreauto.dtb \ ··· 533 529 imx6q-phytec-mira-rdk-emmc.dtb \ 534 530 imx6q-phytec-mira-rdk-nand.dtb \ 535 531 imx6q-phytec-pbab01.dtb \ 532 + imx6q-pico-dwarf.dtb \ 533 + imx6q-pico-hobbit.dtb \ 534 + imx6q-pico-nymph.dtb \ 535 + imx6q-pico-pi.dtb \ 536 536 imx6q-pistachio.dtb \ 537 537 imx6q-rex-pro.dtb \ 538 538 imx6q-sabreauto.dtb \
+17
arch/arm/boot/dts/imx6dl-pico-dwarf.dts
··· 1 + // SPDX-License-Identifier: GPL-2.0 OR MIT 2 + // 3 + // Copyright 2018 Technexion Ltd. 4 + // 5 + // Author: Wig Cheng <wig.cheng@technexion.com> 6 + // Richard Hu <richard.hu@technexion.com> 7 + // Tapani Utriainen <tapani@technexion.com> 8 + 9 + /dts-v1/; 10 + 11 + #include "imx6dl.dtsi" 12 + #include "imx6qdl-pico-pi.dtsi" 13 + 14 + / { 15 + model = "TechNexion PICO-IMX6 DualLite/Solo Board and Dwarf baseboard"; 16 + compatible = "technexion,imx6dl-pico", "fsl,imx6dl"; 17 + };
+17
arch/arm/boot/dts/imx6dl-pico-hobbit.dts
··· 1 + // SPDX-License-Identifier: GPL-2.0 OR MIT 2 + // 3 + // Copyright 2018 Technexion Ltd. 4 + // 5 + // Author: Wig Cheng <wig.cheng@technexion.com> 6 + // Richard Hu <richard.hu@technexion.com> 7 + // Tapani Utriainen <tapani@technexion.com> 8 + 9 + /dts-v1/; 10 + 11 + #include "imx6dl.dtsi" 12 + #include "imx6qdl-pico-hobbit.dtsi" 13 + 14 + / { 15 + model = "TechNexion PICO-IMX6 DualLite/Solo Board and Hobbit baseboard"; 16 + compatible = "technexion,imx6dl-pico", "fsl,imx6dl"; 17 + };
+17
arch/arm/boot/dts/imx6dl-pico-nymph.dts
··· 1 + // SPDX-License-Identifier: GPL-2.0 OR MIT 2 + // 3 + // Copyright 2018 Technexion Ltd. 4 + // 5 + // Author: Wig Cheng <wig.cheng@technexion.com> 6 + // Richard Hu <richard.hu@technexion.com> 7 + // Tapani Utriainen <tapani@technexion.com> 8 + 9 + /dts-v1/; 10 + 11 + #include "imx6dl.dtsi" 12 + #include "imx6qdl-pico-pi.dtsi" 13 + 14 + / { 15 + model = "TechNexion PICO-IMX6 DualLite/Solo Board and Nymph baseboard"; 16 + compatible = "technexion,imx6dl-pico", "fsl,imx6dl"; 17 + };
+17
arch/arm/boot/dts/imx6dl-pico-pi.dts
··· 1 + // SPDX-License-Identifier: GPL-2.0 OR MIT 2 + // 3 + // Copyright 2018 Technexion Ltd. 4 + // 5 + // Author: Wig Cheng <wig.cheng@technexion.com> 6 + // Richard Hu <richard.hu@technexion.com> 7 + // Tapani Utriainen <tapani@technexion.com> 8 + 9 + /dts-v1/; 10 + 11 + #include "imx6dl.dtsi" 12 + #include "imx6qdl-pico-pi.dtsi" 13 + 14 + / { 15 + model = "TechNexion PICO-IMX6 DualLite/Solo Board and PI baseboard"; 16 + compatible = "technexion,imx6dl-pico", "fsl,imx6dl"; 17 + };
+17
arch/arm/boot/dts/imx6q-pico-dwarf.dts
··· 1 + // SPDX-License-Identifier: GPL-2.0 OR MIT 2 + // 3 + // Copyright 2018 Technexion Ltd. 4 + // 5 + // Author: Wig Cheng <wig.cheng@technexion.com> 6 + // Richard Hu <richard.hu@technexion.com> 7 + // Tapani Utriainen <tapani@technexion.com> 8 + 9 + /dts-v1/; 10 + 11 + #include "imx6q.dtsi" 12 + #include "imx6qdl-pico-pi.dtsi" 13 + 14 + / { 15 + model = "TechNexion PICO-IMX6 Quad Board and Dwarf baseboard"; 16 + compatible = "technexion,imx6q-pico", "fsl,imx6q"; 17 + };
+17
arch/arm/boot/dts/imx6q-pico-hobbit.dts
··· 1 + // SPDX-License-Identifier: GPL-2.0 OR MIT 2 + // 3 + // Copyright 2018 Technexion Ltd. 4 + // 5 + // Author: Wig Cheng <wig.cheng@technexion.com> 6 + // Richard Hu <richard.hu@technexion.com> 7 + // Tapani Utriainen <tapani@technexion.com> 8 + 9 + /dts-v1/; 10 + 11 + #include "imx6q.dtsi" 12 + #include "imx6qdl-pico-hobbit.dtsi" 13 + 14 + / { 15 + model = "TechNexion PICO-IMX6 Quad Board and Hobbit baseboard"; 16 + compatible = "technexion,imx6q-pico", "fsl,imx6q"; 17 + };
+17
arch/arm/boot/dts/imx6q-pico-nymph.dts
··· 1 + // SPDX-License-Identifier: GPL-2.0 OR MIT 2 + // 3 + // Copyright 2018 Technexion Ltd. 4 + // 5 + // Author: Wig Cheng <wig.cheng@technexion.com> 6 + // Richard Hu <richard.hu@technexion.com> 7 + // Tapani Utriainen <tapani@technexion.com> 8 + 9 + /dts-v1/; 10 + 11 + #include "imx6q.dtsi" 12 + #include "imx6qdl-pico-pi.dtsi" 13 + 14 + / { 15 + model = "TechNexion PICO-IMX6 Quad Board and Nymph baseboard"; 16 + compatible = "technexion,imx6q-pico", "fsl,imx6q"; 17 + };
+17
arch/arm/boot/dts/imx6q-pico-pi.dts
··· 1 + // SPDX-License-Identifier: GPL-2.0 OR MIT 2 + // 3 + // Copyright 2018 Technexion Ltd. 4 + // 5 + // Author: Wig Cheng <wig.cheng@technexion.com> 6 + // Richard Hu <richard.hu@technexion.com> 7 + // Tapani Utriainen <tapani@technexion.com> 8 + 9 + /dts-v1/; 10 + 11 + #include "imx6q.dtsi" 12 + #include "imx6qdl-pico-pi.dtsi" 13 + 14 + / { 15 + model = "TechNexion PICO-IMX6 Quad Board and PI baseboard"; 16 + compatible = "technexion,imx6q-pico", "fsl,imx6q"; 17 + };
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arch/arm/boot/dts/imx6qdl-pico-dwarf.dtsi
··· 1 + // SPDX-License-Identifier: GPL-2.0+ OR MIT 2 + // 3 + // Copyright 2017 NXP 4 + 5 + #include "imx6qdl-pico.dtsi" 6 + 7 + / { 8 + leds { 9 + compatible = "gpio-leds"; 10 + pinctrl-names = "default"; 11 + pinctrl-0 = <&pinctrl_gpio_leds>; 12 + 13 + led { 14 + label = "gpio-led"; 15 + gpios = <&gpio5 31 GPIO_ACTIVE_HIGH>; 16 + }; 17 + }; 18 + 19 + }; 20 + 21 + &i2c1 { 22 + mpl3115@60 { 23 + compatible = "fsl,mpl3115"; 24 + reg = <0x60>; 25 + }; 26 + }; 27 + 28 + &i2c2 { 29 + io-expander@25 { 30 + compatible = "nxp,pca9554"; 31 + reg = <0x25>; 32 + gpio-controller; 33 + #gpio-cells = <2>; 34 + #interrupt-cells = <2>; 35 + }; 36 + 37 + }; 38 + 39 + &iomuxc { 40 + pinctrl_gpio_leds: gpioledsgrp { 41 + fsl,pins = < 42 + MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x1b0b0 43 + >; 44 + }; 45 + };
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arch/arm/boot/dts/imx6qdl-pico-hobbit.dtsi
··· 1 + // SPDX-License-Identifier: GPL-2.0+ OR MIT 2 + // 3 + // Copyright 2017 NXP 4 + 5 + #include "imx6qdl-pico.dtsi" 6 + 7 + / { 8 + leds { 9 + compatible = "gpio-leds"; 10 + pinctrl-names = "default"; 11 + pinctrl-0 = <&pinctrl_gpio_leds>; 12 + 13 + led { 14 + label = "gpio-led"; 15 + gpios = <&gpio5 31 GPIO_ACTIVE_HIGH>; 16 + }; 17 + }; 18 + 19 + }; 20 + 21 + &i2c2 { 22 + status = "okay"; 23 + 24 + adc081c: adc@50 { 25 + compatible = "ti,adc081c"; 26 + reg = <0x50>; 27 + vref-supply = <&reg_3p3v>; 28 + }; 29 + }; 30 + 31 + &iomuxc { 32 + pinctrl_gpio_leds: gpioledsgrp { 33 + fsl,pins = < 34 + MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x1b0b0 35 + >; 36 + }; 37 + };
+54
arch/arm/boot/dts/imx6qdl-pico-nymph.dtsi
··· 1 + // SPDX-License-Identifier: GPL-2.0+ OR MIT 2 + 3 + #include "imx6qdl-pico.dtsi" 4 + 5 + / { 6 + leds { 7 + compatible = "gpio-leds"; 8 + pinctrl-names = "default"; 9 + pinctrl-0 = <&pinctrl_gpio_leds>; 10 + 11 + led { 12 + label = "gpio-led"; 13 + gpios = <&gpio5 31 GPIO_ACTIVE_HIGH>; 14 + }; 15 + }; 16 + 17 + }; 18 + 19 + &i2c1 { 20 + adc@52 { 21 + compatible = "ti,adc081c"; 22 + reg = <0x52>; 23 + vref-supply = <&reg_2p5v>; 24 + }; 25 + }; 26 + 27 + &i2c2 { 28 + io-expander@25 { 29 + compatible = "nxp,pca9554"; 30 + reg = <0x25>; 31 + gpio-controller; 32 + #gpio-cells = <2>; 33 + #interrupt-cells = <2>; 34 + }; 35 + }; 36 + 37 + &i2c3 { 38 + rtc@68 { 39 + compatible = "dallas,ds1337"; 40 + reg = <0x68>; 41 + }; 42 + }; 43 + 44 + &pcie { 45 + status = "okay"; 46 + }; 47 + 48 + &iomuxc { 49 + pinctrl_gpio_leds: gpioledsgrp { 50 + fsl,pins = < 51 + MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x1b0b0 52 + >; 53 + }; 54 + };
+31
arch/arm/boot/dts/imx6qdl-pico-pi.dtsi
··· 1 + // SPDX-License-Identifier: GPL-2.0+ OR MIT 2 + // 3 + // Copyright 2017 NXP 4 + 5 + #include "imx6qdl-pico.dtsi" 6 + 7 + / { 8 + leds { 9 + compatible = "gpio-leds"; 10 + pinctrl-names = "default"; 11 + pinctrl-0 = <&pinctrl_gpio_leds>; 12 + 13 + led { 14 + label = "gpio-led"; 15 + gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>; 16 + }; 17 + }; 18 + 19 + }; 20 + 21 + &hdmi { 22 + status = "disabled"; 23 + }; 24 + 25 + &iomuxc { 26 + pinctrl_gpio_leds: gpioledsgrp { 27 + fsl,pins = < 28 + MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0 29 + >; 30 + }; 31 + };
+617
arch/arm/boot/dts/imx6qdl-pico.dtsi
··· 1 + // SPDX-License-Identifier: GPL-2.0 OR MIT 2 + // 3 + // Copyright 2018 Technexion Ltd. 4 + // 5 + // Author: Wig Cheng <wig.cheng@technexion.com> 6 + // Richard Hu <richard.hu@technexion.com> 7 + // Tapani Utriainen <tapani@technexion.com> 8 + 9 + #include <dt-bindings/gpio/gpio.h> 10 + 11 + / { 12 + chosen { 13 + stdout-path = &uart1; 14 + }; 15 + 16 + reg_2p5v: regulator-2p5v { 17 + compatible = "regulator-fixed"; 18 + regulator-name = "2P5V"; 19 + regulator-min-microvolt = <2500000>; 20 + regulator-max-microvolt = <2500000>; 21 + regulator-always-on; 22 + }; 23 + 24 + reg_3p3v: regulator-3p3v { 25 + compatible = "regulator-fixed"; 26 + regulator-name = "3P3V"; 27 + regulator-min-microvolt = <3300000>; 28 + regulator-max-microvolt = <3300000>; 29 + regulator-always-on; 30 + }; 31 + 32 + reg_1p8v: regulator-1p8v { 33 + compatible = "regulator-fixed"; 34 + regulator-name = "1P8V"; 35 + regulator-min-microvolt = <1800000>; 36 + regulator-max-microvolt = <1800000>; 37 + regulator-always-on; 38 + }; 39 + 40 + reg_1p5v: regulator-1p5v { 41 + compatible = "regulator-fixed"; 42 + regulator-name = "1P5V"; 43 + regulator-min-microvolt = <1500000>; 44 + regulator-max-microvolt = <1500000>; 45 + regulator-always-on; 46 + }; 47 + 48 + reg_2p8v: regulator-2p8v { 49 + compatible = "regulator-fixed"; 50 + regulator-name = "2P8V"; 51 + regulator-min-microvolt = <2800000>; 52 + regulator-max-microvolt = <2800000>; 53 + regulator-always-on; 54 + }; 55 + 56 + reg_usb_otg_vbus: regulator-usb-otg-vbus { 57 + pinctrl-names = "default"; 58 + pinctrl-0 = <&pinctrl_usbotg_vbus>; 59 + compatible = "regulator-fixed"; 60 + regulator-name = "usb_otg_vbus"; 61 + regulator-min-microvolt = <5000000>; 62 + regulator-max-microvolt = <5000000>; 63 + gpio = <&gpio3 22 GPIO_ACTIVE_LOW>; 64 + }; 65 + 66 + codec_osc: clock { 67 + compatible = "fixed-clock"; 68 + #clock-cells = <0>; 69 + clock-frequency = <24576000>; 70 + }; 71 + 72 + sound { 73 + compatible = "fsl,imx-audio-sgtl5000"; 74 + model = "imx6-pico-sgtl5000"; 75 + ssi-controller = <&ssi1>; 76 + audio-codec = <&sgtl5000>; 77 + audio-routing = 78 + "MIC_IN", "Mic Jack", 79 + "Mic Jack", "Mic Bias", 80 + "Headphone Jack", "HP_OUT"; 81 + mux-int-port = <1>; 82 + mux-ext-port = <3>; 83 + }; 84 + 85 + backlight: backlight { 86 + compatible = "pwm-backlight"; 87 + pwms = <&pwm4 0 50000 0>; 88 + brightness-levels = <0 36 72 108 144 180 216 255>; 89 + default-brightness-level = <6>; 90 + status = "okay"; 91 + }; 92 + 93 + reg_lcd_3v3: regulator-lcd-3v3 { 94 + compatible = "regulator-fixed"; 95 + pinctrl-names = "default"; 96 + pinctrl-0 = <&pinctrl_reg_lcd>; 97 + regulator-name = "lcd-3v3"; 98 + regulator-min-microvolt = <3300000>; 99 + regulator-max-microvolt = <3300000>; 100 + gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; 101 + enable-active-high; 102 + }; 103 + 104 + lcd_display: disp0 { 105 + compatible = "fsl,imx-parallel-display"; 106 + #address-cells = <1>; 107 + #size-cells = <0>; 108 + pinctrl-names = "default"; 109 + pinctrl-0 = <&pinctrl_ipu1>; 110 + status = "okay"; 111 + 112 + port@0 { 113 + reg = <0>; 114 + 115 + lcd_display_in: endpoint { 116 + remote-endpoint = <&ipu1_di0_disp0>; 117 + }; 118 + }; 119 + 120 + port@1 { 121 + reg = <1>; 122 + 123 + lcd_display_out: endpoint { 124 + remote-endpoint = <&lcd_panel_in>; 125 + }; 126 + }; 127 + }; 128 + 129 + panel { 130 + compatible = "vxt,vl050-8048nt-c01"; 131 + backlight = <&backlight>; 132 + power-supply = <&reg_lcd_3v3>; 133 + 134 + port { 135 + lcd_panel_in: endpoint { 136 + remote-endpoint = <&lcd_display_out>; 137 + }; 138 + }; 139 + }; 140 + }; 141 + 142 + &audmux { 143 + pinctrl-names = "default"; 144 + pinctrl-0 = <&pinctrl_audmux>; 145 + status = "okay"; 146 + }; 147 + 148 + &can1 { 149 + pinctrl-names = "default"; 150 + pinctrl-0 = <&pinctrl_flexcan1>; 151 + status = "okay"; 152 + }; 153 + 154 + &can2 { 155 + pinctrl-names = "default"; 156 + pinctrl-0 = <&pinctrl_flexcan2>; 157 + status = "okay"; 158 + }; 159 + 160 + &clks { 161 + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, 162 + <&clks IMX6QDL_CLK_LDB_DI1_SEL>; 163 + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, 164 + <&clks IMX6QDL_CLK_PLL3_USB_OTG>; 165 + }; 166 + 167 + &ecspi2 { 168 + pinctrl-names = "default"; 169 + pinctrl-0 = <&pinctrl_ecspi2>; 170 + cs-gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>; 171 + status = "okay"; 172 + }; 173 + 174 + &fec { 175 + pinctrl-names = "default"; 176 + pinctrl-0 = <&pinctrl_enet>; 177 + phy-mode = "rgmii-id"; 178 + phy-reset-gpios = <&gpio1 26 GPIO_ACTIVE_LOW>; 179 + status = "okay"; 180 + }; 181 + 182 + &hdmi { 183 + ddc-i2c-bus = <&i2c2>; 184 + status = "okay"; 185 + }; 186 + 187 + &i2c1 { 188 + pinctrl-names = "default"; 189 + pinctrl-0 = <&pinctrl_i2c1>; 190 + status = "okay"; 191 + 192 + sgtl5000: audio-codec@a { 193 + #sound-dai-cells = <0>; 194 + reg = <0x0a>; 195 + compatible = "fsl,sgtl5000"; 196 + clocks = <&codec_osc>; 197 + VDDA-supply = <&reg_2p5v>; 198 + VDDIO-supply = <&reg_1p8v>; 199 + }; 200 + }; 201 + 202 + &i2c2 { 203 + clock-frequency = <100000>; 204 + pinctrl-names = "default"; 205 + pinctrl-0 = <&pinctrl_i2c2>; 206 + status = "okay"; 207 + 208 + touchscreen@38 { 209 + compatible = "edt,edt-ft5x06"; 210 + reg = <0x38>; 211 + interrupt-parent = <&gpio5>; 212 + interrupts = <31 IRQ_TYPE_EDGE_FALLING>; 213 + reset-gpios = <&gpio5 27 GPIO_ACTIVE_LOW>; 214 + touchscreen-size-x = <800>; 215 + touchscreen-size-y = <480>; 216 + wakeup-source; 217 + }; 218 + 219 + camera@3c { 220 + compatible = "ovti,ov5645"; 221 + pinctrl-names = "default"; 222 + pinctrl-0 = <&pinctrl_ov5645>; 223 + reg = <0x3c>; 224 + clocks = <&clks IMX6QDL_CLK_CKO2>; 225 + clock-names = "xclk"; 226 + clock-frequency = <24000000>; 227 + vdddo-supply = <&reg_1p8v>; 228 + vdda-supply = <&reg_2p8v>; 229 + vddd-supply = <&reg_1p5v>; 230 + enable-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; 231 + reset-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; 232 + 233 + port { 234 + ov5645_to_mipi_csi2: endpoint { 235 + remote-endpoint = <&mipi_csi2_in>; 236 + clock-lanes = <0>; 237 + data-lanes = <1 2>; 238 + }; 239 + }; 240 + }; 241 + }; 242 + 243 + &i2c3 { 244 + pinctrl-names = "default"; 245 + pinctrl-0 = <&pinctrl_i2c3>; 246 + status = "okay"; 247 + }; 248 + 249 + &ipu1_di0_disp0 { 250 + remote-endpoint = <&lcd_display_in>; 251 + }; 252 + 253 + &mipi_csi { 254 + status = "okay"; 255 + 256 + port@0 { 257 + reg = <0>; 258 + 259 + mipi_csi2_in: endpoint { 260 + remote-endpoint = <&ov5645_to_mipi_csi2>; 261 + clock-lanes = <0>; 262 + data-lanes = <1 2>; 263 + }; 264 + }; 265 + }; 266 + 267 + &pcie { 268 + pinctrl-names = "default"; 269 + pinctrl-0 = <&pinctrl_pcie_reset>; 270 + reset-gpio = <&gpio5 21 GPIO_ACTIVE_LOW>; 271 + }; 272 + 273 + &pwm1 { 274 + pinctrl-names = "default"; 275 + pinctrl-0 = <&pinctrl_pwm1>; 276 + status = "okay"; 277 + }; 278 + 279 + &pwm2 { 280 + pinctrl-names = "default"; 281 + pinctrl-0 = <&pinctrl_pwm2>; 282 + status = "okay"; 283 + }; 284 + 285 + &pwm3 { 286 + pinctrl-names = "default"; 287 + pinctrl-0 = <&pinctrl_pwm3>; 288 + status = "okay"; 289 + }; 290 + 291 + &pwm4 { 292 + pinctrl-names = "default"; 293 + pinctrl-0 = <&pinctrl_pwm4>; 294 + status = "okay"; 295 + }; 296 + 297 + &ssi1 { 298 + status = "okay"; 299 + }; 300 + 301 + &uart1 { 302 + pinctrl-names = "default"; 303 + pinctrl-0 = <&pinctrl_uart1>; 304 + status = "okay"; 305 + }; 306 + 307 + &uart2 { /* Bluetooth module */ 308 + pinctrl-names = "default"; 309 + pinctrl-0 = <&pinctrl_uart2>; 310 + uart-has-rtscts; 311 + status = "okay"; 312 + }; 313 + 314 + &uart3 { 315 + pinctrl-names = "default"; 316 + pinctrl-0 = <&pinctrl_uart3>; 317 + uart-has-rtscts; 318 + status = "okay"; 319 + }; 320 + 321 + &usbh1 { 322 + status = "okay"; 323 + }; 324 + 325 + &usbotg { 326 + vbus-supply = <&reg_usb_otg_vbus>; 327 + pinctrl-names = "default"; 328 + pinctrl-0 = <&pinctrl_usbotg>; 329 + disable-over-current; 330 + dr_mode = "otg"; 331 + status = "okay"; 332 + }; 333 + 334 + &usdhc1 { 335 + pinctrl-names = "default"; 336 + pinctrl-0 = <&pinctrl_usdhc1>; 337 + bus-width = <8>; 338 + cd-gpios = <&gpio3 9 GPIO_ACTIVE_LOW>; 339 + status = "okay"; 340 + }; 341 + 342 + &usdhc2 { /* Wifi/BT */ 343 + pinctrl-names = "default"; 344 + pinctrl-0 = <&pinctrl_usdhc2>; 345 + bus-width = <4>; 346 + no-1-8-v; 347 + keep-power-in-suspend; 348 + non-removable; 349 + status = "okay"; 350 + }; 351 + 352 + &usdhc3 { 353 + pinctrl-names = "default"; 354 + pinctrl-0 = <&pinctrl_usdhc3>; 355 + bus-width = <8>; 356 + no-1-8-v; 357 + non-removable; 358 + status = "okay"; 359 + }; 360 + 361 + &iomuxc { 362 + pinctrl-names = "default"; 363 + pinctrl-0 = <&pinctrl_hog>; 364 + 365 + pinctrl_hog: hoggrp { 366 + fsl,pins = < 367 + MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x4001b0b5 /* PICO_P24 */ 368 + MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x4001b0b5 /* PICO_P26 */ 369 + MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x4001b0b5 /* PICO_P28 */ 370 + MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x4001b0b5 /* PICO_P30 */ 371 + MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x4001b0b5 /* PICO_P32 */ 372 + MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 0x4001b0b5 /* PICO_P34 */ 373 + MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x4001b0b5 /* PICO_P42 */ 374 + MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x4001b0b5 /* PICO_P44 */ 375 + MX6QDL_PAD_CSI0_DAT15__GPIO6_IO01 0x4001b0b5 /* PICO_P48 */ 376 + >; 377 + }; 378 + 379 + pinctrl_audmux: audmuxgrp { 380 + fsl,pins = < 381 + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 382 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 383 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 384 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 385 + >; 386 + }; 387 + 388 + pinctrl_ecspi1: ecspi1grp { 389 + fsl,pins = < 390 + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 391 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 392 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 393 + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x000f0b0 394 + >; 395 + }; 396 + 397 + pinctrl_ecspi2: ecspi2grp { 398 + fsl,pins = < 399 + MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x1b0b1 400 + MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x1b0b1 401 + MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x1b0b1 402 + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000f0b0 403 + MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x000f0b0 404 + >; 405 + }; 406 + 407 + pinctrl_enet: enetgrp { 408 + fsl,pins = < 409 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 410 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 411 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 412 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 413 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 414 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 415 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 416 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 417 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 418 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 419 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 420 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 421 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 422 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 423 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 424 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 425 + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1f0b1 426 + >; 427 + }; 428 + 429 + pinctrl_flexcan1: flexcan1grp { 430 + fsl,pins = < 431 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 432 + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 433 + >; 434 + }; 435 + 436 + pinctrl_flexcan2: flexcan2grp { 437 + fsl,pins = < 438 + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0 439 + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0 440 + >; 441 + }; 442 + 443 + pinctrl_i2c1: i2c1grp { 444 + fsl,pins = < 445 + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 446 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 447 + >; 448 + }; 449 + 450 + pinctrl_i2c2: i2c2grp { 451 + fsl,pins = < 452 + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 453 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 454 + >; 455 + }; 456 + 457 + pinctrl_i2c3: i2c3grp { 458 + fsl,pins = < 459 + MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 460 + MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 461 + >; 462 + }; 463 + 464 + pinctrl_ipu1: ipu1grp { 465 + fsl,pins = < 466 + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 467 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 468 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 469 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 470 + MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x10 471 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 472 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 473 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 474 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 475 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 476 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 477 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 478 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 479 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 480 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 481 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 482 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 483 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 484 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 485 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 486 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 487 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 488 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 489 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 490 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 491 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 492 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 493 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 494 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 495 + >; 496 + }; 497 + 498 + pinctrl_ov5645: ov5645grp { 499 + fsl,pins = < 500 + MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x0b0b0 501 + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0b0b0 502 + MX6QDL_PAD_GPIO_3__CCM_CLKO2 0x000b0 503 + >; 504 + }; 505 + 506 + pinctrl_pcie_reset: pciegrp { 507 + fsl,pins = < 508 + MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x130b0 509 + >; 510 + }; 511 + 512 + pinctrl_pwm1: pwm1grp { 513 + fsl,pins = < 514 + MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 515 + >; 516 + }; 517 + 518 + pinctrl_pwm2: pwm2grp { 519 + fsl,pins = < 520 + MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1 521 + >; 522 + }; 523 + 524 + pinctrl_pwm3: pwm3grp { 525 + fsl,pins = < 526 + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 527 + >; 528 + }; 529 + 530 + pinctrl_pwm4: pwm4grp { 531 + fsl,pins = < 532 + MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1 533 + >; 534 + }; 535 + 536 + pinctrl_reg_lcd: reglcdgrp { 537 + fsl,pins = < 538 + MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0 539 + >; 540 + }; 541 + 542 + pinctrl_uart1: uart1grp { 543 + fsl,pins = < 544 + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 545 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 546 + >; 547 + }; 548 + 549 + pinctrl_uart2: uart2grp { 550 + fsl,pins = < 551 + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 552 + MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1 553 + MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1 554 + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 555 + >; 556 + }; 557 + 558 + pinctrl_uart3: uart3grp { 559 + fsl,pins = < 560 + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 561 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 562 + MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 563 + MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 564 + >; 565 + }; 566 + 567 + pinctrl_usbotg: usbotggrp { 568 + fsl,pins = < 569 + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 570 + >; 571 + }; 572 + 573 + pinctrl_usbotg_vbus: usbotgvbusgrp { 574 + fsl,pins = < 575 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 576 + >; 577 + }; 578 + 579 + pinctrl_usdhc1: usdhc1grp { 580 + fsl,pins = < 581 + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071 582 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x17071 583 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071 584 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071 585 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071 586 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071 587 + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 588 + >; 589 + }; 590 + 591 + pinctrl_usdhc2: usdhc2grp { 592 + fsl,pins = < 593 + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 594 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 595 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 596 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 597 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 598 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 599 + >; 600 + }; 601 + 602 + pinctrl_usdhc3: usdhc3grp { 603 + fsl,pins = < 604 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 605 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 606 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 607 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 608 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 609 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 610 + MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0xb0b1 611 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 612 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 613 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 614 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 615 + >; 616 + }; 617 + };