tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amdgpu/display: Add gpio support for DCN
GPIOs are used for i2c and other things.
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Harry Wentland
and committed by
Alex Deucher
981ab3f1
061bfa06
+666
+192
drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c
+192
drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c
···
1
+
/*
2
+
* Copyright 2013-15 Advanced Micro Devices, Inc.
3
+
*
4
+
* Permission is hereby granted, free of charge, to any person obtaining a
5
+
* copy of this software and associated documentation files (the "Software"),
6
+
* to deal in the Software without restriction, including without limitation
7
+
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8
+
* and/or sell copies of the Software, and to permit persons to whom the
9
+
* Software is furnished to do so, subject to the following conditions:
10
+
*
11
+
* The above copyright notice and this permission notice shall be included in
12
+
* all copies or substantial portions of the Software.
13
+
*
14
+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15
+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16
+
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17
+
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18
+
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19
+
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20
+
* OTHER DEALINGS IN THE SOFTWARE.
21
+
*
22
+
* Authors: AMD
23
+
*
24
+
*/
25
+
26
+
#include "dm_services.h"
27
+
#include "include/gpio_types.h"
28
+
#include "../hw_factory.h"
29
+
30
+
31
+
#include "../hw_gpio.h"
32
+
#include "../hw_ddc.h"
33
+
#include "../hw_hpd.h"
34
+
35
+
#include "hw_factory_dcn10.h"
36
+
37
+
#include "raven1/DCN/dcn_1_0_offset.h"
38
+
#include "raven1/DCN/dcn_1_0_sh_mask.h"
39
+
#include "vega10/soc15ip.h"
40
+
41
+
#define block HPD
42
+
#define reg_num 0
43
+
44
+
/* set field name */
45
+
#define SF_HPD(reg_name, field_name, post_fix)\
46
+
.field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
47
+
48
+
#define BASE_INNER(seg) \
49
+
DCE_BASE__INST0_SEG ## seg
50
+
51
+
/* compile time expand base address. */
52
+
#define BASE(seg) \
53
+
BASE_INNER(seg)
54
+
55
+
#define REG(reg_name)\
56
+
BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
57
+
58
+
#define REGI(reg_name, block, id)\
59
+
BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
60
+
mm ## block ## id ## _ ## reg_name
61
+
62
+
#include "reg_helper.h"
63
+
#include "../hpd_regs.h"
64
+
65
+
#define hpd_regs(id) \
66
+
{\
67
+
HPD_REG_LIST(id)\
68
+
}
69
+
70
+
static const struct hpd_registers hpd_regs[] = {
71
+
hpd_regs(0),
72
+
hpd_regs(1),
73
+
hpd_regs(2),
74
+
hpd_regs(3),
75
+
hpd_regs(4),
76
+
hpd_regs(5)
77
+
};
78
+
79
+
static const struct hpd_sh_mask hpd_shift = {
80
+
HPD_MASK_SH_LIST(__SHIFT)
81
+
};
82
+
83
+
static const struct hpd_sh_mask hpd_mask = {
84
+
HPD_MASK_SH_LIST(_MASK)
85
+
};
86
+
87
+
#include "../ddc_regs.h"
88
+
89
+
/* set field name */
90
+
#define SF_DDC(reg_name, field_name, post_fix)\
91
+
.field_name = reg_name ## __ ## field_name ## post_fix
92
+
93
+
static const struct ddc_registers ddc_data_regs[] = {
94
+
ddc_data_regs(1),
95
+
ddc_data_regs(2),
96
+
ddc_data_regs(3),
97
+
ddc_data_regs(4),
98
+
ddc_data_regs(5),
99
+
ddc_data_regs(6),
100
+
ddc_vga_data_regs,
101
+
ddc_i2c_data_regs
102
+
};
103
+
104
+
static const struct ddc_registers ddc_clk_regs[] = {
105
+
ddc_clk_regs(1),
106
+
ddc_clk_regs(2),
107
+
ddc_clk_regs(3),
108
+
ddc_clk_regs(4),
109
+
ddc_clk_regs(5),
110
+
ddc_clk_regs(6),
111
+
ddc_vga_clk_regs,
112
+
ddc_i2c_clk_regs
113
+
};
114
+
115
+
static const struct ddc_sh_mask ddc_shift = {
116
+
DDC_MASK_SH_LIST(__SHIFT)
117
+
};
118
+
119
+
static const struct ddc_sh_mask ddc_mask = {
120
+
DDC_MASK_SH_LIST(_MASK)
121
+
};
122
+
123
+
static void define_ddc_registers(
124
+
struct hw_gpio_pin *pin,
125
+
uint32_t en)
126
+
{
127
+
struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin);
128
+
129
+
switch (pin->id) {
130
+
case GPIO_ID_DDC_DATA:
131
+
ddc->regs = &ddc_data_regs[en];
132
+
ddc->base.regs = &ddc_data_regs[en].gpio;
133
+
break;
134
+
case GPIO_ID_DDC_CLOCK:
135
+
ddc->regs = &ddc_clk_regs[en];
136
+
ddc->base.regs = &ddc_clk_regs[en].gpio;
137
+
break;
138
+
default:
139
+
ASSERT_CRITICAL(false);
140
+
return;
141
+
}
142
+
143
+
ddc->shifts = &ddc_shift;
144
+
ddc->masks = &ddc_mask;
145
+
146
+
}
147
+
148
+
static void define_hpd_registers(struct hw_gpio_pin *pin, uint32_t en)
149
+
{
150
+
struct hw_hpd *hpd = HW_HPD_FROM_BASE(pin);
151
+
152
+
hpd->regs = &hpd_regs[en];
153
+
hpd->shifts = &hpd_shift;
154
+
hpd->masks = &hpd_mask;
155
+
hpd->base.regs = &hpd_regs[en].gpio;
156
+
}
157
+
158
+
159
+
/* fucntion table */
160
+
static const struct hw_factory_funcs funcs = {
161
+
.create_ddc_data = dal_hw_ddc_create,
162
+
.create_ddc_clock = dal_hw_ddc_create,
163
+
.create_generic = NULL,
164
+
.create_hpd = dal_hw_hpd_create,
165
+
.create_sync = NULL,
166
+
.create_gsl = NULL,
167
+
.define_hpd_registers = define_hpd_registers,
168
+
.define_ddc_registers = define_ddc_registers
169
+
};
170
+
/*
171
+
* dal_hw_factory_dcn10_init
172
+
*
173
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* @brief
174
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* Initialize HW factory function pointers and pin info
175
+
*
176
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* @param
177
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* struct hw_factory *factory - [out] struct of function pointers
178
+
*/
179
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void dal_hw_factory_dcn10_init(struct hw_factory *factory)
180
+
{
181
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/*TODO check ASIC CAPs*/
182
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factory->number_of_pins[GPIO_ID_DDC_DATA] = 8;
183
+
factory->number_of_pins[GPIO_ID_DDC_CLOCK] = 8;
184
+
factory->number_of_pins[GPIO_ID_GENERIC] = 7;
185
+
factory->number_of_pins[GPIO_ID_HPD] = 6;
186
+
factory->number_of_pins[GPIO_ID_GPIO_PAD] = 31;
187
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factory->number_of_pins[GPIO_ID_VIP_PAD] = 0;
188
+
factory->number_of_pins[GPIO_ID_SYNC] = 2;
189
+
factory->number_of_pins[GPIO_ID_GSL] = 4;
190
+
191
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factory->funcs = &funcs;
192
+
}
+32
drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.h
+32
drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.h
···
1
+
/*
2
+
* Copyright 2013-15 Advanced Micro Devices, Inc.
3
+
*
4
+
* Permission is hereby granted, free of charge, to any person obtaining a
5
+
* copy of this software and associated documentation files (the "Software"),
6
+
* to deal in the Software without restriction, including without limitation
7
+
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8
+
* and/or sell copies of the Software, and to permit persons to whom the
9
+
* Software is furnished to do so, subject to the following conditions:
10
+
*
11
+
* The above copyright notice and this permission notice shall be included in
12
+
* all copies or substantial portions of the Software.
13
+
*
14
+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15
+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16
+
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17
+
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18
+
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19
+
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20
+
* OTHER DEALINGS IN THE SOFTWARE.
21
+
*
22
+
* Authors: AMD
23
+
*
24
+
*/
25
+
26
+
#ifndef __DAL_HW_FACTORY_DCN10_H__
27
+
#define __DAL_HW_FACTORY_DCN10_H__
28
+
29
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/* Initialize HW factory function pointers and pin info */
30
+
void dal_hw_factory_dcn10_init(struct hw_factory *factory);
31
+
32
+
#endif /* __DAL_HW_FACTORY_DCN10_H__ */
+408
drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c
+408
drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c
···
1
+
/*
2
+
* Copyright 2013-15 Advanced Micro Devices, Inc.
3
+
*
4
+
* Permission is hereby granted, free of charge, to any person obtaining a
5
+
* copy of this software and associated documentation files (the "Software"),
6
+
* to deal in the Software without restriction, including without limitation
7
+
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8
+
* and/or sell copies of the Software, and to permit persons to whom the
9
+
* Software is furnished to do so, subject to the following conditions:
10
+
*
11
+
* The above copyright notice and this permission notice shall be included in
12
+
* all copies or substantial portions of the Software.
13
+
*
14
+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15
+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16
+
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17
+
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18
+
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19
+
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20
+
* OTHER DEALINGS IN THE SOFTWARE.
21
+
*
22
+
* Authors: AMD
23
+
*
24
+
*/
25
+
26
+
/*
27
+
* Pre-requisites: headers required by header of this unit
28
+
*/
29
+
30
+
#include "hw_translate_dcn10.h"
31
+
32
+
#include "dm_services.h"
33
+
#include "include/gpio_types.h"
34
+
#include "../hw_translate.h"
35
+
36
+
#include "raven1/DCN/dcn_1_0_offset.h"
37
+
#include "raven1/DCN/dcn_1_0_sh_mask.h"
38
+
#include "vega10/soc15ip.h"
39
+
40
+
/* begin *********************
41
+
* macros to expend register list macro defined in HW object header file */
42
+
43
+
#define BASE_INNER(seg) \
44
+
DCE_BASE__INST0_SEG ## seg
45
+
46
+
/* compile time expand base address. */
47
+
#define BASE(seg) \
48
+
BASE_INNER(seg)
49
+
50
+
#define REG(reg_name)\
51
+
BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
52
+
53
+
#define REGI(reg_name, block, id)\
54
+
BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
55
+
mm ## block ## id ## _ ## reg_name
56
+
57
+
/* macros to expend register list macro defined in HW object header file
58
+
* end *********************/
59
+
60
+
static bool offset_to_id(
61
+
uint32_t offset,
62
+
uint32_t mask,
63
+
enum gpio_id *id,
64
+
uint32_t *en)
65
+
{
66
+
switch (offset) {
67
+
/* GENERIC */
68
+
case REG(DC_GPIO_GENERIC_A):
69
+
*id = GPIO_ID_GENERIC;
70
+
switch (mask) {
71
+
case DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK:
72
+
*en = GPIO_GENERIC_A;
73
+
return true;
74
+
case DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK:
75
+
*en = GPIO_GENERIC_B;
76
+
return true;
77
+
case DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK:
78
+
*en = GPIO_GENERIC_C;
79
+
return true;
80
+
case DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK:
81
+
*en = GPIO_GENERIC_D;
82
+
return true;
83
+
case DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK:
84
+
*en = GPIO_GENERIC_E;
85
+
return true;
86
+
case DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK:
87
+
*en = GPIO_GENERIC_F;
88
+
return true;
89
+
case DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK:
90
+
*en = GPIO_GENERIC_G;
91
+
return true;
92
+
default:
93
+
ASSERT_CRITICAL(false);
94
+
return false;
95
+
}
96
+
break;
97
+
/* HPD */
98
+
case REG(DC_GPIO_HPD_A):
99
+
*id = GPIO_ID_HPD;
100
+
switch (mask) {
101
+
case DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK:
102
+
*en = GPIO_HPD_1;
103
+
return true;
104
+
case DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK:
105
+
*en = GPIO_HPD_2;
106
+
return true;
107
+
case DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK:
108
+
*en = GPIO_HPD_3;
109
+
return true;
110
+
case DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK:
111
+
*en = GPIO_HPD_4;
112
+
return true;
113
+
case DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK:
114
+
*en = GPIO_HPD_5;
115
+
return true;
116
+
case DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK:
117
+
*en = GPIO_HPD_6;
118
+
return true;
119
+
default:
120
+
ASSERT_CRITICAL(false);
121
+
return false;
122
+
}
123
+
break;
124
+
/* SYNCA */
125
+
case REG(DC_GPIO_SYNCA_A):
126
+
*id = GPIO_ID_SYNC;
127
+
switch (mask) {
128
+
case DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A_MASK:
129
+
*en = GPIO_SYNC_HSYNC_A;
130
+
return true;
131
+
case DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A_MASK:
132
+
*en = GPIO_SYNC_VSYNC_A;
133
+
return true;
134
+
default:
135
+
ASSERT_CRITICAL(false);
136
+
return false;
137
+
}
138
+
break;
139
+
/* REG(DC_GPIO_GENLK_MASK */
140
+
case REG(DC_GPIO_GENLK_A):
141
+
*id = GPIO_ID_GSL;
142
+
switch (mask) {
143
+
case DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK:
144
+
*en = GPIO_GSL_GENLOCK_CLOCK;
145
+
return true;
146
+
case DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK:
147
+
*en = GPIO_GSL_GENLOCK_VSYNC;
148
+
return true;
149
+
case DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK:
150
+
*en = GPIO_GSL_SWAPLOCK_A;
151
+
return true;
152
+
case DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK:
153
+
*en = GPIO_GSL_SWAPLOCK_B;
154
+
return true;
155
+
default:
156
+
ASSERT_CRITICAL(false);
157
+
return false;
158
+
}
159
+
break;
160
+
/* DDC */
161
+
/* we don't care about the GPIO_ID for DDC
162
+
* in DdcHandle it will use GPIO_ID_DDC_DATA/GPIO_ID_DDC_CLOCK
163
+
* directly in the create method */
164
+
case REG(DC_GPIO_DDC1_A):
165
+
*en = GPIO_DDC_LINE_DDC1;
166
+
return true;
167
+
case REG(DC_GPIO_DDC2_A):
168
+
*en = GPIO_DDC_LINE_DDC2;
169
+
return true;
170
+
case REG(DC_GPIO_DDC3_A):
171
+
*en = GPIO_DDC_LINE_DDC3;
172
+
return true;
173
+
case REG(DC_GPIO_DDC4_A):
174
+
*en = GPIO_DDC_LINE_DDC4;
175
+
return true;
176
+
case REG(DC_GPIO_DDC5_A):
177
+
*en = GPIO_DDC_LINE_DDC5;
178
+
return true;
179
+
case REG(DC_GPIO_DDC6_A):
180
+
*en = GPIO_DDC_LINE_DDC6;
181
+
return true;
182
+
case REG(DC_GPIO_DDCVGA_A):
183
+
*en = GPIO_DDC_LINE_DDC_VGA;
184
+
return true;
185
+
/* GPIO_I2CPAD */
186
+
case REG(DC_GPIO_I2CPAD_A):
187
+
*en = GPIO_DDC_LINE_I2C_PAD;
188
+
return true;
189
+
/* Not implemented */
190
+
case REG(DC_GPIO_PWRSEQ_A):
191
+
case REG(DC_GPIO_PAD_STRENGTH_1):
192
+
case REG(DC_GPIO_PAD_STRENGTH_2):
193
+
case REG(DC_GPIO_DEBUG):
194
+
return false;
195
+
/* UNEXPECTED */
196
+
default:
197
+
ASSERT_CRITICAL(false);
198
+
return false;
199
+
}
200
+
}
201
+
202
+
static bool id_to_offset(
203
+
enum gpio_id id,
204
+
uint32_t en,
205
+
struct gpio_pin_info *info)
206
+
{
207
+
bool result = true;
208
+
209
+
switch (id) {
210
+
case GPIO_ID_DDC_DATA:
211
+
info->mask = DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A_MASK;
212
+
switch (en) {
213
+
case GPIO_DDC_LINE_DDC1:
214
+
info->offset = REG(DC_GPIO_DDC1_A);
215
+
break;
216
+
case GPIO_DDC_LINE_DDC2:
217
+
info->offset = REG(DC_GPIO_DDC2_A);
218
+
break;
219
+
case GPIO_DDC_LINE_DDC3:
220
+
info->offset = REG(DC_GPIO_DDC3_A);
221
+
break;
222
+
case GPIO_DDC_LINE_DDC4:
223
+
info->offset = REG(DC_GPIO_DDC4_A);
224
+
break;
225
+
case GPIO_DDC_LINE_DDC5:
226
+
info->offset = REG(DC_GPIO_DDC5_A);
227
+
break;
228
+
case GPIO_DDC_LINE_DDC6:
229
+
info->offset = REG(DC_GPIO_DDC6_A);
230
+
break;
231
+
case GPIO_DDC_LINE_DDC_VGA:
232
+
info->offset = REG(DC_GPIO_DDCVGA_A);
233
+
break;
234
+
case GPIO_DDC_LINE_I2C_PAD:
235
+
info->offset = REG(DC_GPIO_I2CPAD_A);
236
+
break;
237
+
default:
238
+
ASSERT_CRITICAL(false);
239
+
result = false;
240
+
}
241
+
break;
242
+
case GPIO_ID_DDC_CLOCK:
243
+
info->mask = DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A_MASK;
244
+
switch (en) {
245
+
case GPIO_DDC_LINE_DDC1:
246
+
info->offset = REG(DC_GPIO_DDC1_A);
247
+
break;
248
+
case GPIO_DDC_LINE_DDC2:
249
+
info->offset = REG(DC_GPIO_DDC2_A);
250
+
break;
251
+
case GPIO_DDC_LINE_DDC3:
252
+
info->offset = REG(DC_GPIO_DDC3_A);
253
+
break;
254
+
case GPIO_DDC_LINE_DDC4:
255
+
info->offset = REG(DC_GPIO_DDC4_A);
256
+
break;
257
+
case GPIO_DDC_LINE_DDC5:
258
+
info->offset = REG(DC_GPIO_DDC5_A);
259
+
break;
260
+
case GPIO_DDC_LINE_DDC6:
261
+
info->offset = REG(DC_GPIO_DDC6_A);
262
+
break;
263
+
case GPIO_DDC_LINE_DDC_VGA:
264
+
info->offset = REG(DC_GPIO_DDCVGA_A);
265
+
break;
266
+
case GPIO_DDC_LINE_I2C_PAD:
267
+
info->offset = REG(DC_GPIO_I2CPAD_A);
268
+
break;
269
+
default:
270
+
ASSERT_CRITICAL(false);
271
+
result = false;
272
+
}
273
+
break;
274
+
case GPIO_ID_GENERIC:
275
+
info->offset = REG(DC_GPIO_GENERIC_A);
276
+
switch (en) {
277
+
case GPIO_GENERIC_A:
278
+
info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK;
279
+
break;
280
+
case GPIO_GENERIC_B:
281
+
info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK;
282
+
break;
283
+
case GPIO_GENERIC_C:
284
+
info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK;
285
+
break;
286
+
case GPIO_GENERIC_D:
287
+
info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK;
288
+
break;
289
+
case GPIO_GENERIC_E:
290
+
info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK;
291
+
break;
292
+
case GPIO_GENERIC_F:
293
+
info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK;
294
+
break;
295
+
case GPIO_GENERIC_G:
296
+
info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK;
297
+
break;
298
+
default:
299
+
ASSERT_CRITICAL(false);
300
+
result = false;
301
+
}
302
+
break;
303
+
case GPIO_ID_HPD:
304
+
info->offset = REG(DC_GPIO_HPD_A);
305
+
switch (en) {
306
+
case GPIO_HPD_1:
307
+
info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK;
308
+
break;
309
+
case GPIO_HPD_2:
310
+
info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK;
311
+
break;
312
+
case GPIO_HPD_3:
313
+
info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK;
314
+
break;
315
+
case GPIO_HPD_4:
316
+
info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK;
317
+
break;
318
+
case GPIO_HPD_5:
319
+
info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK;
320
+
break;
321
+
case GPIO_HPD_6:
322
+
info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK;
323
+
break;
324
+
default:
325
+
ASSERT_CRITICAL(false);
326
+
result = false;
327
+
}
328
+
break;
329
+
case GPIO_ID_SYNC:
330
+
switch (en) {
331
+
case GPIO_SYNC_HSYNC_A:
332
+
info->offset = REG(DC_GPIO_SYNCA_A);
333
+
info->mask = DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A_MASK;
334
+
break;
335
+
case GPIO_SYNC_VSYNC_A:
336
+
info->offset = REG(DC_GPIO_SYNCA_A);
337
+
info->mask = DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A_MASK;
338
+
break;
339
+
case GPIO_SYNC_HSYNC_B:
340
+
case GPIO_SYNC_VSYNC_B:
341
+
default:
342
+
ASSERT_CRITICAL(false);
343
+
result = false;
344
+
}
345
+
break;
346
+
case GPIO_ID_GSL:
347
+
switch (en) {
348
+
case GPIO_GSL_GENLOCK_CLOCK:
349
+
info->offset = REG(DC_GPIO_GENLK_A);
350
+
info->mask = DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK;
351
+
break;
352
+
case GPIO_GSL_GENLOCK_VSYNC:
353
+
info->offset = REG(DC_GPIO_GENLK_A);
354
+
info->mask =
355
+
DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK;
356
+
break;
357
+
case GPIO_GSL_SWAPLOCK_A:
358
+
info->offset = REG(DC_GPIO_GENLK_A);
359
+
info->mask = DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK;
360
+
break;
361
+
case GPIO_GSL_SWAPLOCK_B:
362
+
info->offset = REG(DC_GPIO_GENLK_A);
363
+
info->mask = DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK;
364
+
break;
365
+
default:
366
+
ASSERT_CRITICAL(false);
367
+
result = false;
368
+
}
369
+
break;
370
+
case GPIO_ID_VIP_PAD:
371
+
default:
372
+
ASSERT_CRITICAL(false);
373
+
result = false;
374
+
}
375
+
376
+
if (result) {
377
+
info->offset_y = info->offset + 2;
378
+
info->offset_en = info->offset + 1;
379
+
info->offset_mask = info->offset - 1;
380
+
381
+
info->mask_y = info->mask;
382
+
info->mask_en = info->mask;
383
+
info->mask_mask = info->mask;
384
+
}
385
+
386
+
return result;
387
+
}
388
+
389
+
/* function table */
390
+
static const struct hw_translate_funcs funcs = {
391
+
.offset_to_id = offset_to_id,
392
+
.id_to_offset = id_to_offset,
393
+
};
394
+
395
+
/*
396
+
* dal_hw_translate_dcn10_init
397
+
*
398
+
* @brief
399
+
* Initialize Hw translate function pointers.
400
+
*
401
+
* @param
402
+
* struct hw_translate *tr - [out] struct of function pointers
403
+
*
404
+
*/
405
+
void dal_hw_translate_dcn10_init(struct hw_translate *tr)
406
+
{
407
+
tr->funcs = &funcs;
408
+
}
+34
drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.h
+34
drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.h
···
1
+
/*
2
+
* Copyright 2013-15 Advanced Micro Devices, Inc.
3
+
*
4
+
* Permission is hereby granted, free of charge, to any person obtaining a
5
+
* copy of this software and associated documentation files (the "Software"),
6
+
* to deal in the Software without restriction, including without limitation
7
+
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8
+
* and/or sell copies of the Software, and to permit persons to whom the
9
+
* Software is furnished to do so, subject to the following conditions:
10
+
*
11
+
* The above copyright notice and this permission notice shall be included in
12
+
* all copies or substantial portions of the Software.
13
+
*
14
+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15
+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16
+
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17
+
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18
+
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19
+
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20
+
* OTHER DEALINGS IN THE SOFTWARE.
21
+
*
22
+
* Authors: AMD
23
+
*
24
+
*/
25
+
26
+
#ifndef __DAL_HW_TRANSLATE_DCN10_H__
27
+
#define __DAL_HW_TRANSLATE_DCN10_H__
28
+
29
+
struct hw_translate;
30
+
31
+
/* Initialize Hw translate function pointers */
32
+
void dal_hw_translate_dcn10_init(struct hw_translate *tr);
33
+
34
+
#endif /* __DAL_HW_TRANSLATE_DCN10_H__ */