tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
clk: renesas: rza1: Remove struct rz_cpg
The register block base pointer as stored in the reg member of the
rz_cpg structure is only used during initialization. Hence move
it to a local variable, and pass it as a parameter to
rz_cpg_register_clock().
After this, the data member is the only remaining member of the rz_cpg
structure, so the whole structure can be replaced by the data member.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/2380285576edaa4ad3dc5eca7e0ca418f068c6ef.1654694831.git.geert+renesas@glider.be
+15
-18
+15
-18
drivers/clk/renesas/clk-rz.c
+15
-18
drivers/clk/renesas/clk-rz.c
···
15
15
#include <linux/of_address.h>
16
16
#include <linux/slab.h>
17
17
18
-
struct rz_cpg {
19
-
struct clk_onecell_data data;
20
-
void __iomem *reg;
21
-
};
22
-
23
18
#define CPG_FRQCR 0x10
24
19
#define CPG_FRQCR2 0x14
25
20
···
44
49
}
45
50
46
51
static struct clk * __init
47
-
rz_cpg_register_clock(struct device_node *np, struct rz_cpg *cpg, const char *name)
52
+
rz_cpg_register_clock(struct device_node *np, void __iomem *base,
53
+
const char *name)
48
54
{
49
55
u32 val;
50
56
unsigned mult;
···
61
65
}
62
66
63
67
/* If mapping regs failed, skip non-pll clocks. System will boot anyhow */
64
-
if (!cpg->reg)
68
+
if (!base)
65
69
return ERR_PTR(-ENXIO);
66
70
67
71
/* FIXME:"i" and "g" are variable clocks with non-integer dividers (e.g. 2/3)
···
69
73
* let them run at fixed current speed and implement the details later.
70
74
*/
71
75
if (strcmp(name, "i") == 0)
72
-
val = (readl(cpg->reg + CPG_FRQCR) >> 8) & 3;
76
+
val = (readl(base + CPG_FRQCR) >> 8) & 3;
73
77
else if (strcmp(name, "g") == 0)
74
-
val = readl(cpg->reg + CPG_FRQCR2) & 3;
78
+
val = readl(base + CPG_FRQCR2) & 3;
75
79
else
76
80
return ERR_PTR(-EINVAL);
77
81
···
81
85
82
86
static void __init rz_cpg_clocks_init(struct device_node *np)
83
87
{
84
-
struct rz_cpg *cpg;
88
+
struct clk_onecell_data *data;
85
89
struct clk **clks;
90
+
void __iomem *base;
86
91
unsigned i;
87
92
int num_clks;
88
93
···
91
94
if (WARN(num_clks <= 0, "can't count CPG clocks\n"))
92
95
return;
93
96
94
-
cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
97
+
data = kzalloc(sizeof(*data), GFP_KERNEL);
95
98
clks = kcalloc(num_clks, sizeof(*clks), GFP_KERNEL);
96
-
BUG_ON(!cpg || !clks);
99
+
BUG_ON(!data || !clks);
97
100
98
-
cpg->data.clks = clks;
99
-
cpg->data.clk_num = num_clks;
101
+
data->clks = clks;
102
+
data->clk_num = num_clks;
100
103
101
-
cpg->reg = of_iomap(np, 0);
104
+
base = of_iomap(np, 0);
102
105
103
106
for (i = 0; i < num_clks; ++i) {
104
107
const char *name;
···
106
109
107
110
of_property_read_string_index(np, "clock-output-names", i, &name);
108
111
109
-
clk = rz_cpg_register_clock(np, cpg, name);
112
+
clk = rz_cpg_register_clock(np, base, name);
110
113
if (IS_ERR(clk))
111
114
pr_err("%s: failed to register %pOFn %s clock (%ld)\n",
112
115
__func__, np, name, PTR_ERR(clk));
113
116
else
114
-
cpg->data.clks[i] = clk;
117
+
data->clks[i] = clk;
115
118
}
116
119
117
-
of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
120
+
of_clk_add_provider(np, of_clk_src_onecell_get, data);
118
121
119
122
cpg_mstp_add_clk_domain(np);
120
123
}