Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

drm/i915/cdclk: make struct intel_cdclk_state opaque

With all the code touching struct intel_cdclk_state moved inside
intel_cdclk.c, we move the struct definition there too, and make the
type opaque. This nicely reduces includes from intel_cdclk.h.

Reviewed-by: Imre Deak <imre.deak@intel.com>
Link: https://lore.kernel.org/r/2b58c52e8cbcb66a48ecd4a1453e49dc7bd66289.1750847509.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>

+38 -39
+36
drivers/gpu/drm/i915/display/intel_cdclk.c
··· 114 114 * dividers can be programmed correctly. 115 115 */ 116 116 117 + struct intel_cdclk_state { 118 + struct intel_global_state base; 119 + 120 + /* 121 + * Logical configuration of cdclk (used for all scaling, 122 + * watermark, etc. calculations and checks). This is 123 + * computed as if all enabled crtcs were active. 124 + */ 125 + struct intel_cdclk_config logical; 126 + 127 + /* 128 + * Actual configuration of cdclk, can be different from the 129 + * logical configuration only when all crtc's are DPMS off. 130 + */ 131 + struct intel_cdclk_config actual; 132 + 133 + /* minimum acceptable cdclk to satisfy bandwidth requirements */ 134 + int bw_min_cdclk; 135 + /* minimum acceptable cdclk for each pipe */ 136 + int min_cdclk[I915_MAX_PIPES]; 137 + /* minimum acceptable voltage level for each pipe */ 138 + u8 min_voltage_level[I915_MAX_PIPES]; 139 + 140 + /* pipe to which cd2x update is synchronized */ 141 + enum pipe pipe; 142 + 143 + /* forced minimum cdclk for glk+ audio w/a */ 144 + int force_min_cdclk; 145 + 146 + /* bitmask of active pipes */ 147 + u8 active_pipes; 148 + 149 + /* update cdclk with pipes disabled */ 150 + bool disable_pipes; 151 + }; 152 + 117 153 struct intel_cdclk_funcs { 118 154 void (*get_cdclk)(struct intel_display *display, 119 155 struct intel_cdclk_config *cdclk_config);
+2 -39
drivers/gpu/drm/i915/display/intel_cdclk.h
··· 8 8 9 9 #include <linux/types.h> 10 10 11 - #include "intel_display_limits.h" 12 - #include "intel_global_state.h" 13 - 11 + enum pipe; 14 12 struct intel_atomic_state; 13 + struct intel_cdclk_state; 15 14 struct intel_crtc; 16 15 struct intel_crtc_state; 17 16 struct intel_display; ··· 20 21 u8 voltage_level; 21 22 /* This field is only valid for Xe2LPD and above. */ 22 23 bool joined_mbus; 23 - }; 24 - 25 - struct intel_cdclk_state { 26 - struct intel_global_state base; 27 - 28 - /* 29 - * Logical configuration of cdclk (used for all scaling, 30 - * watermark, etc. calculations and checks). This is 31 - * computed as if all enabled crtcs were active. 32 - */ 33 - struct intel_cdclk_config logical; 34 - 35 - /* 36 - * Actual configuration of cdclk, can be different from the 37 - * logical configuration only when all crtc's are DPMS off. 38 - */ 39 - struct intel_cdclk_config actual; 40 - 41 - /* minimum acceptable cdclk to satisfy bandwidth requirements */ 42 - int bw_min_cdclk; 43 - /* minimum acceptable cdclk for each pipe */ 44 - int min_cdclk[I915_MAX_PIPES]; 45 - /* minimum acceptable voltage level for each pipe */ 46 - u8 min_voltage_level[I915_MAX_PIPES]; 47 - 48 - /* pipe to which cd2x update is synchronized */ 49 - enum pipe pipe; 50 - 51 - /* forced minimum cdclk for glk+ audio w/a */ 52 - int force_min_cdclk; 53 - 54 - /* bitmask of active pipes */ 55 - u8 active_pipes; 56 - 57 - /* update cdclk with pipes disabled */ 58 - bool disable_pipes; 59 24 }; 60 25 61 26 void intel_cdclk_init_hw(struct intel_display *display);