drivers/char/synclink_gt.c: add extended sync feature

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

Add support for extended byte synchronous mode feature of hardware.

Signed-off-by: Paul Fulghum <paulkf@microgate.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>

authored by

Paul Fulghum and committed by

Linus Torvalds 15 years ago 9807224f ed77ed61

+113 -3

2 changed files

expand all

drivers

char

synclink_gt.c

include

linux

synclink.h

+108 -3

drivers/char/synclink_gt.c

··· 301 301 unsigned int rx_pio; 302 302 unsigned int if_mode; 303 303 unsigned int base_clock; 304 + unsigned int xsync; 305 + unsigned int xctrl; 304 306 305 307 /* device status */ 306 308 ··· 407 405 #define TDCSR 0x94 /* tx DMA control/status */ 408 406 #define RDDAR 0x98 /* rx DMA descriptor address */ 409 407 #define TDDAR 0x9c /* tx DMA descriptor address */ 408 + #define XSR 0x40 /* extended sync pattern */ 409 + #define XCR 0x44 /* extended control */ 410 410 411 411 #define RXIDLE BIT14 412 412 #define RXBREAK BIT14 ··· 521 517 static int set_gpio(struct slgt_info *info, struct gpio_desc __user *gpio); 522 518 static int get_gpio(struct slgt_info *info, struct gpio_desc __user *gpio); 523 519 static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *gpio); 520 + static int get_xsync(struct slgt_info *info, int __user *if_mode); 521 + static int set_xsync(struct slgt_info *info, int if_mode); 522 + static int get_xctrl(struct slgt_info *info, int __user *if_mode); 523 + static int set_xctrl(struct slgt_info *info, int if_mode); 524 524 525 525 /* 526 526 * driver functions ··· 1064 1056 return get_gpio(info, argp); 1065 1057 case MGSL_IOCWAITGPIO: 1066 1058 return wait_gpio(info, argp); 1059 + case MGSL_IOCGXSYNC: 1060 + return get_xsync(info, argp); 1061 + case MGSL_IOCSXSYNC: 1062 + return set_xsync(info, (int)arg); 1063 + case MGSL_IOCGXCTRL: 1064 + return get_xctrl(info, argp); 1065 + case MGSL_IOCSXCTRL: 1066 + return set_xctrl(info, (int)arg); 1067 1067 } 1068 1068 mutex_lock(&info->port.mutex); 1069 1069 switch (cmd) { ··· 1229 1213 case MGSL_IOCSGPIO: 1230 1214 case MGSL_IOCGGPIO: 1231 1215 case MGSL_IOCWAITGPIO: 1216 + case MGSL_IOCGXSYNC: 1217 + case MGSL_IOCGXCTRL: 1232 1218 case MGSL_IOCSTXIDLE: 1233 1219 case MGSL_IOCTXENABLE: 1234 1220 case MGSL_IOCRXENABLE: 1235 1221 case MGSL_IOCTXABORT: 1236 1222 case TIOCMIWAIT: 1237 1223 case MGSL_IOCSIF: 1224 + case MGSL_IOCSXSYNC: 1225 + case MGSL_IOCSXCTRL: 1238 1226 rc = ioctl(tty, file, cmd, arg); 1239 1227 break; 1240 1228 } ··· 1981 1961 case MGSL_MODE_RAW: 1982 1962 case MGSL_MODE_MONOSYNC: 1983 1963 case MGSL_MODE_BISYNC: 1964 + case MGSL_MODE_XSYNC: 1984 1965 while(rx_get_buf(info)); 1985 1966 break; 1986 1967 } ··· 2910 2889 return 0; 2911 2890 } 2912 2891 2892 + static int get_xsync(struct slgt_info *info, int __user *xsync) 2893 + { 2894 + DBGINFO(("%s get_xsync=%x\n", info->device_name, info->xsync)); 2895 + if (put_user(info->xsync, xsync)) 2896 + return -EFAULT; 2897 + return 0; 2898 + } 2899 + 2900 + /* 2901 + * set extended sync pattern (1 to 4 bytes) for extended sync mode 2902 + * 2903 + * sync pattern is contained in least significant bytes of value 2904 + * most significant byte of sync pattern is oldest (1st sent/detected) 2905 + */ 2906 + static int set_xsync(struct slgt_info *info, int xsync) 2907 + { 2908 + unsigned long flags; 2909 + 2910 + DBGINFO(("%s set_xsync=%x)\n", info->device_name, xsync)); 2911 + spin_lock_irqsave(&info->lock, flags); 2912 + info->xsync = xsync; 2913 + wr_reg32(info, XSR, xsync); 2914 + spin_unlock_irqrestore(&info->lock, flags); 2915 + return 0; 2916 + } 2917 + 2918 + static int get_xctrl(struct slgt_info *info, int __user *xctrl) 2919 + { 2920 + DBGINFO(("%s get_xctrl=%x\n", info->device_name, info->xctrl)); 2921 + if (put_user(info->xctrl, xctrl)) 2922 + return -EFAULT; 2923 + return 0; 2924 + } 2925 + 2926 + /* 2927 + * set extended control options 2928 + * 2929 + * xctrl[31:19] reserved, must be zero 2930 + * xctrl[18:17] extended sync pattern length in bytes 2931 + * 00 = 1 byte in xsr[7:0] 2932 + * 01 = 2 bytes in xsr[15:0] 2933 + * 10 = 3 bytes in xsr[23:0] 2934 + * 11 = 4 bytes in xsr[31:0] 2935 + * xctrl[16] 1 = enable terminal count, 0=disabled 2936 + * xctrl[15:0] receive terminal count for fixed length packets 2937 + * value is count minus one (0 = 1 byte packet) 2938 + * when terminal count is reached, receiver 2939 + * automatically returns to hunt mode and receive 2940 + * FIFO contents are flushed to DMA buffers with 2941 + * end of frame (EOF) status 2942 + */ 2943 + static int set_xctrl(struct slgt_info *info, int xctrl) 2944 + { 2945 + unsigned long flags; 2946 + 2947 + DBGINFO(("%s set_xctrl=%x)\n", info->device_name, xctrl)); 2948 + spin_lock_irqsave(&info->lock, flags); 2949 + info->xctrl = xctrl; 2950 + wr_reg32(info, XCR, xctrl); 2951 + spin_unlock_irqrestore(&info->lock, flags); 2952 + return 0; 2953 + } 2954 + 2913 2955 /* 2914 2956 * set general purpose IO pin state and direction 2915 2957 * ··· 3852 3768 #define CALC_REGADDR() \ 3853 3769 unsigned long reg_addr = ((unsigned long)info->reg_addr) + addr; \ 3854 3770 if (addr >= 0x80) \ 3855 - reg_addr += (info->port_num) * 32; 3771 + reg_addr += (info->port_num) * 32; \ 3772 + else if (addr >= 0x40) \ 3773 + reg_addr += (info->port_num) * 16; 3856 3774 3857 3775 static __u8 rd_reg8(struct slgt_info *info, unsigned int addr) 3858 3776 { ··· 4273 4187 4274 4188 /* TCR (tx control) 4275 4189 * 4276 - * 15..13 mode, 000=HDLC 001=raw 010=async 011=monosync 100=bisync 4190 + * 15..13 mode 4191 + * 000=HDLC/SDLC 4192 + * 001=raw bit synchronous 4193 + * 010=asynchronous/isochronous 4194 + * 011=monosync byte synchronous 4195 + * 100=bisync byte synchronous 4196 + * 101=xsync byte synchronous 4277 4197 * 12..10 encoding 4278 4198 * 09 CRC enable 4279 4199 * 08 CRC32 ··· 4294 4202 val = BIT2; 4295 4203 4296 4204 switch(info->params.mode) { 4205 + case MGSL_MODE_XSYNC: 4206 + val |= BIT15 + BIT13; 4207 + break; 4297 4208 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break; 4298 4209 case MGSL_MODE_BISYNC: val |= BIT15; break; 4299 4210 case MGSL_MODE_RAW: val |= BIT13; break; ··· 4351 4256 4352 4257 /* RCR (rx control) 4353 4258 * 4354 - * 15..13 mode, 000=HDLC 001=raw 010=async 011=monosync 100=bisync 4259 + * 15..13 mode 4260 + * 000=HDLC/SDLC 4261 + * 001=raw bit synchronous 4262 + * 010=asynchronous/isochronous 4263 + * 011=monosync byte synchronous 4264 + * 100=bisync byte synchronous 4265 + * 101=xsync byte synchronous 4355 4266 * 12..10 encoding 4356 4267 * 09 CRC enable 4357 4268 * 08 CRC32 ··· 4369 4268 val = 0; 4370 4269 4371 4270 switch(info->params.mode) { 4271 + case MGSL_MODE_XSYNC: 4272 + val |= BIT15 + BIT13; 4273 + break; 4372 4274 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break; 4373 4275 case MGSL_MODE_BISYNC: val |= BIT15; break; 4374 4276 case MGSL_MODE_RAW: val |= BIT13; break; ··· 4788 4684 switch(info->params.mode) { 4789 4685 case MGSL_MODE_MONOSYNC: 4790 4686 case MGSL_MODE_BISYNC: 4687 + case MGSL_MODE_XSYNC: 4791 4688 /* ignore residue in byte synchronous modes */ 4792 4689 if (desc_residue(info->rbufs[i])) 4793 4690 count--;

include/linux/synclink.h

··· 126 126 #define MGSL_MODE_BISYNC 4 127 127 #define MGSL_MODE_RAW 6 128 128 #define MGSL_MODE_BASE_CLOCK 7 129 + #define MGSL_MODE_XSYNC 8 129 130 130 131 #define MGSL_BUS_TYPE_ISA 1 131 132 #define MGSL_BUS_TYPE_EISA 2 ··· 291 290 #define MGSL_IOCSGPIO _IOW(MGSL_MAGIC_IOC,16,struct gpio_desc) 292 291 #define MGSL_IOCGGPIO _IOR(MGSL_MAGIC_IOC,17,struct gpio_desc) 293 292 #define MGSL_IOCWAITGPIO _IOWR(MGSL_MAGIC_IOC,18,struct gpio_desc) 293 + #define MGSL_IOCSXSYNC _IO(MGSL_MAGIC_IOC, 19) 294 + #define MGSL_IOCGXSYNC _IO(MGSL_MAGIC_IOC, 20) 295 + #define MGSL_IOCSXCTRL _IO(MGSL_MAGIC_IOC, 21) 296 + #define MGSL_IOCGXCTRL _IO(MGSL_MAGIC_IOC, 22) 294 297 295 298 #ifdef __KERNEL__ 296 299 /* provide 32 bit ioctl compatibility on 64 bit systems */