tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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[MIPS] Define MIPS_CPU_IRQ_BASE in generic header

The irq_base for {mips,rm7k,rm9k}_cpu_irq_init() are constant on all
platforms and are same value on most platforms (0 or 16, depends on
CONFIG_I8259). Define them in asm-mips/mach-generic/irq.h and make
them customizable. This will save a few cycle on each CPU interrupt.

A good side effect is removing some dependencies to MALTA in generic
SMTC code.

Although MIPS_CPU_IRQ_BASE is customizable, this patch changes irq
mappings on DDB5477, EMMA2RH and MIPS_SIM, since really customizing
them might cause some header dependency problem and there seems no
good reason to customize it. So currently only VR41XX is using custom
MIPS_CPU_IRQ_BASE value, which is 0 regardless of CONFIG_I8259.

Testing this patch on those platforms is greatly appreciated. Thank
you.

Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

authored by

Atsushi Nemoto and committed by
Ralf Baechle 97dcb82d b6ec8f06

+128 -98
+3 -3
arch/mips/basler/excite/excite_irq.c
··· 47 47 */ 48 48 void __init arch_init_irq(void) 49 49 { 50 - mips_cpu_irq_init(0); 51 - rm7k_cpu_irq_init(8); 52 - rm9k_cpu_irq_init(12); 50 + mips_cpu_irq_init(); 51 + rm7k_cpu_irq_init(); 52 + rm9k_cpu_irq_init(); 53 53 54 54 #ifdef CONFIG_KGDB 55 55 excite_kgdb_init();
+1 -1
arch/mips/cobalt/irq.c
··· 104 104 GT_WRITE(GT_INTRMASK_OFS, 0); 105 105 106 106 init_i8259_irqs(); /* 0 ... 15 */ 107 - mips_cpu_irq_init(COBALT_CPU_IRQ); /* 16 ... 23 */ 107 + mips_cpu_irq_init(); /* 16 ... 23 */ 108 108 109 109 /* 110 110 * Mask all cpu interrupts
+2 -2
arch/mips/ddb5xxx/ddb5477/irq.c
··· 17 17 #include <linux/ptrace.h> 18 18 19 19 #include <asm/i8259.h> 20 + #include <asm/irq_cpu.h> 20 21 #include <asm/system.h> 21 22 #include <asm/mipsregs.h> 22 23 #include <asm/debug.h> ··· 74 73 } 75 74 76 75 extern void vrc5477_irq_init(u32 base); 77 - extern void mips_cpu_irq_init(u32 base); 78 76 static struct irqaction irq_cascade = { no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL }; 79 77 80 78 void __init arch_init_irq(void) ··· 125 125 126 126 /* init all controllers */ 127 127 init_i8259_irqs(); 128 - mips_cpu_irq_init(CPU_IRQ_BASE); 128 + mips_cpu_irq_init(); 129 129 vrc5477_irq_init(VRC5477_IRQ_BASE); 130 130 131 131
+6 -6
arch/mips/dec/setup.c
··· 234 234 memcpy(&cpu_mask_nr_tbl, &kn01_cpu_mask_nr_tbl, 235 235 sizeof(kn01_cpu_mask_nr_tbl)); 236 236 237 - mips_cpu_irq_init(DEC_CPU_IRQ_BASE); 237 + mips_cpu_irq_init(); 238 238 239 239 } /* dec_init_kn01 */ 240 240 ··· 309 309 memcpy(&cpu_mask_nr_tbl, &kn230_cpu_mask_nr_tbl, 310 310 sizeof(kn230_cpu_mask_nr_tbl)); 311 311 312 - mips_cpu_irq_init(DEC_CPU_IRQ_BASE); 312 + mips_cpu_irq_init(); 313 313 314 314 } /* dec_init_kn230 */ 315 315 ··· 403 403 memcpy(&asic_mask_nr_tbl, &kn02_asic_mask_nr_tbl, 404 404 sizeof(kn02_asic_mask_nr_tbl)); 405 405 406 - mips_cpu_irq_init(DEC_CPU_IRQ_BASE); 406 + mips_cpu_irq_init(); 407 407 init_kn02_irqs(KN02_IRQ_BASE); 408 408 409 409 } /* dec_init_kn02 */ ··· 504 504 memcpy(&asic_mask_nr_tbl, &kn02ba_asic_mask_nr_tbl, 505 505 sizeof(kn02ba_asic_mask_nr_tbl)); 506 506 507 - mips_cpu_irq_init(DEC_CPU_IRQ_BASE); 507 + mips_cpu_irq_init(); 508 508 init_ioasic_irqs(IO_IRQ_BASE); 509 509 510 510 } /* dec_init_kn02ba */ ··· 601 601 memcpy(&asic_mask_nr_tbl, &kn02ca_asic_mask_nr_tbl, 602 602 sizeof(kn02ca_asic_mask_nr_tbl)); 603 603 604 - mips_cpu_irq_init(DEC_CPU_IRQ_BASE); 604 + mips_cpu_irq_init(); 605 605 init_ioasic_irqs(IO_IRQ_BASE); 606 606 607 607 } /* dec_init_kn02ca */ ··· 702 702 memcpy(&asic_mask_nr_tbl, &kn03_asic_mask_nr_tbl, 703 703 sizeof(kn03_asic_mask_nr_tbl)); 704 704 705 - mips_cpu_irq_init(DEC_CPU_IRQ_BASE); 705 + mips_cpu_irq_init(); 706 706 init_ioasic_irqs(IO_IRQ_BASE); 707 707 708 708 } /* dec_init_kn03 */
+1 -1
arch/mips/emma2rh/markeins/irq.c
··· 106 106 emma2rh_irq_init(EMMA2RH_IRQ_BASE); 107 107 emma2rh_sw_irq_init(EMMA2RH_SW_IRQ_BASE); 108 108 emma2rh_gpio_irq_init(EMMA2RH_GPIO_IRQ_BASE); 109 - mips_cpu_irq_init(CPU_IRQ_BASE); 109 + mips_cpu_irq_init(); 110 110 111 111 /* setup cascade interrupts */ 112 112 setup_irq(EMMA2RH_IRQ_BASE + EMMA2RH_SW_CASCADE, &irq_cascade);
+2 -2
arch/mips/gt64120/momenco_ocelot/irq.c
··· 90 90 clear_c0_status(ST0_IM); 91 91 local_irq_disable(); 92 92 93 - mips_cpu_irq_init(0); 94 - rm7k_cpu_irq_init(8); 93 + mips_cpu_irq_init(); 94 + rm7k_cpu_irq_init(); 95 95 }
+1 -1
arch/mips/gt64120/wrppmc/irq.c
··· 63 63 void __init arch_init_irq(void) 64 64 { 65 65 /* IRQ 0 - 7 are for MIPS common irq_cpu controller */ 66 - mips_cpu_irq_init(0); 66 + mips_cpu_irq_init(); 67 67 68 68 gt64120_init_pic(); 69 69 }
+4 -7
arch/mips/kernel/irq-rm7000.c
··· 17 17 #include <asm/mipsregs.h> 18 18 #include <asm/system.h> 19 19 20 - static int irq_base; 21 - 22 20 static inline void unmask_rm7k_irq(unsigned int irq) 23 21 { 24 - set_c0_intcontrol(0x100 << (irq - irq_base)); 22 + set_c0_intcontrol(0x100 << (irq - RM7K_CPU_IRQ_BASE)); 25 23 } 26 24 27 25 static inline void mask_rm7k_irq(unsigned int irq) 28 26 { 29 - clear_c0_intcontrol(0x100 << (irq - irq_base)); 27 + clear_c0_intcontrol(0x100 << (irq - RM7K_CPU_IRQ_BASE)); 30 28 } 31 29 32 30 static struct irq_chip rm7k_irq_controller = { ··· 35 37 .unmask = unmask_rm7k_irq, 36 38 }; 37 39 38 - void __init rm7k_cpu_irq_init(int base) 40 + void __init rm7k_cpu_irq_init(void) 39 41 { 42 + int base = RM7K_CPU_IRQ_BASE; 40 43 int i; 41 44 42 45 clear_c0_intcontrol(0x00000f00); /* Mask all */ ··· 45 46 for (i = base; i < base + 4; i++) 46 47 set_irq_chip_and_handler(i, &rm7k_irq_controller, 47 48 handle_level_irq); 48 - 49 - irq_base = base; 50 49 }
+4 -7
arch/mips/kernel/irq-rm9000.c
··· 18 18 #include <asm/mipsregs.h> 19 19 #include <asm/system.h> 20 20 21 - static int irq_base; 22 - 23 21 static inline void unmask_rm9k_irq(unsigned int irq) 24 22 { 25 - set_c0_intcontrol(0x1000 << (irq - irq_base)); 23 + set_c0_intcontrol(0x1000 << (irq - RM9K_CPU_IRQ_BASE)); 26 24 } 27 25 28 26 static inline void mask_rm9k_irq(unsigned int irq) 29 27 { 30 - clear_c0_intcontrol(0x1000 << (irq - irq_base)); 28 + clear_c0_intcontrol(0x1000 << (irq - RM9K_CPU_IRQ_BASE)); 31 29 } 32 30 33 31 static inline void rm9k_cpu_irq_enable(unsigned int irq) ··· 91 93 92 94 EXPORT_SYMBOL(rm9000_perfcount_irq); 93 95 94 - void __init rm9k_cpu_irq_init(int base) 96 + void __init rm9k_cpu_irq_init(void) 95 97 { 98 + int base = RM9K_CPU_IRQ_BASE; 96 99 int i; 97 100 98 101 clear_c0_intcontrol(0x0000f000); /* Mask all */ ··· 105 106 rm9000_perfcount_irq = base + 1; 106 107 set_irq_chip_and_handler(rm9000_perfcount_irq, &rm9k_perfcounter_irq, 107 108 handle_level_irq); 108 - 109 - irq_base = base; 110 109 }
+7 -10
arch/mips/kernel/irq_cpu.c
··· 25 25 * Don't even think about using this on SMP. You have been warned. 26 26 * 27 27 * This file exports one global function: 28 - * void mips_cpu_irq_init(int irq_base); 28 + * void mips_cpu_irq_init(void); 29 29 */ 30 30 #include <linux/init.h> 31 31 #include <linux/interrupt.h> ··· 36 36 #include <asm/mipsmtregs.h> 37 37 #include <asm/system.h> 38 38 39 - static int mips_cpu_irq_base; 40 - 41 39 static inline void unmask_mips_irq(unsigned int irq) 42 40 { 43 - set_c0_status(0x100 << (irq - mips_cpu_irq_base)); 41 + set_c0_status(0x100 << (irq - MIPS_CPU_IRQ_BASE)); 44 42 irq_enable_hazard(); 45 43 } 46 44 47 45 static inline void mask_mips_irq(unsigned int irq) 48 46 { 49 - clear_c0_status(0x100 << (irq - mips_cpu_irq_base)); 47 + clear_c0_status(0x100 << (irq - MIPS_CPU_IRQ_BASE)); 50 48 irq_disable_hazard(); 51 49 } 52 50 ··· 68 70 { 69 71 unsigned int vpflags = dvpe(); 70 72 71 - clear_c0_cause(0x100 << (irq - mips_cpu_irq_base)); 73 + clear_c0_cause(0x100 << (irq - MIPS_CPU_IRQ_BASE)); 72 74 evpe(vpflags); 73 75 unmask_mips_mt_irq(irq); 74 76 ··· 82 84 static void mips_mt_cpu_irq_ack(unsigned int irq) 83 85 { 84 86 unsigned int vpflags = dvpe(); 85 - clear_c0_cause(0x100 << (irq - mips_cpu_irq_base)); 87 + clear_c0_cause(0x100 << (irq - MIPS_CPU_IRQ_BASE)); 86 88 evpe(vpflags); 87 89 mask_mips_mt_irq(irq); 88 90 } ··· 97 99 .eoi = unmask_mips_mt_irq, 98 100 }; 99 101 100 - void __init mips_cpu_irq_init(int irq_base) 102 + void __init mips_cpu_irq_init(void) 101 103 { 104 + int irq_base = MIPS_CPU_IRQ_BASE; 102 105 int i; 103 106 104 107 /* Mask interrupts. */ ··· 117 118 for (i = irq_base + 2; i < irq_base + 8; i++) 118 119 set_irq_chip_and_handler(i, &mips_cpu_irq_controller, 119 120 handle_level_irq); 120 - 121 - mips_cpu_irq_base = irq_base; 122 121 }
+2 -2
arch/mips/kernel/rtlx.c
··· 63 63 64 64 static void rtlx_dispatch(void) 65 65 { 66 - do_IRQ(MIPSCPU_INT_BASE + MIPS_CPU_RTLX_IRQ); 66 + do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_RTLX_IRQ); 67 67 } 68 68 69 69 ··· 491 491 .name = "RTLX", 492 492 }; 493 493 494 - static int rtlx_irq_num = MIPSCPU_INT_BASE + MIPS_CPU_RTLX_IRQ; 494 + static int rtlx_irq_num = MIPS_CPU_IRQ_BASE + MIPS_CPU_RTLX_IRQ; 495 495 496 496 static char register_chrdev_failed[] __initdata = 497 497 KERN_ERR "rtlx_module_init: unable to register device\n";
+4 -5
arch/mips/kernel/smp-mt.c
··· 35 35 #include <asm/mipsregs.h> 36 36 #include <asm/mipsmtregs.h> 37 37 #include <asm/mips_mt.h> 38 - #include <asm/mips-boards/maltaint.h> /* This is f*cking wrong */ 39 38 40 39 #define MIPS_CPU_IPI_RESCHED_IRQ 0 41 40 #define MIPS_CPU_IPI_CALL_IRQ 1 ··· 107 108 108 109 static void ipi_resched_dispatch(void) 109 110 { 110 - do_IRQ(MIPSCPU_INT_BASE + MIPS_CPU_IPI_RESCHED_IRQ); 111 + do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ); 111 112 } 112 113 113 114 static void ipi_call_dispatch(void) 114 115 { 115 - do_IRQ(MIPSCPU_INT_BASE + MIPS_CPU_IPI_CALL_IRQ); 116 + do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ); 116 117 } 117 118 118 119 static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id) ··· 269 270 set_vi_handler(MIPS_CPU_IPI_CALL_IRQ, ipi_call_dispatch); 270 271 } 271 272 272 - cpu_ipi_resched_irq = MIPSCPU_INT_BASE + MIPS_CPU_IPI_RESCHED_IRQ; 273 - cpu_ipi_call_irq = MIPSCPU_INT_BASE + MIPS_CPU_IPI_CALL_IRQ; 273 + cpu_ipi_resched_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ; 274 + cpu_ipi_call_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ; 274 275 275 276 setup_irq(cpu_ipi_resched_irq, &irq_resched); 276 277 setup_irq(cpu_ipi_call_irq, &irq_call);
+1 -11
arch/mips/kernel/smtc.c
··· 26 26 * This file should be built into the kernel only if CONFIG_MIPS_MT_SMTC is set. 27 27 */ 28 28 29 - /* 30 - * MIPSCPU_INT_BASE is identically defined in both 31 - * asm-mips/mips-boards/maltaint.h and asm-mips/mips-boards/simint.h, 32 - * but as yet there's no properly organized include structure that 33 - * will ensure that the right *int.h file will be included for a 34 - * given platform build. 35 - */ 36 - 37 - #define MIPSCPU_INT_BASE 16 38 - 39 29 #define MIPS_CPU_IPI_IRQ 1 40 30 41 31 #define LOCK_MT_PRA() \ ··· 911 921 * interrupts. 912 922 */ 913 923 914 - static int cpu_ipi_irq = MIPSCPU_INT_BASE + MIPS_CPU_IPI_IRQ; 924 + static int cpu_ipi_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_IRQ; 915 925 916 926 static irqreturn_t ipi_interrupt(int irq, void *dev_idm) 917 927 {
+1 -1
arch/mips/mips-boards/atlas/atlas_int.c
··· 238 238 init_atlas_irqs(ATLAS_INT_BASE); 239 239 240 240 if (!cpu_has_veic) 241 - mips_cpu_irq_init(MIPSCPU_INT_BASE); 241 + mips_cpu_irq_init(); 242 242 243 243 switch(mips_revision_corid) { 244 244 case MIPS_REVISION_CORID_CORE_MSC:
+1 -1
arch/mips/mips-boards/malta/malta_int.c
··· 310 310 init_i8259_irqs(); 311 311 312 312 if (!cpu_has_veic) 313 - mips_cpu_irq_init (MIPSCPU_INT_BASE); 313 + mips_cpu_irq_init(); 314 314 315 315 switch(mips_revision_corid) { 316 316 case MIPS_REVISION_CORID_CORE_MSC:
+1 -1
arch/mips/mips-boards/sead/sead_int.c
··· 113 113 114 114 void __init arch_init_irq(void) 115 115 { 116 - mips_cpu_irq_init(MIPSCPU_INT_BASE); 116 + mips_cpu_irq_init(); 117 117 }
+2 -4
arch/mips/mips-boards/sim/sim_int.c
··· 21 21 #include <linux/interrupt.h> 22 22 #include <linux/kernel_stat.h> 23 23 #include <asm/mips-boards/simint.h> 24 - 25 - 26 - extern void mips_cpu_irq_init(int); 24 + #include <asm/irq_cpu.h> 27 25 28 26 static inline int clz(unsigned long x) 29 27 { ··· 84 86 85 87 void __init arch_init_irq(void) 86 88 { 87 - mips_cpu_irq_init(MIPSCPU_INT_BASE); 89 + mips_cpu_irq_init(); 88 90 }
+2 -2
arch/mips/momentum/jaguar_atx/irq.c
··· 82 82 */ 83 83 clear_c0_status(ST0_IM); 84 84 85 - mips_cpu_irq_init(0); 86 - rm7k_cpu_irq_init(8); 85 + mips_cpu_irq_init(); 86 + rm7k_cpu_irq_init(); 87 87 88 88 /* set up the cascading interrupts */ 89 89 setup_irq(8, &cascade_mv64340);
+1 -1
arch/mips/momentum/ocelot_3/irq.c
··· 65 65 */ 66 66 clear_c0_status(ST0_IM | ST0_BEV); 67 67 68 - rm7k_cpu_irq_init(8); 68 + rm7k_cpu_irq_init(); 69 69 70 70 /* set up the cascading interrupts */ 71 71 setup_irq(8, &cascade_mv64340); /* unmask intControl IM8, IRQ 9 */
+1 -1
arch/mips/momentum/ocelot_c/irq.c
··· 94 94 */ 95 95 clear_c0_status(ST0_IM); 96 96 97 - mips_cpu_irq_init(0); 97 + mips_cpu_irq_init(); 98 98 99 99 /* set up the cascading interrupts */ 100 100 setup_irq(3, &cascade_fpga);
+2 -2
arch/mips/momentum/ocelot_g/irq.c
··· 94 94 clear_c0_status(ST0_IM); 95 95 local_irq_disable(); 96 96 97 - mips_cpu_irq_init(0); 98 - rm7k_cpu_irq_init(8); 97 + mips_cpu_irq_init(); 98 + rm7k_cpu_irq_init(); 99 99 100 100 gt64240_irq_init(); 101 101 }
+3 -3
arch/mips/pmc-sierra/yosemite/irq.c
··· 148 148 { 149 149 clear_c0_status(ST0_IM); 150 150 151 - mips_cpu_irq_init(0); 152 - rm7k_cpu_irq_init(8); 153 - rm9k_cpu_irq_init(12); 151 + mips_cpu_irq_init(); 152 + rm7k_cpu_irq_init(); 153 + rm9k_cpu_irq_init(); 154 154 155 155 #ifdef CONFIG_KGDB 156 156 /* At this point, initialize the second serial port */
+2 -3
arch/mips/sgi-ip22/ip22-int.c
··· 19 19 20 20 #include <asm/mipsregs.h> 21 21 #include <asm/addrspace.h> 22 + #include <asm/irq_cpu.h> 22 23 23 24 #include <asm/sgi/ioc.h> 24 25 #include <asm/sgi/hpc3.h> ··· 254 253 indy_8254timer_irq(); 255 254 } 256 255 257 - extern void mips_cpu_irq_init(unsigned int irq_base); 258 - 259 256 void __init arch_init_irq(void) 260 257 { 261 258 int i; ··· 315 316 sgint->cmeimask1 = 0; 316 317 317 318 /* init CPU irqs */ 318 - mips_cpu_irq_init(SGINT_CPU); 319 + mips_cpu_irq_init(); 319 320 320 321 for (i = SGINT_LOCAL0; i < SGI_INTERRUPTS; i++) { 321 322 struct irq_chip *handler;
+1 -1
arch/mips/vr41xx/common/irq.c
··· 117 117 118 118 void __init arch_init_irq(void) 119 119 { 120 - mips_cpu_irq_init(MIPS_CPU_IRQ_BASE); 120 + mips_cpu_irq_init(); 121 121 }
+3 -2
include/asm-mips/ddb5xxx/ddb5477.h
··· 17 17 #ifndef __ASM_DDB5XXX_DDB5477_H 18 18 #define __ASM_DDB5XXX_DDB5477_H 19 19 20 + #include <irq.h> 20 21 21 22 /* 22 23 * This contains macros that are specific to DDB5477 or renamed from ··· 258 257 #define DDB_IRQ_BASE 0 259 258 260 259 #define I8259_IRQ_BASE DDB_IRQ_BASE 261 - #define VRC5477_IRQ_BASE (I8259_IRQ_BASE + NUM_I8259_IRQ) 262 - #define CPU_IRQ_BASE (VRC5477_IRQ_BASE + NUM_VRC5477_IRQ) 260 + #define CPU_IRQ_BASE MIPS_CPU_IRQ_BASE 261 + #define VRC5477_IRQ_BASE (CPU_IRQ_BASE + NUM_CPU_IRQ) 263 262 264 263 /* 265 264 * vrc5477 irq defs
+2 -1
include/asm-mips/dec/interrupts.h
··· 14 14 #ifndef __ASM_DEC_INTERRUPTS_H 15 15 #define __ASM_DEC_INTERRUPTS_H 16 16 17 + #include <irq.h> 17 18 #include <asm/mipsregs.h> 18 19 19 20 ··· 88 87 #define DEC_CPU_INR_SW1 1 /* software #1 */ 89 88 #define DEC_CPU_INR_SW0 0 /* software #0 */ 90 89 91 - #define DEC_CPU_IRQ_BASE 0 /* first IRQ assigned to CPU */ 90 + #define DEC_CPU_IRQ_BASE MIPS_CPU_IRQ_BASE /* first IRQ assigned to CPU */ 92 91 93 92 #define DEC_CPU_IRQ_NR(n) ((n) + DEC_CPU_IRQ_BASE) 94 93 #define DEC_CPU_IRQ_MASK(n) (1 << ((n) + CAUSEB_IP))
+4 -1
include/asm-mips/emma2rh/emma2rh.h
··· 24 24 #ifndef __ASM_EMMA2RH_EMMA2RH_H 25 25 #define __ASM_EMMA2RH_EMMA2RH_H 26 26 27 + #include <irq.h> 28 + 27 29 /* 28 30 * EMMA2RH registers 29 31 */ ··· 106 104 #define NUM_EMMA2RH_IRQ 96 107 105 108 106 #define CPU_EMMA2RH_CASCADE 2 109 - #define EMMA2RH_IRQ_BASE 0 107 + #define CPU_IRQ_BASE MIPS_CPU_IRQ_BASE 108 + #define EMMA2RH_IRQ_BASE (CPU_IRQ_BASE + NUM_CPU_IRQ) 110 109 111 110 /* 112 111 * emma2rh irq defs
-1
include/asm-mips/emma2rh/markeins.h
··· 33 33 34 34 #define EMMA2RH_SW_IRQ_BASE (EMMA2RH_IRQ_BASE + NUM_EMMA2RH_IRQ) 35 35 #define EMMA2RH_GPIO_IRQ_BASE (EMMA2RH_SW_IRQ_BASE + NUM_EMMA2RH_IRQ_SW) 36 - #define CPU_IRQ_BASE (EMMA2RH_GPIO_IRQ_BASE + NUM_EMMA2RH_IRQ_GPIO) 37 36 38 37 #define EMMA2RH_SW_IRQ_INT0 (0+EMMA2RH_SW_IRQ_BASE) 39 38 #define EMMA2RH_SW_IRQ_INT1 (1+EMMA2RH_SW_IRQ_BASE)
+3 -3
include/asm-mips/irq_cpu.h
··· 13 13 #ifndef _ASM_IRQ_CPU_H 14 14 #define _ASM_IRQ_CPU_H 15 15 16 - extern void mips_cpu_irq_init(int irq_base); 17 - extern void rm7k_cpu_irq_init(int irq_base); 18 - extern void rm9k_cpu_irq_init(int irq_base); 16 + extern void mips_cpu_irq_init(void); 17 + extern void rm7k_cpu_irq_init(void); 18 + extern void rm9k_cpu_irq_init(void); 19 19 20 20 #endif /* _ASM_IRQ_CPU_H */
+3 -1
include/asm-mips/mach-cobalt/cobalt.h
··· 12 12 #ifndef __ASM_COBALT_H 13 13 #define __ASM_COBALT_H 14 14 15 + #include <irq.h> 16 + 15 17 /* 16 18 * i8259 legacy interrupts used on Cobalt: 17 19 * ··· 27 25 /* 28 26 * CPU IRQs are 16 ... 23 29 27 */ 30 - #define COBALT_CPU_IRQ 16 28 + #define COBALT_CPU_IRQ MIPS_CPU_IRQ_BASE 31 29 32 30 #define COBALT_GALILEO_IRQ (COBALT_CPU_IRQ + 2) 33 31 #define COBALT_SCC_IRQ (COBALT_CPU_IRQ + 3) /* pre-production has 85C30 */
+2
include/asm-mips/mach-emma2rh/irq.h
··· 10 10 11 11 #define NR_IRQS 256 12 12 13 + #include_next <irq.h> 14 + 13 15 #endif /* __ASM_MACH_EMMA2RH_IRQ_H */
+26
include/asm-mips/mach-generic/irq.h
··· 8 8 #ifndef __ASM_MACH_GENERIC_IRQ_H 9 9 #define __ASM_MACH_GENERIC_IRQ_H 10 10 11 + #ifndef NR_IRQS 11 12 #define NR_IRQS 128 13 + #endif 14 + 15 + #ifdef CONFIG_IRQ_CPU 16 + 17 + #ifndef MIPS_CPU_IRQ_BASE 18 + #ifdef CONFIG_I8259 19 + #define MIPS_CPU_IRQ_BASE 16 20 + #else 21 + #define MIPS_CPU_IRQ_BASE 0 22 + #endif /* CONFIG_I8259 */ 23 + #endif 24 + 25 + #ifdef CONFIG_IRQ_CPU_RM7K 26 + #ifndef RM7K_CPU_IRQ_BASE 27 + #define RM7K_CPU_IRQ_BASE (MIPS_CPU_IRQ_BASE+8) 28 + #endif 29 + #endif 30 + 31 + #ifdef CONFIG_IRQ_CPU_RM9K 32 + #ifndef RM9K_CPU_IRQ_BASE 33 + #define RM9K_CPU_IRQ_BASE (MIPS_CPU_IRQ_BASE+12) 34 + #endif 35 + #endif 36 + 37 + #endif /* CONFIG_IRQ_CPU */ 12 38 13 39 #endif /* __ASM_MACH_GENERIC_IRQ_H */
+2
include/asm-mips/mach-mips/irq.h
··· 4 4 5 5 #define NR_IRQS 256 6 6 7 + #include_next <irq.h> 8 + 7 9 #endif /* __ASM_MACH_MIPS_IRQ_H */
+8
include/asm-mips/mach-vr41xx/irq.h
··· 1 + #ifndef __ASM_MACH_VR41XX_IRQ_H 2 + #define __ASM_MACH_VR41XX_IRQ_H 3 + 4 + #include <asm/vr41xx/irq.h> /* for MIPS_CPU_IRQ_BASE */ 5 + 6 + #include_next <irq.h> 7 + 8 + #endif /* __ASM_MACH_VR41XX_IRQ_H */
+3 -1
include/asm-mips/mips-boards/atlasint.h
··· 26 26 #ifndef _MIPS_ATLASINT_H 27 27 #define _MIPS_ATLASINT_H 28 28 29 + #include <irq.h> 30 + 29 31 /* 30 32 * Interrupts 0..7 are used for Atlas CPU interrupts (nonEIC mode) 31 33 */ 32 - #define MIPSCPU_INT_BASE 0 34 + #define MIPSCPU_INT_BASE MIPS_CPU_IRQ_BASE 33 35 34 36 /* CPU interrupt offsets */ 35 37 #define MIPSCPU_INT_SW0 0
+3 -1
include/asm-mips/mips-boards/maltaint.h
··· 25 25 #ifndef _MIPS_MALTAINT_H 26 26 #define _MIPS_MALTAINT_H 27 27 28 + #include <irq.h> 29 + 28 30 /* 29 31 * Interrupts 0..15 are used for Malta ISA compatible interrupts 30 32 */ ··· 35 33 /* 36 34 * Interrupts 16..23 are used for Malta CPU interrupts (nonEIC mode) 37 35 */ 38 - #define MIPSCPU_INT_BASE 16 36 + #define MIPSCPU_INT_BASE MIPS_CPU_IRQ_BASE 39 37 40 38 /* CPU interrupt offsets */ 41 39 #define MIPSCPU_INT_SW0 0
+3 -1
include/asm-mips/mips-boards/seadint.h
··· 20 20 #ifndef _MIPS_SEADINT_H 21 21 #define _MIPS_SEADINT_H 22 22 23 + #include <irq.h> 24 + 23 25 /* 24 26 * Interrupts 0..7 are used for SEAD CPU interrupts 25 27 */ 26 - #define MIPSCPU_INT_BASE 0 28 + #define MIPSCPU_INT_BASE MIPS_CPU_IRQ_BASE 27 29 28 30 #define MIPSCPU_INT_UART0 2 29 31 #define MIPSCPU_INT_UART1 3
+2 -1
include/asm-mips/mips-boards/simint.h
··· 17 17 #ifndef _MIPS_SIMINT_H 18 18 #define _MIPS_SIMINT_H 19 19 20 + #include <irq.h> 20 21 21 22 #define SIM_INT_BASE 0 22 23 #define MIPSCPU_INT_MB0 2 23 - #define MIPSCPU_INT_BASE 16 24 + #define MIPSCPU_INT_BASE MIPS_CPU_IRQ_BASE 24 25 #define MIPS_CPU_TIMER_IRQ 7 25 26 26 27
+2 -1
include/asm-mips/rtlx.h
··· 6 6 #ifndef __ASM_RTLX_H 7 7 #define __ASM_RTLX_H_ 8 8 9 + #include <irq.h> 10 + 9 11 #define LX_NODE_BASE 10 10 12 11 - #define MIPSCPU_INT_BASE 16 12 13 #define MIPS_CPU_RTLX_IRQ 0 13 14 14 15 #define RTLX_VERSION 2
+7 -6
include/asm-mips/sgi/ip22.h
··· 21 21 * HAL2 driver). This will prevent many complications, trust me ;-) 22 22 */ 23 23 24 + #include <irq.h> 24 25 #include <asm/sgi/ioc.h> 25 26 26 27 #define SGINT_EISA 0 /* 16 EISA irq levels (Indigo2) */ 27 - #define SGINT_CPU 16 /* MIPS CPU define 8 interrupt sources */ 28 - #define SGINT_LOCAL0 24 /* 8 local0 irq levels */ 29 - #define SGINT_LOCAL1 32 /* 8 local1 irq levels */ 30 - #define SGINT_LOCAL2 40 /* 8 local2 vectored irq levels */ 31 - #define SGINT_LOCAL3 48 /* 8 local3 vectored irq levels */ 32 - #define SGINT_END 56 /* End of 'spaces' */ 28 + #define SGINT_CPU MIPS_CPU_IRQ_BASE /* MIPS CPU define 8 interrupt sources */ 29 + #define SGINT_LOCAL0 (SGINT_CPU+8) /* 8 local0 irq levels */ 30 + #define SGINT_LOCAL1 (SGINT_CPU+16) /* 8 local1 irq levels */ 31 + #define SGINT_LOCAL2 (SGINT_CPU+24) /* 8 local2 vectored irq levels */ 32 + #define SGINT_LOCAL3 (SGINT_CPU+32) /* 8 local3 vectored irq levels */ 33 + #define SGINT_END (SGINT_CPU+40) /* End of 'spaces' */ 33 34 34 35 /* 35 36 * Individual interrupt definitions for the Indy and Indigo2