Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

drm/panel: simple: Add support for DataImage SCF0700C48GGU18

This adds support for the DataImage SCF0700C48GGU18 7.0" WVGA (800x480)
TFT LCD panel. The panel has 24-bit parallel interface and can be
supported by the simple panel driver.

Signed-off-by: Michal Vokáč <michal.vokac@ysoft.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1529930490-11874-2-git-send-email-michal.vokac@ysoft.com

authored by

Michal Vokáč and committed by
Thierry Reding
97ceb1fb 03fa9aa3

+37
+8
Documentation/devicetree/bindings/display/panel/dataimage,scf0700c48ggu18.txt
··· 1 + DataImage, Inc. 7" WVGA (800x480) TFT LCD panel with 24-bit parallel interface. 2 + 3 + Required properties: 4 + - compatible: should be "dataimage,scf0700c48ggu18" 5 + - power-supply: as specified in the base binding 6 + 7 + This binding is compatible with the simple-panel binding, which is specified 8 + in simple-panel.txt in this directory.
+29
drivers/gpu/drm/panel/panel-simple.c
··· 906 906 }, 907 907 }; 908 908 909 + static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = { 910 + .clock = 33260, 911 + .hdisplay = 800, 912 + .hsync_start = 800 + 40, 913 + .hsync_end = 800 + 40 + 128, 914 + .htotal = 800 + 40 + 128 + 88, 915 + .vdisplay = 480, 916 + .vsync_start = 480 + 10, 917 + .vsync_end = 480 + 10 + 2, 918 + .vtotal = 480 + 10 + 2 + 33, 919 + .vrefresh = 60, 920 + .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 921 + }; 922 + 923 + static const struct panel_desc dataimage_scf0700c48ggu18 = { 924 + .modes = &dataimage_scf0700c48ggu18_mode, 925 + .num_modes = 1, 926 + .bpc = 8, 927 + .size = { 928 + .width = 152, 929 + .height = 91, 930 + }, 931 + .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 932 + .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE, 933 + }; 934 + 909 935 static const struct display_timing dlc_dlc0700yzg_1_timing = { 910 936 .pixelclock = { 45000000, 51200000, 57000000 }, 911 937 .hactive = { 1024, 1024, 1024 }, ··· 2357 2331 }, { 2358 2332 .compatible = "chunghwa,claa101wb01", 2359 2333 .data = &chunghwa_claa101wb01 2334 + }, { 2335 + .compatible = "dataimage,scf0700c48ggu18", 2336 + .data = &dataimage_scf0700c48ggu18, 2360 2337 }, { 2361 2338 .compatible = "dlc,dlc0700yzg-1", 2362 2339 .data = &dlc_dlc0700yzg_1,