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ARM: dts: at91: use generic name for reset controller

Use generic name for reset controller of AT91 devices to comply with
DT specifications.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220610092414.1816571-2-claudiu.beznea@microchip.com

Claudiu Beznea 979813d2 b66724d2

+11 -11
+1 -1
arch/arm/boot/dts/at91sam9260.dtsi
··· 123 123 clock-names = "slow_xtal", "main_xtal"; 124 124 }; 125 125 126 - rstc@fffffd00 { 126 + reset-controller@fffffd00 { 127 127 compatible = "atmel,at91sam9260-rstc"; 128 128 reg = <0xfffffd00 0x10>; 129 129 clocks = <&pmc PMC_TYPE_CORE PMC_SLOW>;
+1 -1
arch/arm/boot/dts/at91sam9261.dtsi
··· 603 603 clock-names = "slow_xtal", "main_xtal"; 604 604 }; 605 605 606 - rstc@fffffd00 { 606 + reset-controller@fffffd00 { 607 607 compatible = "atmel,at91sam9260-rstc"; 608 608 reg = <0xfffffd00 0x10>; 609 609 clocks = <&slow_xtal>;
+1 -1
arch/arm/boot/dts/at91sam9263.dtsi
··· 151 151 clock-names = "t0_clk", "slow_clk"; 152 152 }; 153 153 154 - rstc@fffffd00 { 154 + reset-controller@fffffd00 { 155 155 compatible = "atmel,at91sam9260-rstc"; 156 156 reg = <0xfffffd00 0x10>; 157 157 clocks = <&slow_xtal>;
+1 -1
arch/arm/boot/dts/at91sam9g45.dtsi
··· 137 137 clock-names = "slow_clk", "main_xtal"; 138 138 }; 139 139 140 - rstc@fffffd00 { 140 + reset-controller@fffffd00 { 141 141 compatible = "atmel,at91sam9g45-rstc"; 142 142 reg = <0xfffffd00 0x10>; 143 143 clocks = <&clk32k>;
+1 -1
arch/arm/boot/dts/at91sam9n12.dtsi
··· 126 126 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 127 127 }; 128 128 129 - rstc@fffffe00 { 129 + reset-controller@fffffe00 { 130 130 compatible = "atmel,at91sam9g45-rstc"; 131 131 reg = <0xfffffe00 0x10>; 132 132 clocks = <&clk32k>;
+1 -1
arch/arm/boot/dts/at91sam9rl.dtsi
··· 766 766 clock-names = "slow_clk", "main_xtal"; 767 767 }; 768 768 769 - rstc@fffffd00 { 769 + reset-controller@fffffd00 { 770 770 compatible = "atmel,at91sam9260-rstc"; 771 771 reg = <0xfffffd00 0x10>; 772 772 clocks = <&clk32k>;
+1 -1
arch/arm/boot/dts/at91sam9x5.dtsi
··· 134 134 clock-names = "slow_clk", "main_xtal"; 135 135 }; 136 136 137 - reset_controller: rstc@fffffe00 { 137 + reset_controller: reset-controller@fffffe00 { 138 138 compatible = "atmel,at91sam9g45-rstc"; 139 139 reg = <0xfffffe00 0x10>; 140 140 clocks = <&clk32k>;
+1 -1
arch/arm/boot/dts/sam9x60.dtsi
··· 667 667 clock-names = "td_slck", "md_slck", "main_xtal"; 668 668 }; 669 669 670 - reset_controller: rstc@fffffe00 { 670 + reset_controller: reset-controller@fffffe00 { 671 671 compatible = "microchip,sam9x60-rstc"; 672 672 reg = <0xfffffe00 0x10>; 673 673 clocks = <&clk32k 0>;
+1 -1
arch/arm/boot/dts/sama5d2.dtsi
··· 668 668 ranges = <0 0xf8044000 0x1420>; 669 669 }; 670 670 671 - reset_controller: rstc@f8048000 { 671 + reset_controller: reset-controller@f8048000 { 672 672 compatible = "atmel,sama5d3-rstc"; 673 673 reg = <0xf8048000 0x10>; 674 674 clocks = <&clk32k>;
+1 -1
arch/arm/boot/dts/sama5d3.dtsi
··· 1003 1003 clock-names = "slow_clk", "main_xtal"; 1004 1004 }; 1005 1005 1006 - reset_controller: rstc@fffffe00 { 1006 + reset_controller: reset-controller@fffffe00 { 1007 1007 compatible = "atmel,sama5d3-rstc", "atmel,at91sam9g45-rstc"; 1008 1008 reg = <0xfffffe00 0x10>; 1009 1009 clocks = <&clk32k>;
+1 -1
arch/arm/boot/dts/sama5d4.dtsi
··· 726 726 }; 727 727 }; 728 728 729 - reset_controller: rstc@fc068600 { 729 + reset_controller: reset-controller@fc068600 { 730 730 compatible = "atmel,sama5d3-rstc", "atmel,at91sam9g45-rstc"; 731 731 reg = <0xfc068600 0x10>; 732 732 clocks = <&clk32k>;