tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu

Pull m68knommu updates from Greg Ungerer:
"The bulk of the changes are generalizing the ColdFire v3 core support
and adding in 537x CPU support. Also a couple of other bug fixes, one
to fix a reintroduction of a past bug in the romfs filesystem nommu
support."

* 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu:
m68knommu: enable Timer on coldfire 532x
m68knommu: fix ColdFire 5373/5329 QSPI base address
m68knommu: add support for configuring a Freescale M5373EVB board
m68knommu: add support for the ColdFire 537x family of CPUs
m68knommu: make ColdFire M532x platform support more v3 generic
m68knommu: create and use a common M53xx ColdFire class of CPUs
m68k: remove unused asm/dbg.h
m68k: Set ColdFire ACR1 cache mode depending on kernel configuration
romfs: fix nommu map length to keep inside filesystem
m68k: clean up unused "config ROMVECSIZE"

Linus Torvalds 977b58e1 f5b8fcb4

+60 -49
+12
arch/m68k/Kconfig.cpu
··· 223 223 help 224 224 Motorola ColdFire 5307 processor support. 225 225 226 + config M53xx 227 + bool 228 + 226 229 config M532x 227 230 bool "MCF532x" 228 231 depends on !MMU 232 + select M53xx 229 233 select HAVE_CACHE_CB 230 234 help 231 235 Freescale (Motorola) ColdFire 532x processor support. 236 + 237 + config M537x 238 + bool "MCF537x" 239 + depends on !MMU 240 + select M53xx 241 + select HAVE_CACHE_CB 242 + help 243 + Freescale ColdFire 537x processor support. 232 244 233 245 config M5407 234 246 bool "MCF5407"
+7 -9
arch/m68k/Kconfig.machine
··· 358 358 help 359 359 Support for the senTec COBRA5329 board. 360 360 361 + config M5373EVB 362 + bool "Freescale M5373EVB board support" 363 + depends on M537x 364 + select FREESCALE 365 + help 366 + Support for the Freescale M5373EVB board. 367 + 361 368 config M5407C3 362 369 bool "Motorola M5407C3 board support" 363 370 depends on M5407 ··· 545 538 This is almost always the same as the base of the ROM. Since on all 546 539 68000 type variants the vectors are at the base of the boot device 547 540 on system startup. 548 - 549 - config ROMVECSIZE 550 - hex "Size of ROM vector region (in bytes)" 551 - default "0x400" 552 - depends on ROM 553 - help 554 - Define the size of the vector region in ROM. For most 68000 555 - variants this would be 0x400 bytes in size. Set to 0 if you do 556 - not want a vector region at the start of the ROM. 557 541 558 542 config ROMSTART 559 543 hex "Address of the base of system image in ROM"
+1
arch/m68k/Makefile
··· 45 45 cpuflags-$(CONFIG_M54xx) := $(call cc-option,-mcpu=5475,-m5200) 46 46 cpuflags-$(CONFIG_M5407) := $(call cc-option,-mcpu=5407,-m5200) 47 47 cpuflags-$(CONFIG_M532x) := $(call cc-option,-mcpu=532x,-m5307) 48 + cpuflags-$(CONFIG_M537x) := $(call cc-option,-mcpu=537x,-m5307) 48 49 cpuflags-$(CONFIG_M5307) := $(call cc-option,-mcpu=5307,-m5200) 49 50 cpuflags-$(CONFIG_M528x) := $(call cc-option,-mcpu=528x,-m5307) 50 51 cpuflags-$(CONFIG_M5275) := $(call cc-option,-mcpu=5275,-m5307)
-6
arch/m68k/include/asm/dbg.h
··· 1 - #define DEBUG 1 2 - #ifdef CONFIG_COLDFIRE 3 - #define BREAK asm volatile ("halt") 4 - #else 5 - #define BREAK *(volatile unsigned char *)0xdeadbee0 = 0 6 - #endif
+1 -1
arch/m68k/include/asm/dma.h
··· 39 39 #define MAX_M68K_DMA_CHANNELS 4 40 40 #elif defined(CONFIG_M5272) 41 41 #define MAX_M68K_DMA_CHANNELS 1 42 - #elif defined(CONFIG_M532x) 42 + #elif defined(CONFIG_M53xx) 43 43 #define MAX_M68K_DMA_CHANNELS 0 44 44 #else 45 45 #define MAX_M68K_DMA_CHANNELS 2
+6 -6
arch/m68k/include/asm/m532xsim.h arch/m68k/include/asm/m53xxsim.h
··· 1 1 /****************************************************************************/ 2 2 3 3 /* 4 - * m532xsim.h -- ColdFire 5329 registers 4 + * m53xxsim.h -- ColdFire 5329 registers 5 5 */ 6 6 7 7 /****************************************************************************/ 8 - #ifndef m532xsim_h 9 - #define m532xsim_h 8 + #ifndef m53xxsim_h 9 + #define m53xxsim_h 10 10 /****************************************************************************/ 11 11 12 - #define CPU_NAME "COLDFIRE(m532x)" 12 + #define CPU_NAME "COLDFIRE(m53xx)" 13 13 #define CPU_INSTR_PER_JIFFY 3 14 14 #define MCF_BUSCLK (MCF_CLK / 3) 15 15 ··· 107 107 /* 108 108 * QSPI module. 109 109 */ 110 - #define MCFQSPI_BASE 0xFC058000 /* Base address of QSPI */ 110 + #define MCFQSPI_BASE 0xFC05C000 /* Base address of QSPI */ 111 111 #define MCFQSPI_SIZE 0x40 /* Size of QSPI region */ 112 112 113 113 #define MCFQSPI_CS0 84 ··· 1238 1238 #define MCFEPORT_EPFR (0xFC094006) 1239 1239 1240 1240 /********************************************************************/ 1241 - #endif /* m532xsim_h */ 1241 + #endif /* m53xxsim_h */
+2 -2
arch/m68k/include/asm/m53xxacr.h
··· 55 55 #define CACHE_SIZE 0x2000 /* 8k of unified cache */ 56 56 #define ICACHE_SIZE CACHE_SIZE 57 57 #define DCACHE_SIZE CACHE_SIZE 58 - #elif defined(CONFIG_M532x) 59 - #define CACHE_SIZE 0x4000 /* 32k of unified cache */ 58 + #elif defined(CONFIG_M53xx) 59 + #define CACHE_SIZE 0x4000 /* 16k of unified cache */ 60 60 #define ICACHE_SIZE CACHE_SIZE 61 61 #define DCACHE_SIZE CACHE_SIZE 62 62 #endif
+6 -1
arch/m68k/include/asm/m54xxacr.h
··· 96 96 */ 97 97 #define ACR0_MODE (ACR_BA(CONFIG_MBAR)+ACR_ADMSK(0x1000000)+ \ 98 98 ACR_ENABLE+ACR_SUPER+ACR_CM_OFF_PRE+ACR_SP) 99 + #if defined(CONFIG_CACHE_COPYBACK) 99 100 #define ACR1_MODE (ACR_BA(CONFIG_RAMBASE)+ACR_ADMSK(CONFIG_RAMSIZE)+ \ 100 - ACR_ENABLE+ACR_SUPER+ACR_SP) 101 + ACR_ENABLE+ACR_SUPER+ACR_SP+ACR_CM_CP) 102 + #else 103 + #define ACR1_MODE (ACR_BA(CONFIG_RAMBASE)+ACR_ADMSK(CONFIG_RAMSIZE)+ \ 104 + ACR_ENABLE+ACR_SUPER+ACR_SP+ACR_CM_WT) 105 + #endif 101 106 #define ACR2_MODE 0 102 107 #define ACR3_MODE (ACR_BA(CONFIG_RAMBASE)+ACR_ADMSK(CONFIG_RAMSIZE)+ \ 103 108 ACR_ENABLE+ACR_SUPER+ACR_SP)
+5 -5
arch/m68k/include/asm/mcfgpio.h
··· 104 104 #if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \ 105 105 defined(CONFIG_M520x) || defined(CONFIG_M523x) || \ 106 106 defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 107 - defined(CONFIG_M532x) || defined(CONFIG_M54xx) || \ 107 + defined(CONFIG_M53xx) || defined(CONFIG_M54xx) || \ 108 108 defined(CONFIG_M5441x) 109 109 110 110 /* These parts have GPIO organized by 8 bit ports */ ··· 139 139 140 140 #if defined(CONFIG_M520x) || defined(CONFIG_M523x) || \ 141 141 defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 142 - defined(CONFIG_M532x) || defined(CONFIG_M5441x) 142 + defined(CONFIG_M53xx) || defined(CONFIG_M5441x) 143 143 /* 144 144 * These parts have an 'Edge' Port module (external interrupt/GPIO) which uses 145 145 * read-modify-write to change an output and a GPIO module which has separate ··· 195 195 return MCFSIM2_GPIO1READ; 196 196 #elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \ 197 197 defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 198 - defined(CONFIG_M532x) || defined(CONFIG_M5441x) 198 + defined(CONFIG_M53xx) || defined(CONFIG_M5441x) 199 199 #if !defined(CONFIG_M5441x) 200 200 if (gpio < 8) 201 201 return MCFEPORT_EPPDR; ··· 237 237 return MCFSIM2_GPIO1WRITE; 238 238 #elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \ 239 239 defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 240 - defined(CONFIG_M532x) || defined(CONFIG_M5441x) 240 + defined(CONFIG_M53xx) || defined(CONFIG_M5441x) 241 241 #if !defined(CONFIG_M5441x) 242 242 if (gpio < 8) 243 243 return MCFEPORT_EPDR; ··· 279 279 return MCFSIM2_GPIO1ENABLE; 280 280 #elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \ 281 281 defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 282 - defined(CONFIG_M532x) || defined(CONFIG_M5441x) 282 + defined(CONFIG_M53xx) || defined(CONFIG_M5441x) 283 283 #if !defined(CONFIG_M5441x) 284 284 if (gpio < 8) 285 285 return MCFEPORT_EPDDR;
+2 -2
arch/m68k/include/asm/mcfsim.h
··· 36 36 #elif defined(CONFIG_M5307) 37 37 #include <asm/m5307sim.h> 38 38 #include <asm/mcfintc.h> 39 - #elif defined(CONFIG_M532x) 40 - #include <asm/m532xsim.h> 39 + #elif defined(CONFIG_M53xx) 40 + #include <asm/m53xxsim.h> 41 41 #elif defined(CONFIG_M5407) 42 42 #include <asm/m5407sim.h> 43 43 #include <asm/mcfintc.h>
+1 -1
arch/m68k/include/asm/mcftimer.h
··· 19 19 #define MCFTIMER_TRR 0x04 /* Timer Reference (r/w) */ 20 20 #define MCFTIMER_TCR 0x08 /* Timer Capture reg (r/w) */ 21 21 #define MCFTIMER_TCN 0x0C /* Timer Counter reg (r/w) */ 22 - #if defined(CONFIG_M532x) || defined(CONFIG_M5441x) 22 + #if defined(CONFIG_M53xx) || defined(CONFIG_M5441x) 23 23 #define MCFTIMER_TER 0x03 /* Timer Event reg (r/w) */ 24 24 #else 25 25 #define MCFTIMER_TER 0x11 /* Timer Event reg (r/w) */
+1 -1
arch/m68k/platform/coldfire/Makefile
··· 25 25 obj-$(CONFIG_M5272) += m5272.o intc-5272.o timers.o 26 26 obj-$(CONFIG_M528x) += m528x.o pit.o intc-2.o reset.o 27 27 obj-$(CONFIG_M5307) += m5307.o timers.o intc.o reset.o 28 - obj-$(CONFIG_M532x) += m532x.o timers.o intc-simr.o reset.o 28 + obj-$(CONFIG_M53xx) += m53xx.o timers.o intc-simr.o reset.o 29 29 obj-$(CONFIG_M5407) += m5407.o timers.o intc.o reset.o 30 30 obj-$(CONFIG_M54xx) += m54xx.o sltimers.o intc-2.o 31 31 obj-$(CONFIG_M5441x) += m5441x.o pit.o intc-simr.o reset.o
+11 -12
arch/m68k/platform/coldfire/m532x.c arch/m68k/platform/coldfire/m53xx.c
··· 1 1 /***************************************************************************/ 2 2 3 3 /* 4 - * linux/arch/m68knommu/platform/532x/config.c 4 + * m53xx.c -- platform support for ColdFire 53xx based boards 5 5 * 6 6 * Copyright (C) 1999-2002, Greg Ungerer (gerg@snapgear.com) 7 7 * Copyright (C) 2000, Lineo (www.lineo.com) ··· 118 118 &__clk_0_24, /* mcfuart.0 */ 119 119 &__clk_0_25, /* mcfuart.1 */ 120 120 &__clk_0_26, /* mcfuart.2 */ 121 - 121 + &__clk_0_28, /* mcftmr.0 */ 122 + &__clk_0_29, /* mcftmr.1 */ 122 123 &__clk_0_32, /* mcfpit.0 */ 123 124 &__clk_0_33, /* mcfpit.1 */ 124 125 &__clk_0_37, /* mcfeport.0 */ ··· 135 134 &__clk_0_17, /* edma */ 136 135 &__clk_0_22, /* mcfi2c.0 */ 137 136 &__clk_0_23, /* mcfqspi.0 */ 138 - &__clk_0_28, /* mcftmr.0 */ 139 - &__clk_0_29, /* mcftmr.1 */ 140 137 &__clk_0_30, /* mcftmr.2 */ 141 138 &__clk_0_31, /* mcftmr.3 */ 142 139 &__clk_0_34, /* mcfpit.2 */ ··· 152 153 }; 153 154 154 155 155 - static void __init m532x_clk_init(void) 156 + static void __init m53xx_clk_init(void) 156 157 { 157 158 unsigned i; 158 159 ··· 168 169 169 170 #if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) 170 171 171 - static void __init m532x_qspi_init(void) 172 + static void __init m53xx_qspi_init(void) 172 173 { 173 174 /* setup QSPS pins for QSPI with gpio CS control */ 174 175 writew(0x01f0, MCFGPIO_PAR_QSPI); ··· 178 179 179 180 /***************************************************************************/ 180 181 181 - static void __init m532x_uarts_init(void) 182 + static void __init m53xx_uarts_init(void) 182 183 { 183 184 /* UART GPIO initialization */ 184 185 writew(readw(MCFGPIO_PAR_UART) | 0x0FFF, MCFGPIO_PAR_UART); ··· 186 187 187 188 /***************************************************************************/ 188 189 189 - static void __init m532x_fec_init(void) 190 + static void __init m53xx_fec_init(void) 190 191 { 191 192 u8 v; 192 193 ··· 216 217 } 217 218 #endif 218 219 mach_sched_init = hw_timer_init; 219 - m532x_clk_init(); 220 - m532x_uarts_init(); 221 - m532x_fec_init(); 220 + m53xx_clk_init(); 221 + m53xx_uarts_init(); 222 + m53xx_fec_init(); 222 223 #if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) 223 - m532x_qspi_init(); 224 + m53xx_qspi_init(); 224 225 #endif 225 226 226 227 #ifdef CONFIG_BDM_DISABLE
+1 -1
arch/m68k/platform/coldfire/timers.c
··· 36 36 */ 37 37 void coldfire_profile_init(void); 38 38 39 - #if defined(CONFIG_M532x) || defined(CONFIG_M5441x) 39 + #if defined(CONFIG_M53xx) || defined(CONFIG_M5441x) 40 40 #define __raw_readtrr __raw_readl 41 41 #define __raw_writetrr __raw_writel 42 42 #else
-1
drivers/tty/serial/68328serial.c
··· 14 14 * 2.4/2.5 port David McCullough 15 15 */ 16 16 17 - #include <asm/dbg.h> 18 17 #include <linux/module.h> 19 18 #include <linux/errno.h> 20 19 #include <linux/serial.h>
+4 -1
fs/romfs/mmap-nommu.c
··· 49 49 return (unsigned long) -EINVAL; 50 50 51 51 offset += ROMFS_I(inode)->i_dataoffset; 52 - if (offset > mtd->size - len) 52 + if (offset >= mtd->size) 53 53 return (unsigned long) -EINVAL; 54 + /* the mapping mustn't extend beyond the EOF */ 55 + if ((offset + len) > mtd->size) 56 + len = mtd->size - offset; 54 57 55 58 ret = mtd_get_unmapped_area(mtd, len, offset, flags); 56 59 if (ret == -EOPNOTSUPP)