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KVM: x86/pmu: fix masking logic for MSR_CORE_PERF_GLOBAL_CTRL

When commit c59a1f106f5c ("KVM: x86/pmu: Add IA32_PEBS_ENABLE
MSR emulation for extended PEBS") switched the initialization of
cpuc->guest_switch_msrs to use compound literals, it screwed up
the boolean logic:

+ u64 pebs_mask = cpuc->pebs_enabled & x86_pmu.pebs_capable;
...
- arr[0].guest = intel_ctrl & ~cpuc->intel_ctrl_host_mask;
- arr[0].guest &= ~(cpuc->pebs_enabled & x86_pmu.pebs_capable);
+ .guest = intel_ctrl & (~cpuc->intel_ctrl_host_mask | ~pebs_mask),

Before the patch, the value of arr[0].guest would have been intel_ctrl &
~cpuc->intel_ctrl_host_mask & ~pebs_mask. The intent is to always treat
PEBS events as host-only because, while the guest runs, there is no way
to tell the processor about the virtual address where to put PEBS records
intended for the host.

Unfortunately, the new expression can be expanded to

(intel_ctrl & ~cpuc->intel_ctrl_host_mask) | (intel_ctrl & ~pebs_mask)

which makes no sense; it includes any bit that isn't *both* marked as
exclude_guest and using PEBS. So, reinstate the old logic. Another
way to write it could be "intel_ctrl & ~(cpuc->intel_ctrl_host_mask |
pebs_mask)", presumably the intention of the author of the faulty.
However, I personally find the repeated application of A AND NOT B to
be a bit more readable.

This shows up as guest failures when running concurrent long-running
perf workloads on the host, and was reported to happen with rcutorture.
All guests on a given host would die simultaneously with something like an
instruction fault or a segmentation violation.

Reported-by: Paul E. McKenney <paulmck@kernel.org>
Analyzed-by: Sean Christopherson <seanjc@google.com>
Tested-by: Paul E. McKenney <paulmck@kernel.org>
Cc: stable@vger.kernel.org
Fixes: c59a1f106f5c ("KVM: x86/pmu: Add IA32_PEBS_ENABLE MSR emulation for extended PEBS")
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

+6 -1
+6 -1
arch/x86/events/intel/core.c
··· 4051 4051 u64 pebs_mask = cpuc->pebs_enabled & x86_pmu.pebs_capable; 4052 4052 int global_ctrl, pebs_enable; 4053 4053 4054 + /* 4055 + * In addition to obeying exclude_guest/exclude_host, remove bits being 4056 + * used for PEBS when running a guest, because PEBS writes to virtual 4057 + * addresses (not physical addresses). 4058 + */ 4054 4059 *nr = 0; 4055 4060 global_ctrl = (*nr)++; 4056 4061 arr[global_ctrl] = (struct perf_guest_switch_msr){ 4057 4062 .msr = MSR_CORE_PERF_GLOBAL_CTRL, 4058 4063 .host = intel_ctrl & ~cpuc->intel_ctrl_guest_mask, 4059 - .guest = intel_ctrl & (~cpuc->intel_ctrl_host_mask | ~pebs_mask), 4064 + .guest = intel_ctrl & ~cpuc->intel_ctrl_host_mask & ~pebs_mask, 4060 4065 }; 4061 4066 4062 4067 if (!x86_pmu.pebs)