tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

V4L/DVB (4551): Added register aliases for saa711x registers, instead of using reg numbers

Signed-off-by: Mauro Carvalho Chehab <mchehab@infradead.org>

Mauro Carvalho Chehab 96ecfc4e 236f16d2

+991 -333
+442 -333
drivers/media/video/saa7115.c
··· 33 33 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 34 34 */ 35 35 36 + #include "saa711x_regs.h" 36 37 37 38 #include <linux/kernel.h> 38 39 #include <linux/module.h> ··· 112 111 113 112 static const unsigned char saa7115_init_auto_input[] = { 114 113 /* Front-End Part */ 115 - 0x01, 0x48, /* white peak control disabled */ 116 - 0x03, 0x20, /* was 0x30. 0x20: long vertical blanking */ 117 - 0x04, 0x90, /* analog gain set to 0 */ 118 - 0x05, 0x90, /* analog gain set to 0 */ 114 + R_01_INC_DELAY, 0x48, /* white peak control disabled */ 115 + R_03_INPUT_CNTL_2, 0x20, /* was 0x30. 0x20: long vertical blanking */ 116 + R_04_INPUT_CNTL_3, 0x90, /* analog gain set to 0 */ 117 + R_05_INPUT_CNTL_4, 0x90, /* analog gain set to 0 */ 119 118 /* Decoder Part */ 120 - 0x06, 0xeb, /* horiz sync begin = -21 */ 121 - 0x07, 0xe0, /* horiz sync stop = -17 */ 122 - 0x0a, 0x80, /* was 0x88. decoder brightness, 0x80 is itu standard */ 123 - 0x0b, 0x44, /* was 0x48. decoder contrast, 0x44 is itu standard */ 124 - 0x0c, 0x40, /* was 0x47. decoder saturation, 0x40 is itu standard */ 125 - 0x0d, 0x00, /* chrominance hue control */ 126 - 0x0f, 0x00, /* chrominance gain control: use automicatic mode */ 127 - 0x10, 0x06, /* chrominance/luminance control: active adaptive combfilter */ 128 - 0x11, 0x00, /* delay control */ 129 - 0x12, 0x9d, /* RTS0 output control: VGATE */ 130 - 0x13, 0x80, /* X-port output control: ITU656 standard mode, RTCO output enable RTCE */ 131 - 0x14, 0x00, /* analog/ADC/auto compatibility control */ 132 - 0x18, 0x40, /* raw data gain 0x00 = nominal */ 133 - 0x19, 0x80, /* raw data offset 0x80 = 0 LSB */ 134 - 0x1a, 0x77, /* color killer level control 0x77 = recommended */ 135 - 0x1b, 0x42, /* misc chroma control 0x42 = recommended */ 136 - 0x1c, 0xa9, /* combfilter control 0xA9 = recommended */ 137 - 0x1d, 0x01, /* combfilter control 0x01 = recommended */ 119 + R_06_H_SYNC_START, 0xeb, /* horiz sync begin = -21 */ 120 + R_07_H_SYNC_STOP, 0xe0, /* horiz sync stop = -17 */ 121 + R_0A_LUMA_BRIGHT_CNTL, 0x80, /* was 0x88. decoder brightness, 0x80 is itu standard */ 122 + R_0B_LUMA_CONTRAST_CNTL, 0x44, /* was 0x48. decoder contrast, 0x44 is itu standard */ 123 + R_0C_CHROMA_SAT_CNTL, 0x40, /* was 0x47. decoder saturation, 0x40 is itu standard */ 124 + R_0D_CHROMA_HUE_CNTL, 0x00, 125 + R_0F_CHROMA_GAIN_CNTL, 0x00, /* use automatic gain */ 126 + R_10_CHROMA_CNTL_2, 0x06, /* chroma: active adaptive combfilter */ 127 + R_11_MODE_DELAY_CNTL, 0x00, 128 + R_12_RT_SIGNAL_CNTL, 0x9d, /* RTS0 output control: VGATE */ 129 + R_13_RT_X_PORT_OUT_CNTL, 0x80, /* ITU656 standard mode, RTCO output enable RTCE */ 130 + R_14_ANAL_ADC_COMPAT_CNTL, 0x00, 131 + R_18_RAW_DATA_GAIN_CNTL, 0x40, /* gain 0x00 = nominal */ 132 + R_19_RAW_DATA_OFF_CNTL, 0x80, 133 + R_1A_COLOR_KILL_LVL_CNTL, 0x77, /* recommended value */ 134 + R_1B_MISC_TVVCRDET, 0x42, /* recommended value */ 135 + R_1C_ENHAN_COMB_CTRL1, 0xa9, /* recommended value */ 136 + R_1D_ENHAN_COMB_CTRL2, 0x01, /* recommended value */ 138 137 139 138 /* Power Device Control */ 140 - 0x88, 0xd0, /* reset device */ 141 - 0x88, 0xf0, /* set device programmed, all in operational mode */ 139 + R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0, /* reset device */ 140 + R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0, /* set device programmed, all in operational mode */ 142 141 0x00, 0x00 143 142 }; 144 143 145 144 static const unsigned char saa7115_cfg_reset_scaler[] = { 146 - 0x87, 0x00, /* disable I-port output */ 147 - 0x88, 0xd0, /* reset scaler */ 148 - 0x88, 0xf0, /* activate scaler */ 149 - 0x87, 0x01, /* enable I-port output */ 145 + R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x00, /* disable I-port output */ 146 + R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0, /* reset scaler */ 147 + R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0, /* activate scaler */ 148 + R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x01, /* enable I-port output */ 150 149 0x00, 0x00 151 150 }; 152 151 153 152 /* ============== SAA7715 VIDEO templates ============= */ 154 153 155 154 static const unsigned char saa7115_cfg_60hz_fullres_x[] = { 156 - 0xcc, 0xd0, /* hsize low (output), hor. output window size = 0x2d0 = 720 */ 157 - 0xcd, 0x02, /* hsize hi (output) */ 155 + /* hsize = 0x2d0 = 720 */ 156 + R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH, 0xd0, 157 + R_CD_B_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 0x02, 158 158 159 159 /* Why not in 60hz-Land, too? */ 160 - 0xd0, 0x01, /* downscale = 1 */ 161 - 0xd8, 0x00, /* hor lum scaling 0x0400 = 1 */ 162 - 0xd9, 0x04, 163 - 0xdc, 0x00, /* hor chrom scaling 0x0200. must be hor lum scaling / 2 */ 164 - 0xdd, 0x02, /* H-scaling incr chroma */ 160 + R_D0_B_HORIZ_PRESCALING, 0x01, /* downscale = 1 */ 161 + /* hor lum scaling 0x0400 = 1 */ 162 + R_D8_B_HORIZ_LUMA_SCALING_INC, 0x00, 163 + R_D9_B_HORIZ_LUMA_SCALING_INC_MSB, 0x04, 164 + 165 + /* must be hor lum scaling / 2 */ 166 + R_DC_B_HORIZ_CHROMA_SCALING, 0x00, 167 + R_DD_B_HORIZ_CHROMA_SCALING_MSB, 0x02, 165 168 166 169 0x00, 0x00 167 170 }; 171 + 168 172 static const unsigned char saa7115_cfg_60hz_fullres_y[] = { 169 - 0xce, 0xf8, /* vsize low (output), ver. output window size = 248 (but 60hz is 240?) */ 170 - 0xcf, 0x00, /* vsize hi (output) */ 173 + /* output window size = 248 (but 60hz is 240?) */ 174 + R_CE_B_VERT_OUTPUT_WINDOW_LENGTH, 0xf8, 175 + R_CF_B_VERT_OUTPUT_WINDOW_LENGTH_MSB, 0x00, 171 176 172 177 /* Why not in 60hz-Land, too? */ 173 - 0xd5, 0x40, /* Lum contrast, nominal value = 0x40 */ 174 - 0xd6, 0x40, /* Chroma satur. nominal value = 0x80 */ 178 + R_D5_B_LUMA_CONTRAST_CNTL, 0x40, /* Lum contrast, nominal value = 0x40 */ 179 + R_D6_B_CHROMA_SATURATION_CNTL, 0x40, /* Chroma satur. nominal value = 0x80 */ 175 180 176 - 0xe0, 0x00, /* V-scaling incr luma low */ 177 - 0xe1, 0x04, /* " hi */ 178 - 0xe2, 0x00, /* V-scaling incr chroma low */ 179 - 0xe3, 0x04, /* " hi */ 181 + R_E0_B_VERT_LUMA_SCALING_INC, 0x00, 182 + R_E1_B_VERT_LUMA_SCALING_INC_MSB, 0x04, 183 + 184 + R_E2_B_VERT_CHROMA_SCALING_INC, 0x00, 185 + R_E3_B_VERT_CHROMA_SCALING_INC_MSB, 0x04, 180 186 181 187 0x00, 0x00 182 188 }; 183 189 184 190 static const unsigned char saa7115_cfg_60hz_video[] = { 185 - 0x80, 0x00, /* reset tasks */ 186 - 0x88, 0xd0, /* reset scaler */ 191 + R_80_GLOBAL_CNTL_1, 0x00, /* reset tasks */ 192 + R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0, /* reset scaler */ 187 193 188 - 0x15, 0x03, /* VGATE pulse start */ 189 - 0x16, 0x11, /* VGATE pulse stop */ 190 - 0x17, 0x9c, /* VGATE MSB and other values */ 194 + R_15_VGATE_START_FID_CHG, 0x03, 195 + R_16_VGATE_STOP, 0x11, 196 + R_17_MISC_VGATE_CONF_AND_MSB, 0x9c, 191 197 192 - 0x08, 0x68, /* 0xBO: auto detection, 0x68 = NTSC */ 193 - 0x0e, 0x07, /* lots of different stuff... video autodetection is on */ 198 + R_08_SYNC_CNTL, 0x68, /* 0xBO: auto detection, 0x68 = NTSC */ 199 + R_0E_CHROMA_CNTL_1, 0x07, /* video autodetection is on */ 194 200 195 - 0x5a, 0x06, /* Vertical offset, standard 60hz value for ITU656 line counting */ 201 + R_5A_V_OFF_FOR_SLICER, 0x06, /* standard 60hz value for ITU656 line counting */ 196 202 197 203 /* Task A */ 198 - 0x90, 0x80, /* Task Handling Control */ 199 - 0x91, 0x48, /* X-port formats/config */ 200 - 0x92, 0x40, /* Input Ref. signal Def. */ 201 - 0x93, 0x84, /* I-port config */ 202 - 0x94, 0x01, /* hoffset low (input), 0x0002 is minimum */ 203 - 0x95, 0x00, /* hoffset hi (input) */ 204 - 0x96, 0xd0, /* hsize low (input), 0x02d0 = 720 */ 205 - 0x97, 0x02, /* hsize hi (input) */ 206 - 0x98, 0x05, /* voffset low (input) */ 207 - 0x99, 0x00, /* voffset hi (input) */ 208 - 0x9a, 0x0c, /* vsize low (input), 0x0c = 12 */ 209 - 0x9b, 0x00, /* vsize hi (input) */ 210 - 0x9c, 0xa0, /* hsize low (output), 0x05a0 = 1440 */ 211 - 0x9d, 0x05, /* hsize hi (output) */ 212 - 0x9e, 0x0c, /* vsize low (output), 0x0c = 12 */ 213 - 0x9f, 0x00, /* vsize hi (output) */ 204 + R_90_A_TASK_HANDLING_CNTL, 0x80, 205 + R_91_A_X_PORT_FORMATS_AND_CONF, 0x48, 206 + R_92_A_X_PORT_INPUT_REFERENCE_SIGNAL, 0x40, 207 + R_93_A_I_PORT_OUTPUT_FORMATS_AND_CONF, 0x84, 208 + 209 + /* hoffset low (input), 0x0002 is minimum */ 210 + R_94_A_HORIZ_INPUT_WINDOW_START, 0x01, 211 + R_95_A_HORIZ_INPUT_WINDOW_START_MSB, 0x00, 212 + 213 + /* hsize low (input), 0x02d0 = 720 */ 214 + R_96_A_HORIZ_INPUT_WINDOW_LENGTH, 0xd0, 215 + R_97_A_HORIZ_INPUT_WINDOW_LENGTH_MSB, 0x02, 216 + 217 + R_98_A_VERT_INPUT_WINDOW_START, 0x05, 218 + R_99_A_VERT_INPUT_WINDOW_START_MSB, 0x00, 219 + 220 + R_9A_A_VERT_INPUT_WINDOW_LENGTH, 0x0c, 221 + R_9B_A_VERT_INPUT_WINDOW_LENGTH_MSB, 0x00, 222 + 223 + R_9C_A_HORIZ_OUTPUT_WINDOW_LENGTH, 0xa0, 224 + R_9D_A_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 0x05, 225 + 226 + R_9E_A_VERT_OUTPUT_WINDOW_LENGTH, 0x0c, 227 + R_9F_A_VERT_OUTPUT_WINDOW_LENGTH_MSB, 0x00, 214 228 215 229 /* Task B */ 216 - 0xc0, 0x00, /* Task Handling Control */ 217 - 0xc1, 0x08, /* X-port formats/config */ 218 - 0xc2, 0x00, /* Input Ref. signal Def. */ 219 - 0xc3, 0x80, /* I-port config */ 220 - 0xc4, 0x02, /* hoffset low (input), 0x0002 is minimum */ 221 - 0xc5, 0x00, /* hoffset hi (input) */ 222 - 0xc6, 0xd0, /* hsize low (input), 0x02d0 = 720 */ 223 - 0xc7, 0x02, /* hsize hi (input) */ 224 - 0xc8, 0x12, /* voffset low (input), 0x12 = 18 */ 225 - 0xc9, 0x00, /* voffset hi (input) */ 226 - 0xca, 0xf8, /* vsize low (input), 0xf8 = 248 */ 227 - 0xcb, 0x00, /* vsize hi (input) */ 228 - 0xcc, 0xd0, /* hsize low (output), 0x02d0 = 720 */ 229 - 0xcd, 0x02, /* hsize hi (output) */ 230 + R_C0_B_TASK_HANDLING_CNTL, 0x00, 231 + R_C1_B_X_PORT_FORMATS_AND_CONF, 0x08, 232 + R_C2_B_INPUT_REFERENCE_SIGNAL_DEFINITION, 0x00, 233 + R_C3_B_I_PORT_FORMATS_AND_CONF, 0x80, 230 234 231 - 0xf0, 0xad, /* Set PLL Register. 60hz 525 lines per frame, 27 MHz */ 232 - 0xf1, 0x05, /* low bit with 0xF0 */ 233 - 0xf5, 0xad, /* Set pulse generator register */ 234 - 0xf6, 0x01, 235 + /* 0x0002 is minimum */ 236 + R_C4_B_HORIZ_INPUT_WINDOW_START, 0x02, 237 + R_C5_B_HORIZ_INPUT_WINDOW_START_MSB, 0x00, 235 238 236 - 0x87, 0x00, /* Disable I-port output */ 237 - 0x88, 0xd0, /* reset scaler */ 238 - 0x80, 0x20, /* Activate only task "B", continuous mode (was 0xA0) */ 239 - 0x88, 0xf0, /* activate scaler */ 240 - 0x87, 0x01, /* Enable I-port output */ 239 + /* 0x02d0 = 720 */ 240 + R_C6_B_HORIZ_INPUT_WINDOW_LENGTH, 0xd0, 241 + R_C7_B_HORIZ_INPUT_WINDOW_LENGTH_MSB, 0x02, 242 + 243 + /* vwindow start 0x12 = 18 */ 244 + R_C8_B_VERT_INPUT_WINDOW_START, 0x12, 245 + R_C9_B_VERT_INPUT_WINDOW_START_MSB, 0x00, 246 + 247 + /* vwindow length 0xf8 = 248 */ 248 + R_CA_B_VERT_INPUT_WINDOW_LENGTH, 0xf8, 249 + R_CB_B_VERT_INPUT_WINDOW_LENGTH_MSB, 0x00, 250 + 251 + /* hwindow 0x02d0 = 720 */ 252 + R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH, 0xd0, 253 + R_CD_B_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 0x02, 254 + 255 + R_F0_LFCO_PER_LINE, 0xad, /* Set PLL Register. 60hz 525 lines per frame, 27 MHz */ 256 + R_F1_P_I_PARAM_SELECT, 0x05, /* low bit with 0xF0 */ 257 + R_F5_PULSGEN_LINE_LENGTH, 0xad, 258 + R_F6_PULSE_A_POS_LSB_AND_PULSEGEN_CONFIG, 0x01, 259 + 260 + R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x00, /* Disable I-port output */ 261 + R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0, /* reset scaler */ 262 + R_80_GLOBAL_CNTL_1, 0x20, /* Activate only task "B", continuous mode (was 0xA0) */ 263 + R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0, /* activate scaler */ 264 + R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x01, /* Enable I-port output */ 241 265 0x00, 0x00 242 266 }; 243 267 244 268 static const unsigned char saa7115_cfg_50hz_fullres_x[] = { 245 - 0xcc, 0xd0, /* hsize low (output), 720 same as 60hz */ 246 - 0xcd, 0x02, /* hsize hi (output) */ 269 + /* hsize low (output), 720 same as 60hz */ 270 + R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH, 0xd0, 271 + R_CD_B_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 0x02, 247 272 248 - 0xd0, 0x01, /* down scale = 1 */ 249 - 0xd8, 0x00, /* hor lum scaling 0x0400 = 1 */ 250 - 0xd9, 0x04, 251 - 0xdc, 0x00, /* hor chrom scaling 0x0200. must be hor lum scaling / 2 */ 252 - 0xdd, 0x02, /* H-scaling incr chroma */ 273 + R_D0_B_HORIZ_PRESCALING, 0x01, /* down scale = 1 */ 274 + R_D8_B_HORIZ_LUMA_SCALING_INC, 0x00, /* hor lum scaling 0x0400 = 1 */ 275 + R_D9_B_HORIZ_LUMA_SCALING_INC_MSB, 0x04, 276 + 277 + /* must be hor lum scaling / 2 */ 278 + R_DC_B_HORIZ_CHROMA_SCALING, 0x00, 279 + R_DD_B_HORIZ_CHROMA_SCALING_MSB, 0x02, 253 280 254 281 0x00, 0x00 255 282 }; 256 283 static const unsigned char saa7115_cfg_50hz_fullres_y[] = { 257 - 0xce, 0x20, /* vsize low (output), 0x0120 = 288 */ 258 - 0xcf, 0x01, /* vsize hi (output) */ 284 + /* vsize low (output), 0x0120 = 288 */ 285 + R_CE_B_VERT_OUTPUT_WINDOW_LENGTH, 0x20, 286 + R_CF_B_VERT_OUTPUT_WINDOW_LENGTH_MSB, 0x01, 259 287 260 - 0xd5, 0x40, /* Lum contrast, nominal value = 0x40 */ 261 - 0xd6, 0x40, /* Chroma satur. nominal value = 0x80 */ 288 + R_D5_B_LUMA_CONTRAST_CNTL, 0x40, /* Lum contrast, nominal value = 0x40 */ 289 + R_D6_B_CHROMA_SATURATION_CNTL, 0x40, /* Chroma satur. nominal value = 0x80 */ 262 290 263 - 0xe0, 0x00, /* V-scaling incr luma low */ 264 - 0xe1, 0x04, /* " hi */ 265 - 0xe2, 0x00, /* V-scaling incr chroma low */ 266 - 0xe3, 0x04, /* " hi */ 291 + R_E0_B_VERT_LUMA_SCALING_INC, 0x00, 292 + R_E1_B_VERT_LUMA_SCALING_INC_MSB, 0x04, 293 + 294 + R_E2_B_VERT_CHROMA_SCALING_INC, 0x00, 295 + R_E3_B_VERT_CHROMA_SCALING_INC_MSB, 0x04, 267 296 268 297 0x00, 0x00 269 298 }; 270 299 271 300 static const unsigned char saa7115_cfg_50hz_video[] = { 272 - 0x80, 0x00, /* reset tasks */ 273 - 0x88, 0xd0, /* reset scaler */ 301 + R_80_GLOBAL_CNTL_1, 0x00, 302 + R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0, /* reset scaler */ 274 303 275 - 0x15, 0x37, /* VGATE start */ 276 - 0x16, 0x16, /* VGATE stop */ 277 - 0x17, 0x99, /* VGATE MSB and other values */ 304 + R_15_VGATE_START_FID_CHG, 0x37, /* VGATE start */ 305 + R_16_VGATE_STOP, 0x16, 306 + R_17_MISC_VGATE_CONF_AND_MSB, 0x99, 278 307 279 - 0x08, 0x28, /* 0x28 = PAL */ 280 - 0x0e, 0x07, /* chrominance control 1 */ 308 + R_08_SYNC_CNTL, 0x28, /* 0x28 = PAL */ 309 + R_0E_CHROMA_CNTL_1, 0x07, 281 310 282 - 0x5a, 0x03, /* Vertical offset, standard 50hz value */ 311 + R_5A_V_OFF_FOR_SLICER, 0x03, /* standard 50hz value */ 283 312 284 313 /* Task A */ 285 - 0x90, 0x81, /* Task Handling Control */ 286 - 0x91, 0x48, /* X-port formats/config */ 287 - 0x92, 0x40, /* Input Ref. signal Def. */ 288 - 0x93, 0x84, /* I-port config */ 314 + R_90_A_TASK_HANDLING_CNTL, 0x81, 315 + R_91_A_X_PORT_FORMATS_AND_CONF, 0x48, 316 + R_92_A_X_PORT_INPUT_REFERENCE_SIGNAL, 0x40, 317 + R_93_A_I_PORT_OUTPUT_FORMATS_AND_CONF, 0x84, 318 + 289 319 /* This is weird: the datasheet says that you should use 2 as the minimum value, */ 290 320 /* but Hauppauge uses 0, and changing that to 2 causes indeed problems (for 50hz) */ 291 - 0x94, 0x00, /* hoffset low (input), 0x0002 is minimum */ 292 - 0x95, 0x00, /* hoffset hi (input) */ 293 - 0x96, 0xd0, /* hsize low (input), 0x02d0 = 720 */ 294 - 0x97, 0x02, /* hsize hi (input) */ 295 - 0x98, 0x03, /* voffset low (input) */ 296 - 0x99, 0x00, /* voffset hi (input) */ 297 - 0x9a, 0x12, /* vsize low (input), 0x12 = 18 */ 298 - 0x9b, 0x00, /* vsize hi (input) */ 299 - 0x9c, 0xa0, /* hsize low (output), 0x05a0 = 1440 */ 300 - 0x9d, 0x05, /* hsize hi (output) */ 301 - 0x9e, 0x12, /* vsize low (output), 0x12 = 18 */ 302 - 0x9f, 0x00, /* vsize hi (output) */ 321 + /* hoffset low (input), 0x0002 is minimum */ 322 + R_94_A_HORIZ_INPUT_WINDOW_START, 0x00, 323 + R_95_A_HORIZ_INPUT_WINDOW_START_MSB, 0x00, 324 + 325 + /* hsize low (input), 0x02d0 = 720 */ 326 + R_96_A_HORIZ_INPUT_WINDOW_LENGTH, 0xd0, 327 + R_97_A_HORIZ_INPUT_WINDOW_LENGTH_MSB, 0x02, 328 + 329 + R_98_A_VERT_INPUT_WINDOW_START, 0x03, 330 + R_99_A_VERT_INPUT_WINDOW_START_MSB, 0x00, 331 + 332 + /* vsize 0x12 = 18 */ 333 + R_9A_A_VERT_INPUT_WINDOW_LENGTH, 0x12, 334 + R_9B_A_VERT_INPUT_WINDOW_LENGTH_MSB, 0x00, 335 + 336 + /* hsize 0x05a0 = 1440 */ 337 + R_9C_A_HORIZ_OUTPUT_WINDOW_LENGTH, 0xa0, 338 + R_9D_A_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 0x05, /* hsize hi (output) */ 339 + R_9E_A_VERT_OUTPUT_WINDOW_LENGTH, 0x12, /* vsize low (output), 0x12 = 18 */ 340 + R_9F_A_VERT_OUTPUT_WINDOW_LENGTH_MSB, 0x00, /* vsize hi (output) */ 303 341 304 342 /* Task B */ 305 - 0xc0, 0x00, /* Task Handling Control */ 306 - 0xc1, 0x08, /* X-port formats/config */ 307 - 0xc2, 0x00, /* Input Ref. signal Def. */ 308 - 0xc3, 0x80, /* I-port config */ 309 - 0xc4, 0x00, /* hoffset low (input), 0x0002 is minimum. See comment at 0x94 above. */ 310 - 0xc5, 0x00, /* hoffset hi (input) */ 311 - 0xc6, 0xd0, /* hsize low (input), 0x02d0 = 720 */ 312 - 0xc7, 0x02, /* hsize hi (input) */ 313 - 0xc8, 0x16, /* voffset low (input), 0x16 = 22 */ 314 - 0xc9, 0x00, /* voffset hi (input) */ 315 - 0xca, 0x20, /* vsize low (input), 0x0120 = 288 */ 316 - 0xcb, 0x01, /* vsize hi (input) */ 317 - 0xcc, 0xd0, /* hsize low (output), 0x02d0 = 720 */ 318 - 0xcd, 0x02, /* hsize hi (output) */ 319 - 0xce, 0x20, /* vsize low (output), 0x0120 = 288 */ 320 - 0xcf, 0x01, /* vsize hi (output) */ 343 + R_C0_B_TASK_HANDLING_CNTL, 0x00, 344 + R_C1_B_X_PORT_FORMATS_AND_CONF, 0x08, 345 + R_C2_B_INPUT_REFERENCE_SIGNAL_DEFINITION, 0x00, 346 + R_C3_B_I_PORT_FORMATS_AND_CONF, 0x80, 321 347 322 - 0xf0, 0xb0, /* Set PLL Register. 50hz 625 lines per frame, 27 MHz */ 323 - 0xf1, 0x05, /* low bit with 0xF0, (was 0x05) */ 324 - 0xf5, 0xb0, /* Set pulse generator register */ 325 - 0xf6, 0x01, 348 + /* This is weird: the datasheet says that you should use 2 as the minimum value, */ 349 + /* but Hauppauge uses 0, and changing that to 2 causes indeed problems (for 50hz) */ 350 + /* hoffset low (input), 0x0002 is minimum. See comment above. */ 351 + R_C4_B_HORIZ_INPUT_WINDOW_START, 0x00, 352 + R_C5_B_HORIZ_INPUT_WINDOW_START_MSB, 0x00, 326 353 327 - 0x87, 0x00, /* Disable I-port output */ 328 - 0x88, 0xd0, /* reset scaler (was 0xD0) */ 329 - 0x80, 0x20, /* Activate only task "B" */ 330 - 0x88, 0xf0, /* activate scaler */ 331 - 0x87, 0x01, /* Enable I-port output */ 354 + /* hsize 0x02d0 = 720 */ 355 + R_C6_B_HORIZ_INPUT_WINDOW_LENGTH, 0xd0, 356 + R_C7_B_HORIZ_INPUT_WINDOW_LENGTH_MSB, 0x02, 357 + 358 + /* voffset 0x16 = 22 */ 359 + R_C8_B_VERT_INPUT_WINDOW_START, 0x16, 360 + R_C9_B_VERT_INPUT_WINDOW_START_MSB, 0x00, 361 + 362 + /* vsize 0x0120 = 288 */ 363 + R_CA_B_VERT_INPUT_WINDOW_LENGTH, 0x20, 364 + R_CB_B_VERT_INPUT_WINDOW_LENGTH_MSB, 0x01, 365 + 366 + /* hsize 0x02d0 = 720 */ 367 + R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH, 0xd0, 368 + R_CD_B_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 0x02, 369 + 370 + /* vsize 0x0120 = 288 */ 371 + R_CE_B_VERT_OUTPUT_WINDOW_LENGTH, 0x20, 372 + R_CF_B_VERT_OUTPUT_WINDOW_LENGTH_MSB, 0x01, 373 + 374 + R_F0_LFCO_PER_LINE, 0xb0, /* Set PLL Register. 50hz 625 lines per frame, 27 MHz */ 375 + R_F1_P_I_PARAM_SELECT, 0x05, /* low bit with 0xF0, (was 0x05) */ 376 + R_F5_PULSGEN_LINE_LENGTH, 0xb0, 377 + R_F6_PULSE_A_POS_LSB_AND_PULSEGEN_CONFIG, 0x01, 378 + 379 + R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x00, /* Disable I-port output */ 380 + R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0, /* reset scaler (was 0xD0) */ 381 + R_80_GLOBAL_CNTL_1, 0x20, /* Activate only task "B" */ 382 + R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0, /* activate scaler */ 383 + R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x01, /* Enable I-port output */ 384 + 332 385 0x00, 0x00 333 386 }; 334 387 335 388 /* ============== SAA7715 VIDEO templates (end) ======= */ 336 389 337 390 static const unsigned char saa7115_cfg_vbi_on[] = { 338 - 0x80, 0x00, /* reset tasks */ 339 - 0x88, 0xd0, /* reset scaler */ 340 - 0x80, 0x30, /* Activate both tasks */ 341 - 0x88, 0xf0, /* activate scaler */ 342 - 0x87, 0x01, /* Enable I-port output */ 391 + R_80_GLOBAL_CNTL_1, 0x00, /* reset tasks */ 392 + R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0, /* reset scaler */ 393 + R_80_GLOBAL_CNTL_1, 0x30, /* Activate both tasks */ 394 + R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0, /* activate scaler */ 395 + R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x01, /* Enable I-port output */ 396 + 343 397 0x00, 0x00 344 398 }; 345 399 346 400 static const unsigned char saa7115_cfg_vbi_off[] = { 347 - 0x80, 0x00, /* reset tasks */ 348 - 0x88, 0xd0, /* reset scaler */ 349 - 0x80, 0x20, /* Activate only task "B" */ 350 - 0x88, 0xf0, /* activate scaler */ 351 - 0x87, 0x01, /* Enable I-port output */ 401 + R_80_GLOBAL_CNTL_1, 0x00, /* reset tasks */ 402 + R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0, /* reset scaler */ 403 + R_80_GLOBAL_CNTL_1, 0x20, /* Activate only task "B" */ 404 + R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0, /* activate scaler */ 405 + R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x01, /* Enable I-port output */ 406 + 352 407 0x00, 0x00 353 408 }; 354 409 355 410 static const unsigned char saa7113_init_auto_input[] = { 356 - 0x01, 0x08, /* PH7113_INCREMENT_DELAY - (1) (1) (1) (1) IDEL3 IDEL2 IDELL1 IDEL0 */ 357 - 0x02, 0xc2, /* PH7113_ANALOG_INPUT_CONTR_1 - FUSE1 FUSE0 GUDL1 GUDL0 MODE3 MODE2 MODE1 MODE0 */ 358 - 0x03, 0x30, /* PH7113_ANALOG_INPUT_CONTR_2 - (1) HLNRS VBSL WPOFF HOLDG GAFIX GAI28 GAI18 */ 359 - 0x04, 0x00, /* PH7113_ANALOG_INPUT_CONTR_3 - GAI17 GAI16 GAI15 GAI14 GAI13 GAI12 GAI11 GAI10 */ 360 - 0x05, 0x00, /* PH7113_ANALOG_INPUT_CONTR_4 - GAI27 GAI26 GAI25 GAI24 GAI23 GAI22 GAI21 GAI20 */ 361 - 0x06, 0x89, /* PH7113_HORIZONTAL_SYNC_START - HSB7 HSB6 HSB5 HSB4 HSB3 HSB2 HSB1 HSB0 */ 362 - 0x07, 0x0d, /* PH7113_HORIZONTAL_SYNC_STOP - HSS7 HSS6 HSS5 HSS4 HSS3 HSS2 HSS1 HSS0 */ 363 - 0x08, 0x88, /* PH7113_SYNC_CONTROL - AUFD FSEL FOET HTC1 HTC0 HPLL VNOI1 VNOI0 */ 364 - 0x09, 0x01, /* PH7113_LUMINANCE_CONTROL - BYPS PREF BPSS1 BPSS0 VBLB UPTCV APER1 APER0 */ 365 - 0x0a, 0x80, /* PH7113_LUMINANCE_BRIGHTNESS - BRIG7 BRIG6 BRIG5 BRIG4 BRIG3 BRIG2 BRIG1 BRIG0 */ 366 - 0x0b, 0x47, /* PH7113_LUMINANCE_CONTRAST - CONT7 CONT6 CONT5 CONT4 CONT3 CONT2 CONT1 CONT0 */ 367 - 0x0c, 0x40, /* PH7113_CHROMA_SATURATION - SATN7 SATN6 SATN5 SATN4 SATN3 SATN2 SATN1 SATN0 */ 368 - 0x0d, 0x00, /* PH7113_CHROMA_HUE_CONTROL - HUEC7 HUEC6 HUEC5 HUEC4 HUEC3 HUEC2 HUEC1 HUEC0 */ 369 - 0x0e, 0x01, /* PH7113_CHROMA_CONTROL - CDTO CSTD2 CSTD1 CSTD0 DCCF FCTC CHBW1 CHBW0 */ 370 - 0x0f, 0x2a, /* PH7113_CHROMA_GAIN_CONTROL - ACGC CGAIN6 CGAIN5 CGAIN4 CGAIN3 CGAIN2 CGAIN1 CGAIN0 */ 371 - 0x10, 0x08, /* PH7113_FORMAT_DELAY_CONTROL - OFTS1 OFTS0 HDEL1 HDEL0 VRLN YDEL2 YDEL1 YDEL0 */ 372 - 0x11, 0x0c, /* PH7113_OUTPUT_CONTROL_1 - GPSW1 CM99 GPSW0 HLSEL OEYC OERT VIPB COLO */ 373 - 0x12, 0x07, /* PH7113_OUTPUT_CONTROL_2 - RTSE13 RTSE12 RTSE11 RTSE10 RTSE03 RTSE02 RTSE01 RTSE00 */ 374 - 0x13, 0x00, /* PH7113_OUTPUT_CONTROL_3 - ADLSB (1) (1) OLDSB FIDP (1) AOSL1 AOSL0 */ 375 - 0x14, 0x00, /* RESERVED 14 - (1) (1) (1) (1) (1) (1) (1) (1) */ 376 - 0x15, 0x00, /* PH7113_V_GATE1_START - VSTA7 VSTA6 VSTA5 VSTA4 VSTA3 VSTA2 VSTA1 VSTA0 */ 377 - 0x16, 0x00, /* PH7113_V_GATE1_STOP - VSTO7 VSTO6 VSTO5 VSTO4 VSTO3 VSTO2 VSTO1 VSTO0 */ 378 - 0x17, 0x00, /* PH7113_V_GATE1_MSB - (1) (1) (1) (1) (1) (1) VSTO8 VSTA8 */ 411 + R_01_INC_DELAY, 0x08, 412 + R_02_INPUT_CNTL_1, 0xc2, 413 + R_03_INPUT_CNTL_2, 0x30, 414 + R_04_INPUT_CNTL_3, 0x00, 415 + R_05_INPUT_CNTL_4, 0x00, 416 + R_06_H_SYNC_START, 0x89, 417 + R_07_H_SYNC_STOP, 0x0d, 418 + R_08_SYNC_CNTL, 0x88, 419 + R_09_LUMA_CNTL, 0x01, 420 + R_0A_LUMA_BRIGHT_CNTL, 0x80, 421 + R_0B_LUMA_CONTRAST_CNTL, 0x47, 422 + R_0C_CHROMA_SAT_CNTL, 0x40, 423 + R_0D_CHROMA_HUE_CNTL, 0x00, 424 + R_0E_CHROMA_CNTL_1, 0x01, 425 + R_0F_CHROMA_GAIN_CNTL, 0x2a, 426 + R_10_CHROMA_CNTL_2, 0x08, 427 + R_11_MODE_DELAY_CNTL, 0x0c, 428 + R_12_RT_SIGNAL_CNTL, 0x07, 429 + R_13_RT_X_PORT_OUT_CNTL, 0x00, 430 + R_14_ANAL_ADC_COMPAT_CNTL, 0x00, 431 + R_15_VGATE_START_FID_CHG, 0x00, 432 + R_16_VGATE_STOP, 0x00, 433 + R_17_MISC_VGATE_CONF_AND_MSB, 0x00, 434 + 379 435 0x00, 0x00 380 436 }; 381 437 382 438 static const unsigned char saa7115_init_misc[] = { 383 - 0x81, 0x01, /* reg 0x15,0x16 define blanking window */ 384 - 0x82, 0x00, 385 - 0x83, 0x01, /* I port settings */ 386 - 0x84, 0x20, 387 - 0x85, 0x21, 388 - 0x86, 0xc5, 389 - 0x87, 0x01, 439 + R_81_V_SYNC_FLD_ID_SRC_SEL_AND_RETIMED_V_F, 0x01, 440 + 0x82, 0x00, /* Reserved register - value should be zero*/ 441 + R_83_X_PORT_I_O_ENA_AND_OUT_CLK, 0x01, 442 + R_84_I_PORT_SIGNAL_DEF, 0x20, 443 + R_85_I_PORT_SIGNAL_POLAR, 0x21, 444 + R_86_I_PORT_FIFO_FLAG_CNTL_AND_ARBIT, 0xc5, 445 + R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x01, 390 446 391 447 /* Task A */ 392 - 0xa0, 0x01, /* down scale = 1 */ 393 - 0xa1, 0x00, /* prescale accumulation length = 1 */ 394 - 0xa2, 0x00, /* dc gain and fir prefilter control */ 395 - 0xa4, 0x80, /* Lum Brightness, nominal value = 0x80 */ 396 - 0xa5, 0x40, /* Lum contrast, nominal value = 0x40 */ 397 - 0xa6, 0x40, /* Chroma satur. nominal value = 0x80 */ 398 - 0xa8, 0x00, /* hor lum scaling 0x0200 = 2 zoom */ 399 - 0xa9, 0x02, /* note: 2 x zoom ensures that VBI lines have same length as video lines. */ 400 - 0xaa, 0x00, /* H-phase offset Luma = 0 */ 401 - 0xac, 0x00, /* hor chrom scaling 0x0200. must be hor lum scaling / 2 */ 402 - 0xad, 0x01, /* H-scaling incr chroma */ 403 - 0xae, 0x00, /* H-phase offset chroma. must be offset luma / 2 */ 448 + R_A0_A_HORIZ_PRESCALING, 0x01, 449 + R_A1_A_ACCUMULATION_LENGTH, 0x00, 450 + R_A2_A_PRESCALER_DC_GAIN_AND_FIR_PREFILTER, 0x00, 404 451 405 - 0xb0, 0x00, /* V-scaling incr luma low */ 406 - 0xb1, 0x04, /* " hi */ 407 - 0xb2, 0x00, /* V-scaling incr chroma low */ 408 - 0xb3, 0x04, /* " hi */ 409 - 0xb4, 0x01, /* V-scaling mode control */ 410 - 0xb8, 0x00, /* V-phase offset chroma 00 */ 411 - 0xb9, 0x00, /* V-phase offset chroma 01 */ 412 - 0xba, 0x00, /* V-phase offset chroma 10 */ 413 - 0xbb, 0x00, /* V-phase offset chroma 11 */ 414 - 0xbc, 0x00, /* V-phase offset luma 00 */ 415 - 0xbd, 0x00, /* V-phase offset luma 01 */ 416 - 0xbe, 0x00, /* V-phase offset luma 10 */ 417 - 0xbf, 0x00, /* V-phase offset luma 11 */ 452 + /* Configure controls at nominal value*/ 453 + R_A4_A_LUMA_BRIGHTNESS_CNTL, 0x80, 454 + R_A5_A_LUMA_CONTRAST_CNTL, 0x40, 455 + R_A6_A_CHROMA_SATURATION_CNTL, 0x40, 456 + 457 + /* note: 2 x zoom ensures that VBI lines have same length as video lines. */ 458 + R_A8_A_HORIZ_LUMA_SCALING_INC, 0x00, 459 + R_A9_A_HORIZ_LUMA_SCALING_INC_MSB, 0x02, 460 + 461 + R_AA_A_HORIZ_LUMA_PHASE_OFF, 0x00, 462 + 463 + /* must be horiz lum scaling / 2 */ 464 + R_AC_A_HORIZ_CHROMA_SCALING_INC, 0x00, 465 + R_AD_A_HORIZ_CHROMA_SCALING_INC_MSB, 0x01, 466 + 467 + /* must be offset luma / 2 */ 468 + R_AE_A_HORIZ_CHROMA_PHASE_OFF, 0x00, 469 + 470 + R_B0_A_VERT_LUMA_SCALING_INC, 0x00, 471 + R_B1_A_VERT_LUMA_SCALING_INC_MSB, 0x04, 472 + 473 + R_B2_A_VERT_CHROMA_SCALING_INC, 0x00, 474 + R_B3_A_VERT_CHROMA_SCALING_INC_MSB, 0x04, 475 + 476 + R_B4_A_VERT_SCALING_MODE_CNTL, 0x01, 477 + 478 + R_B8_A_VERT_CHROMA_PHASE_OFF_00, 0x00, 479 + R_B9_A_VERT_CHROMA_PHASE_OFF_01, 0x00, 480 + R_BA_A_VERT_CHROMA_PHASE_OFF_10, 0x00, 481 + R_BB_A_VERT_CHROMA_PHASE_OFF_11, 0x00, 482 + 483 + R_BC_A_VERT_LUMA_PHASE_OFF_00, 0x00, 484 + R_BD_A_VERT_LUMA_PHASE_OFF_01, 0x00, 485 + R_BE_A_VERT_LUMA_PHASE_OFF_10, 0x00, 486 + R_BF_A_VERT_LUMA_PHASE_OFF_11, 0x00, 418 487 419 488 /* Task B */ 420 - 0xd0, 0x01, /* down scale = 1 */ 421 - 0xd1, 0x00, /* prescale accumulation length = 1 */ 422 - 0xd2, 0x00, /* dc gain and fir prefilter control */ 423 - 0xd4, 0x80, /* Lum Brightness, nominal value = 0x80 */ 424 - 0xd5, 0x40, /* Lum contrast, nominal value = 0x40 */ 425 - 0xd6, 0x40, /* Chroma satur. nominal value = 0x80 */ 426 - 0xd8, 0x00, /* hor lum scaling 0x0400 = 1 */ 427 - 0xd9, 0x04, 428 - 0xda, 0x00, /* H-phase offset Luma = 0 */ 429 - 0xdc, 0x00, /* hor chrom scaling 0x0200. must be hor lum scaling / 2 */ 430 - 0xdd, 0x02, /* H-scaling incr chroma */ 431 - 0xde, 0x00, /* H-phase offset chroma. must be offset luma / 2 */ 489 + R_D0_B_HORIZ_PRESCALING, 0x01, 490 + R_D1_B_ACCUMULATION_LENGTH, 0x00, 491 + R_D2_B_PRESCALER_DC_GAIN_AND_FIR_PREFILTER, 0x00, 432 492 433 - 0xe0, 0x00, /* V-scaling incr luma low */ 434 - 0xe1, 0x04, /* " hi */ 435 - 0xe2, 0x00, /* V-scaling incr chroma low */ 436 - 0xe3, 0x04, /* " hi */ 437 - 0xe4, 0x01, /* V-scaling mode control */ 438 - 0xe8, 0x00, /* V-phase offset chroma 00 */ 439 - 0xe9, 0x00, /* V-phase offset chroma 01 */ 440 - 0xea, 0x00, /* V-phase offset chroma 10 */ 441 - 0xeb, 0x00, /* V-phase offset chroma 11 */ 442 - 0xec, 0x00, /* V-phase offset luma 00 */ 443 - 0xed, 0x00, /* V-phase offset luma 01 */ 444 - 0xee, 0x00, /* V-phase offset luma 10 */ 445 - 0xef, 0x00, /* V-phase offset luma 11 */ 493 + /* Configure controls at nominal value*/ 494 + R_D4_B_LUMA_BRIGHTNESS_CNTL, 0x80, 495 + R_D5_B_LUMA_CONTRAST_CNTL, 0x40, 496 + R_D6_B_CHROMA_SATURATION_CNTL, 0x40, 446 497 447 - 0xf2, 0x50, /* crystal clock = 24.576 MHz, target = 27MHz */ 448 - 0xf3, 0x46, 449 - 0xf4, 0x00, 450 - 0xf7, 0x4b, /* not the recommended settings! */ 451 - 0xf8, 0x00, 452 - 0xf9, 0x4b, 453 - 0xfa, 0x00, 454 - 0xfb, 0x4b, 455 - 0xff, 0x88, /* PLL2 lock detection settings: 71 lines 50% phase error */ 498 + /* hor lum scaling 0x0400 = 1 */ 499 + R_D8_B_HORIZ_LUMA_SCALING_INC, 0x00, 500 + R_D9_B_HORIZ_LUMA_SCALING_INC_MSB, 0x04, 501 + 502 + R_DA_B_HORIZ_LUMA_PHASE_OFF, 0x00, 503 + 504 + /* must be hor lum scaling / 2 */ 505 + R_DC_B_HORIZ_CHROMA_SCALING, 0x00, 506 + R_DD_B_HORIZ_CHROMA_SCALING_MSB, 0x02, 507 + 508 + /* must be offset luma / 2 */ 509 + R_DE_B_HORIZ_PHASE_OFFSET_CRHOMA, 0x00, 510 + 511 + R_E0_B_VERT_LUMA_SCALING_INC, 0x00, 512 + R_E1_B_VERT_LUMA_SCALING_INC_MSB, 0x04, 513 + 514 + R_E2_B_VERT_CHROMA_SCALING_INC, 0x00, 515 + R_E3_B_VERT_CHROMA_SCALING_INC_MSB, 0x04, 516 + 517 + R_E4_B_VERT_SCALING_MODE_CNTL, 0x01, 518 + 519 + R_E8_B_VERT_CHROMA_PHASE_OFF_00, 0x00, 520 + R_E9_B_VERT_CHROMA_PHASE_OFF_01, 0x00, 521 + R_EA_B_VERT_CHROMA_PHASE_OFF_10, 0x00, 522 + R_EB_B_VERT_CHROMA_PHASE_OFF_11, 0x00, 523 + 524 + R_EC_B_VERT_LUMA_PHASE_OFF_00, 0x00, 525 + R_ED_B_VERT_LUMA_PHASE_OFF_01, 0x00, 526 + R_EE_B_VERT_LUMA_PHASE_OFF_10, 0x00, 527 + R_EF_B_VERT_LUMA_PHASE_OFF_11, 0x00, 528 + 529 + R_F2_NOMINAL_PLL2_DTO, 0x50, /* crystal clock = 24.576 MHz, target = 27MHz */ 530 + R_F3_PLL_INCREMENT, 0x46, 531 + R_F4_PLL2_STATUS, 0x00, 532 + R_F7_PULSE_A_POS_MSB, 0x4b, /* not the recommended settings! */ 533 + R_F8_PULSE_B_POS, 0x00, 534 + R_F9_PULSE_B_POS_MSB, 0x4b, 535 + R_FA_PULSE_C_POS, 0x00, 536 + R_FB_PULSE_C_POS_MSB, 0x4b, 537 + 538 + /* PLL2 lock detection settings: 71 lines 50% phase error */ 539 + R_FF_S_PLL_MAX_PHASE_ERR_THRESH_NUM_LINES, 0x88, 456 540 457 541 /* Turn off VBI */ 458 - 0x40, 0x20, /* No framing code errors allowed. */ 459 - 0x41, 0xff, 460 - 0x42, 0xff, 461 - 0x43, 0xff, 462 - 0x44, 0xff, 463 - 0x45, 0xff, 464 - 0x46, 0xff, 465 - 0x47, 0xff, 466 - 0x48, 0xff, 467 - 0x49, 0xff, 468 - 0x4a, 0xff, 469 - 0x4b, 0xff, 470 - 0x4c, 0xff, 471 - 0x4d, 0xff, 472 - 0x4e, 0xff, 473 - 0x4f, 0xff, 474 - 0x50, 0xff, 475 - 0x51, 0xff, 476 - 0x52, 0xff, 477 - 0x53, 0xff, 478 - 0x54, 0xff, 479 - 0x55, 0xff, 480 - 0x56, 0xff, 481 - 0x57, 0xff, 482 - 0x58, 0x40, 483 - 0x59, 0x47, 484 - 0x5b, 0x83, 485 - 0x5d, 0xbd, 486 - 0x5e, 0x35, 542 + R_40_SLICER_CNTL_1, 0x20, /* No framing code errors allowed. */ 543 + R_41_LCR_BASE, 0xff, 544 + R_41_LCR_BASE+1, 0xff, 545 + R_41_LCR_BASE+2, 0xff, 546 + R_41_LCR_BASE+3, 0xff, 547 + R_41_LCR_BASE+4, 0xff, 548 + R_41_LCR_BASE+5, 0xff, 549 + R_41_LCR_BASE+6, 0xff, 550 + R_41_LCR_BASE+7, 0xff, 551 + R_41_LCR_BASE+8, 0xff, 552 + R_41_LCR_BASE+9, 0xff, 553 + R_41_LCR_BASE+10, 0xff, 554 + R_41_LCR_BASE+11, 0xff, 555 + R_41_LCR_BASE+12, 0xff, 556 + R_41_LCR_BASE+13, 0xff, 557 + R_41_LCR_BASE+14, 0xff, 558 + R_41_LCR_BASE+15, 0xff, 559 + R_41_LCR_BASE+16, 0xff, 560 + R_41_LCR_BASE+17, 0xff, 561 + R_41_LCR_BASE+18, 0xff, 562 + R_41_LCR_BASE+19, 0xff, 563 + R_41_LCR_BASE+20, 0xff, 564 + R_41_LCR_BASE+21, 0xff, 565 + R_41_LCR_BASE+22, 0xff, 566 + R_58_PROGRAM_FRAMING_CODE, 0x40, 567 + R_59_H_OFF_FOR_SLICER, 0x47, 568 + R_5B_FLD_OFF_AND_MSB_FOR_H_AND_V_OFF, 0x83, 569 + R_5D_DID, 0xbd, 570 + R_5E_SDID, 0x35, 487 571 488 - 0x02, 0x84, /* input tuner -> input 4, amplifier active */ 489 - 0x09, 0x53, /* 0x53, was 0x56 for 60hz. luminance control */ 572 + R_02_INPUT_CNTL_1, 0x84, /* input tuner -> input 4, amplifier active */ 573 + R_09_LUMA_CNTL, 0x53, /* 0x53, was 0x56 for 60hz. luminance control */ 490 574 491 - 0x80, 0x20, /* enable task B */ 492 - 0x88, 0xd0, 493 - 0x88, 0xf0, 575 + R_80_GLOBAL_CNTL_1, 0x20, /* enable task B */ 576 + R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0, 577 + R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0, 494 578 0x00, 0x00 495 579 }; 496 580 ··· 703 617 if (state->apll) 704 618 acc |= 0x08; 705 619 706 - saa7115_write(client, 0x38, 0x03); 707 - saa7115_write(client, 0x39, 0x10); 708 - saa7115_write(client, 0x3a, acc); 709 - saa7115_write(client, 0x30, acpf & 0xff); 710 - saa7115_write(client, 0x31, (acpf >> 8) & 0xff); 711 - saa7115_write(client, 0x32, (acpf >> 16) & 0x03); 712 - saa7115_write(client, 0x34, acni & 0xff); 713 - saa7115_write(client, 0x35, (acni >> 8) & 0xff); 714 - saa7115_write(client, 0x36, (acni >> 16) & 0x3f); 620 + saa7115_write(client, R_38_CLK_RATIO_AMXCLK_TO_ASCLK, 0x03); 621 + saa7115_write(client, R_39_CLK_RATIO_ASCLK_TO_ALRCLK, 0x10); 622 + saa7115_write(client, R_3A_AUD_CLK_GEN_BASIC_SETUP, acc); 623 + 624 + saa7115_write(client, R_30_AUD_MAST_CLK_CYCLES_PER_FIELD, acpf & 0xff); 625 + saa7115_write(client, R_30_AUD_MAST_CLK_CYCLES_PER_FIELD+1, 626 + (acpf >> 8) & 0xff); 627 + saa7115_write(client, R_30_AUD_MAST_CLK_CYCLES_PER_FIELD+2, 628 + (acpf >> 16) & 0x03); 629 + 630 + saa7115_write(client, R_34_AUD_MAST_CLK_NOMINAL_INC, acni & 0xff); 631 + saa7115_write(client, R_34_AUD_MAST_CLK_NOMINAL_INC+1, (acni >> 8) & 0xff); 632 + saa7115_write(client, R_34_AUD_MAST_CLK_NOMINAL_INC+2, (acni >> 16) & 0x3f); 715 633 state->audclk_freq = freq; 716 634 return 0; 717 635 } ··· 732 642 } 733 643 734 644 state->bright = ctrl->value; 735 - saa7115_write(client, 0x0a, state->bright); 645 + saa7115_write(client, R_0A_LUMA_BRIGHT_CNTL, state->bright); 736 646 break; 737 647 738 648 case V4L2_CID_CONTRAST: ··· 742 652 } 743 653 744 654 state->contrast = ctrl->value; 745 - saa7115_write(client, 0x0b, state->contrast); 655 + saa7115_write(client, R_0B_LUMA_CONTRAST_CNTL, state->contrast); 746 656 break; 747 657 748 658 case V4L2_CID_SATURATION: ··· 752 662 } 753 663 754 664 state->sat = ctrl->value; 755 - saa7115_write(client, 0x0c, state->sat); 665 + saa7115_write(client, R_0C_CHROMA_SAT_CNTL, state->sat); 756 666 break; 757 667 758 668 case V4L2_CID_HUE: ··· 762 672 } 763 673 764 674 state->hue = ctrl->value; 765 - saa7115_write(client, 0x0d, state->hue); 675 + saa7115_write(client, R_0D_CHROMA_HUE_CNTL, state->hue); 766 676 break; 767 677 768 678 default: ··· 799 709 static void saa7115_set_v4lstd(struct i2c_client *client, v4l2_std_id std) 800 710 { 801 711 struct saa7115_state *state = i2c_get_clientdata(client); 802 - int taskb = saa7115_read(client, 0x80) & 0x10; 712 + int taskb = saa7115_read(client, R_80_GLOBAL_CNTL_1) & 0x10; 803 713 804 714 /* Prevent unnecessary standard changes. During a standard 805 715 change the I-Port is temporarily disabled. Any devices ··· 830 740 100 reserved NTSC-Japan (3.58MHz) 831 741 */ 832 742 if (state->ident == V4L2_IDENT_SAA7113) { 833 - u8 reg = saa7115_read(client, 0x0e) & 0x8f; 743 + u8 reg = saa7115_read(client, R_0E_CHROMA_CNTL_1) & 0x8f; 834 744 835 745 if (std == V4L2_STD_PAL_M) { 836 746 reg |= 0x30; ··· 841 751 } else if (std == V4L2_STD_NTSC_M_JP) { 842 752 reg |= 0x40; 843 753 } 844 - saa7115_write(client, 0x0e, reg); 754 + saa7115_write(client, R_0E_CHROMA_CNTL_1, reg); 845 755 } 846 756 847 757 ··· 873 783 v4l_info(client, "Audio frequency: %d Hz\n", state->audclk_freq); 874 784 if (state->ident != V4L2_IDENT_SAA7115) { 875 785 /* status for the saa7114 */ 876 - reg1f = saa7115_read(client, 0x1f); 786 + reg1f = saa7115_read(client, R_1F_STATUS_BYTE_2_VD_DEC); 877 787 signalOk = (reg1f & 0xc1) == 0x81; 878 788 v4l_info(client, "Video signal: %s\n", signalOk ? "ok" : "bad"); 879 789 v4l_info(client, "Frequency: %s\n", (reg1f & 0x20) ? "60 Hz" : "50 Hz"); ··· 881 791 } 882 792 883 793 /* status for the saa7115 */ 884 - reg1e = saa7115_read(client, 0x1e); 885 - reg1f = saa7115_read(client, 0x1f); 794 + reg1e = saa7115_read(client, R_1E_STATUS_BYTE_1_VD_DEC); 795 + reg1f = saa7115_read(client, R_1F_STATUS_BYTE_2_VD_DEC); 886 796 887 797 signalOk = (reg1f & 0xc1) == 0x81 && (reg1e & 0xc0) == 0x80; 888 798 vcr = !(reg1f & 0x10); ··· 978 888 979 889 /* write the lcr registers */ 980 890 for (i = 2; i <= 23; i++) { 981 - saa7115_write(client, i - 2 + 0x41, lcr[i]); 891 + saa7115_write(client, i - 2 + R_41_LCR_BASE, lcr[i]); 982 892 } 983 893 984 894 /* enable/disable raw VBI capturing */ 985 - saa7115_writeregs(client, fmt->service_set == 0 ? saa7115_cfg_vbi_on : saa7115_cfg_vbi_off); 895 + saa7115_writeregs(client, fmt->service_set == 0 ? 896 + saa7115_cfg_vbi_on : 897 + saa7115_cfg_vbi_off); 986 898 } 987 899 988 900 static int saa7115_get_v4lfmt(struct i2c_client *client, struct v4l2_format *fmt) ··· 1003 911 return -EINVAL; 1004 912 memset(sliced, 0, sizeof(*sliced)); 1005 913 /* done if using raw VBI */ 1006 - if (saa7115_read(client, 0x80) & 0x10) 914 + if (saa7115_read(client, R_80_GLOBAL_CNTL_1) & 0x10) 1007 915 return 0; 1008 916 for (i = 2; i <= 23; i++) { 1009 - u8 v = saa7115_read(client, i - 2 + 0x41); 917 + u8 v = saa7115_read(client, i - 2 + R_41_LCR_BASE); 1010 918 1011 919 sliced->service_lines[0][i] = lcr2vbi[v >> 4]; 1012 920 sliced->service_lines[1][i] = lcr2vbi[v & 0xf]; ··· 1044 952 /* probably have a valid size, let's set it */ 1045 953 /* Set output width/height */ 1046 954 /* width */ 1047 - saa7115_write(client, 0xcc, (u8) (pix->width & 0xff)); 1048 - saa7115_write(client, 0xcd, (u8) ((pix->width >> 8) & 0xff)); 955 + saa7115_write(client, R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH, 956 + (u8) (pix->width & 0xff)); 957 + saa7115_write(client, R_CD_B_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 958 + (u8) ((pix->width >> 8) & 0xff)); 1049 959 /* height */ 1050 - saa7115_write(client, 0xce, (u8) (pix->height & 0xff)); 1051 - saa7115_write(client, 0xcf, (u8) ((pix->height >> 8) & 0xff)); 960 + saa7115_write(client, R_CE_B_VERT_OUTPUT_WINDOW_LENGTH, 961 + (u8) (pix->height & 0xff)); 962 + saa7115_write(client, R_CF_B_VERT_OUTPUT_WINDOW_LENGTH_MSB, 963 + (u8) ((pix->height >> 8) & 0xff)); 1052 964 1053 965 /* Scaling settings */ 1054 966 /* Hprescaler is floor(inres/outres) */ ··· 1066 970 v4l_dbg(1, debug, client, "Hpsc: 0x%05x, Hfsc: 0x%05x\n", HPSC, HFSC); 1067 971 /* FIXME hardcodes to "Task B" 1068 972 * write H prescaler integer */ 1069 - saa7115_write(client, 0xd0, (u8) (HPSC & 0x3f)); 973 + saa7115_write(client, R_D0_B_HORIZ_PRESCALING, 974 + (u8) (HPSC & 0x3f)); 1070 975 1071 976 /* write H fine-scaling (luminance) */ 1072 - saa7115_write(client, 0xd8, (u8) (HFSC & 0xff)); 1073 - saa7115_write(client, 0xd9, (u8) ((HFSC >> 8) & 0xff)); 977 + saa7115_write(client, R_D8_B_HORIZ_LUMA_SCALING_INC, 978 + (u8) (HFSC & 0xff)); 979 + saa7115_write(client, R_D9_B_HORIZ_LUMA_SCALING_INC_MSB, 980 + (u8) ((HFSC >> 8) & 0xff)); 1074 981 /* write H fine-scaling (chrominance) 1075 982 * must be lum/2, so i'll just bitshift :) */ 1076 - saa7115_write(client, 0xDC, (u8) ((HFSC >> 1) & 0xff)); 1077 - saa7115_write(client, 0xDD, (u8) ((HFSC >> 9) & 0xff)); 983 + saa7115_write(client, R_DC_B_HORIZ_CHROMA_SCALING, 984 + (u8) ((HFSC >> 1) & 0xff)); 985 + saa7115_write(client, R_DD_B_HORIZ_CHROMA_SCALING_MSB, 986 + (u8) ((HFSC >> 9) & 0xff)); 1078 987 } else { 1079 988 if (is_50hz) { 1080 989 v4l_dbg(1, debug, client, "Setting full 50hz width\n"); ··· 1097 996 v4l_dbg(1, debug, client, "Vsrc: %d, Vscy: 0x%05x\n", Vsrc, VSCY); 1098 997 1099 998 /* Correct Contrast and Luminance */ 1100 - saa7115_write(client, 0xd5, (u8) (64 * 1024 / VSCY)); 1101 - saa7115_write(client, 0xd6, (u8) (64 * 1024 / VSCY)); 999 + saa7115_write(client, R_D5_B_LUMA_CONTRAST_CNTL, 1000 + (u8) (64 * 1024 / VSCY)); 1001 + saa7115_write(client, R_D6_B_CHROMA_SATURATION_CNTL, 1002 + (u8) (64 * 1024 / VSCY)); 1102 1003 1103 1004 /* write V fine-scaling (luminance) */ 1104 - saa7115_write(client, 0xe0, (u8) (VSCY & 0xff)); 1105 - saa7115_write(client, 0xe1, (u8) ((VSCY >> 8) & 0xff)); 1005 + saa7115_write(client, R_E0_B_VERT_LUMA_SCALING_INC, 1006 + (u8) (VSCY & 0xff)); 1007 + saa7115_write(client, R_E1_B_VERT_LUMA_SCALING_INC_MSB, 1008 + (u8) ((VSCY >> 8) & 0xff)); 1106 1009 /* write V fine-scaling (chrominance) */ 1107 - saa7115_write(client, 0xe2, (u8) (VSCY & 0xff)); 1108 - saa7115_write(client, 0xe3, (u8) ((VSCY >> 8) & 0xff)); 1010 + saa7115_write(client, R_E2_B_VERT_CHROMA_SCALING_INC, 1011 + (u8) (VSCY & 0xff)); 1012 + saa7115_write(client, R_E3_B_VERT_CHROMA_SCALING_INC_MSB, 1013 + (u8) ((VSCY >> 8) & 0xff)); 1109 1014 } else { 1110 1015 if (is_50hz) { 1111 1016 v4l_dbg(1, debug, client, "Setting full 50Hz height\n"); ··· 1130 1023 The format is described in the saa7115 datasheet in Tables 25 and 26 1131 1024 and in Figure 33. 1132 1025 The current implementation uses SAV/EAV codes and not the ancillary data 1133 - headers. The vbi->p pointer points to the SDID byte right after the SAV 1026 + headers. The vbi->p pointer points to the R_5E_SDID byte right after the SAV 1134 1027 code. */ 1135 1028 static void saa7115_decode_vbi_line(struct i2c_client *client, 1136 1029 struct v4l2_decode_vbi_line *vbi) ··· 1220 1113 1221 1114 if (state->radio) 1222 1115 break; 1223 - status = saa7115_read(client, 0x1f); 1116 + status = saa7115_read(client, R_1F_STATUS_BYTE_2_VD_DEC); 1224 1117 1225 1118 v4l_dbg(1, debug, client, "status: 0x%02x\n", status); 1226 1119 vt->signal = ((status & (1 << 6)) == 0) ? 0xffff : 0x0; ··· 1294 1187 state->input = route->input; 1295 1188 1296 1189 /* select mode */ 1297 - saa7115_write(client, 0x02, 1298 - (saa7115_read(client, 0x02) & 0xf0) | 1190 + saa7115_write(client, R_02_INPUT_CNTL_1, 1191 + (saa7115_read(client, R_02_INPUT_CNTL_1) & 0xf0) | 1299 1192 state->input); 1300 1193 1301 1194 /* bypass chrominance trap for S-Video modes */ 1302 - saa7115_write(client, 0x09, 1303 - (saa7115_read(client, 0x09) & 0x7f) | 1195 + saa7115_write(client, R_09_LUMA_CNTL, 1196 + (saa7115_read(client, R_09_LUMA_CNTL) & 0x7f) | 1304 1197 (state->input >= SAA7115_SVIDEO0 ? 0x80 : 0x0)); 1305 1198 break; 1306 1199 } ··· 1312 1205 1313 1206 if (state->enable != (cmd == VIDIOC_STREAMON)) { 1314 1207 state->enable = (cmd == VIDIOC_STREAMON); 1315 - saa7115_write(client, 0x87, state->enable); 1208 + saa7115_write(client, 1209 + R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 1210 + state->enable); 1316 1211 } 1317 1212 break; 1318 1213 ··· 1501 1392 i2c_attach_client(client); 1502 1393 1503 1394 v4l_dbg(1, debug, client, "status: (1E) 0x%02x, (1F) 0x%02x\n", 1504 - saa7115_read(client, 0x1e), saa7115_read(client, 0x1f)); 1395 + saa7115_read(client, R_1E_STATUS_BYTE_1_VD_DEC), saa7115_read(client, R_1F_STATUS_BYTE_2_VD_DEC)); 1505 1396 1506 1397 return 0; 1507 1398 }
+549
drivers/media/video/saa711x_regs.h
··· 1 + /* saa711x - Philips SAA711x video decoder register specifications 2 + * 3 + * Copyright (c) 2006 Mauro Carvalho Chehab <mchehab@infradead.org> 4 + * 5 + * This program is free software; you can redistribute it and/or 6 + * modify it under the terms of the GNU General Public License 7 + * as published by the Free Software Foundation; either version 2 8 + * of the License, or (at your option) any later version. 9 + * 10 + * This program is distributed in the hope that it will be useful, 11 + * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 + * GNU General Public License for more details. 14 + */ 15 + 16 + #define R_00_CHIP_VERSION 0x00 17 + /* Video Decoder */ 18 + /* Video Decoder - Frontend part */ 19 + #define R_01_INC_DELAY 0x01 20 + #define R_02_INPUT_CNTL_1 0x02 21 + #define R_03_INPUT_CNTL_2 0x03 22 + #define R_04_INPUT_CNTL_3 0x04 23 + #define R_05_INPUT_CNTL_4 0x05 24 + /* Video Decoder - Decoder part */ 25 + #define R_06_H_SYNC_START 0x06 26 + #define R_07_H_SYNC_STOP 0x07 27 + #define R_08_SYNC_CNTL 0x08 28 + #define R_09_LUMA_CNTL 0x09 29 + #define R_0A_LUMA_BRIGHT_CNTL 0x0a 30 + #define R_0B_LUMA_CONTRAST_CNTL 0x0b 31 + #define R_0C_CHROMA_SAT_CNTL 0x0c 32 + #define R_0D_CHROMA_HUE_CNTL 0x0d 33 + #define R_0E_CHROMA_CNTL_1 0x0e 34 + #define R_0F_CHROMA_GAIN_CNTL 0x0f 35 + #define R_10_CHROMA_CNTL_2 0x10 36 + #define R_11_MODE_DELAY_CNTL 0x11 37 + #define R_12_RT_SIGNAL_CNTL 0x12 38 + #define R_13_RT_X_PORT_OUT_CNTL 0x13 39 + #define R_14_ANAL_ADC_COMPAT_CNTL 0x14 40 + #define R_15_VGATE_START_FID_CHG 0x15 41 + #define R_16_VGATE_STOP 0x16 42 + #define R_17_MISC_VGATE_CONF_AND_MSB 0x17 43 + #define R_18_RAW_DATA_GAIN_CNTL 0x18 44 + #define R_19_RAW_DATA_OFF_CNTL 0x19 45 + #define R_1A_COLOR_KILL_LVL_CNTL 0x1a 46 + #define R_1B_MISC_TVVCRDET 0x1b 47 + #define R_1C_ENHAN_COMB_CTRL1 0x1c 48 + #define R_1D_ENHAN_COMB_CTRL2 0x1d 49 + #define R_1E_STATUS_BYTE_1_VD_DEC 0x1e 50 + #define R_1F_STATUS_BYTE_2_VD_DEC 0x1f 51 + 52 + /* Component processing and interrupt masking part */ 53 + #define R_23_INPUT_CNTL_5 0x23 54 + #define R_24_INPUT_CNTL_6 0x24 55 + #define R_25_INPUT_CNTL_7 0x25 56 + #define R_29_COMP_DELAY 0x29 57 + #define R_2A_COMP_BRIGHT_CNTL 0x2a 58 + #define R_2B_COMP_CONTRAST_CNTL 0x2b 59 + #define R_2C_COMP_SAT_CNTL 0x2c 60 + #define R_2D_INTERRUPT_MASK_1 0x2d 61 + #define R_2E_INTERRUPT_MASK_2 0x2e 62 + #define R_2F_INTERRUPT_MASK_3 0x2f 63 + 64 + /* Audio clock generator part */ 65 + #define R_30_AUD_MAST_CLK_CYCLES_PER_FIELD 0x30 66 + #define R_34_AUD_MAST_CLK_NOMINAL_INC 0x34 67 + #define R_38_CLK_RATIO_AMXCLK_TO_ASCLK 0x38 68 + #define R_39_CLK_RATIO_ASCLK_TO_ALRCLK 0x39 69 + #define R_3A_AUD_CLK_GEN_BASIC_SETUP 0x3a 70 + 71 + /* General purpose VBI data slicer part */ 72 + #define R_40_SLICER_CNTL_1 0x40 73 + #define R_41_LCR_BASE 0x41 74 + #define R_58_PROGRAM_FRAMING_CODE 0x58 75 + #define R_59_H_OFF_FOR_SLICER 0x59 76 + #define R_5A_V_OFF_FOR_SLICER 0x5a 77 + #define R_5B_FLD_OFF_AND_MSB_FOR_H_AND_V_OFF 0x5b 78 + #define R_5D_DID 0x5d 79 + #define R_5E_SDID 0x5e 80 + #define R_60_SLICER_STATUS_BYTE_0 0x60 81 + #define R_61_SLICER_STATUS_BYTE_1 0x61 82 + #define R_62_SLICER_STATUS_BYTE_2 0x62 83 + 84 + /* X port, I port and the scaler part */ 85 + /* Task independent global settings */ 86 + #define R_80_GLOBAL_CNTL_1 0x80 87 + #define R_81_V_SYNC_FLD_ID_SRC_SEL_AND_RETIMED_V_F 0x81 88 + #define R_83_X_PORT_I_O_ENA_AND_OUT_CLK 0x83 89 + #define R_84_I_PORT_SIGNAL_DEF 0x84 90 + #define R_85_I_PORT_SIGNAL_POLAR 0x85 91 + #define R_86_I_PORT_FIFO_FLAG_CNTL_AND_ARBIT 0x86 92 + #define R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED 0x87 93 + #define R_88_POWER_SAVE_ADC_PORT_CNTL 0x88 94 + #define R_8F_STATUS_INFO_SCALER 0x8f 95 + /* Task A definition */ 96 + /* Basic settings and acquisition window definition */ 97 + #define R_90_A_TASK_HANDLING_CNTL 0x90 98 + #define R_91_A_X_PORT_FORMATS_AND_CONF 0x91 99 + #define R_92_A_X_PORT_INPUT_REFERENCE_SIGNAL 0x92 100 + #define R_93_A_I_PORT_OUTPUT_FORMATS_AND_CONF 0x93 101 + #define R_94_A_HORIZ_INPUT_WINDOW_START 0x94 102 + #define R_95_A_HORIZ_INPUT_WINDOW_START_MSB 0x95 103 + #define R_96_A_HORIZ_INPUT_WINDOW_LENGTH 0x96 104 + #define R_97_A_HORIZ_INPUT_WINDOW_LENGTH_MSB 0x97 105 + #define R_98_A_VERT_INPUT_WINDOW_START 0x98 106 + #define R_99_A_VERT_INPUT_WINDOW_START_MSB 0x99 107 + #define R_9A_A_VERT_INPUT_WINDOW_LENGTH 0x9a 108 + #define R_9B_A_VERT_INPUT_WINDOW_LENGTH_MSB 0x9b 109 + #define R_9C_A_HORIZ_OUTPUT_WINDOW_LENGTH 0x9c 110 + #define R_9D_A_HORIZ_OUTPUT_WINDOW_LENGTH_MSB 0x9d 111 + #define R_9E_A_VERT_OUTPUT_WINDOW_LENGTH 0x9e 112 + #define R_9F_A_VERT_OUTPUT_WINDOW_LENGTH_MSB 0x9f 113 + /* FIR filtering and prescaling */ 114 + #define R_A0_A_HORIZ_PRESCALING 0xa0 115 + #define R_A1_A_ACCUMULATION_LENGTH 0xa1 116 + #define R_A2_A_PRESCALER_DC_GAIN_AND_FIR_PREFILTER 0xa2 117 + #define R_A4_A_LUMA_BRIGHTNESS_CNTL 0xa4 118 + #define R_A5_A_LUMA_CONTRAST_CNTL 0xa5 119 + #define R_A6_A_CHROMA_SATURATION_CNTL 0xa6 120 + /* Horizontal phase scaling */ 121 + #define R_A8_A_HORIZ_LUMA_SCALING_INC 0xa8 122 + #define R_A9_A_HORIZ_LUMA_SCALING_INC_MSB 0xa9 123 + #define R_AA_A_HORIZ_LUMA_PHASE_OFF 0xaa 124 + #define R_AC_A_HORIZ_CHROMA_SCALING_INC 0xac 125 + #define R_AD_A_HORIZ_CHROMA_SCALING_INC_MSB 0xad 126 + #define R_AE_A_HORIZ_CHROMA_PHASE_OFF 0xae 127 + #define R_AF_A_HORIZ_CHROMA_PHASE_OFF_MSB 0xaf 128 + /* Vertical scaling */ 129 + #define R_B0_A_VERT_LUMA_SCALING_INC 0xb0 130 + #define R_B1_A_VERT_LUMA_SCALING_INC_MSB 0xb1 131 + #define R_B2_A_VERT_CHROMA_SCALING_INC 0xb2 132 + #define R_B3_A_VERT_CHROMA_SCALING_INC_MSB 0xb3 133 + #define R_B4_A_VERT_SCALING_MODE_CNTL 0xb4 134 + #define R_B8_A_VERT_CHROMA_PHASE_OFF_00 0xb8 135 + #define R_B9_A_VERT_CHROMA_PHASE_OFF_01 0xb9 136 + #define R_BA_A_VERT_CHROMA_PHASE_OFF_10 0xba 137 + #define R_BB_A_VERT_CHROMA_PHASE_OFF_11 0xbb 138 + #define R_BC_A_VERT_LUMA_PHASE_OFF_00 0xbc 139 + #define R_BD_A_VERT_LUMA_PHASE_OFF_01 0xbd 140 + #define R_BE_A_VERT_LUMA_PHASE_OFF_10 0xbe 141 + #define R_BF_A_VERT_LUMA_PHASE_OFF_11 0xbf 142 + /* Task B definition */ 143 + /* Basic settings and acquisition window definition */ 144 + #define R_C0_B_TASK_HANDLING_CNTL 0xc0 145 + #define R_C1_B_X_PORT_FORMATS_AND_CONF 0xc1 146 + #define R_C2_B_INPUT_REFERENCE_SIGNAL_DEFINITION 0xc2 147 + #define R_C3_B_I_PORT_FORMATS_AND_CONF 0xc3 148 + #define R_C4_B_HORIZ_INPUT_WINDOW_START 0xc4 149 + #define R_C5_B_HORIZ_INPUT_WINDOW_START_MSB 0xc5 150 + #define R_C6_B_HORIZ_INPUT_WINDOW_LENGTH 0xc6 151 + #define R_C7_B_HORIZ_INPUT_WINDOW_LENGTH_MSB 0xc7 152 + #define R_C8_B_VERT_INPUT_WINDOW_START 0xc8 153 + #define R_C9_B_VERT_INPUT_WINDOW_START_MSB 0xc9 154 + #define R_CA_B_VERT_INPUT_WINDOW_LENGTH 0xca 155 + #define R_CB_B_VERT_INPUT_WINDOW_LENGTH_MSB 0xcb 156 + #define R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH 0xcc 157 + #define R_CD_B_HORIZ_OUTPUT_WINDOW_LENGTH_MSB 0xcd 158 + #define R_CE_B_VERT_OUTPUT_WINDOW_LENGTH 0xce 159 + #define R_CF_B_VERT_OUTPUT_WINDOW_LENGTH_MSB 0xcf 160 + /* FIR filtering and prescaling */ 161 + #define R_D0_B_HORIZ_PRESCALING 0xd0 162 + #define R_D1_B_ACCUMULATION_LENGTH 0xd1 163 + #define R_D2_B_PRESCALER_DC_GAIN_AND_FIR_PREFILTER 0xd2 164 + #define R_D4_B_LUMA_BRIGHTNESS_CNTL 0xd4 165 + #define R_D5_B_LUMA_CONTRAST_CNTL 0xd5 166 + #define R_D6_B_CHROMA_SATURATION_CNTL 0xd6 167 + /* Horizontal phase scaling */ 168 + #define R_D8_B_HORIZ_LUMA_SCALING_INC 0xd8 169 + #define R_D9_B_HORIZ_LUMA_SCALING_INC_MSB 0xd9 170 + #define R_DA_B_HORIZ_LUMA_PHASE_OFF 0xda 171 + #define R_DC_B_HORIZ_CHROMA_SCALING 0xdc 172 + #define R_DD_B_HORIZ_CHROMA_SCALING_MSB 0xdd 173 + #define R_DE_B_HORIZ_PHASE_OFFSET_CRHOMA 0xde 174 + /* Vertical scaling */ 175 + #define R_E0_B_VERT_LUMA_SCALING_INC 0xe0 176 + #define R_E1_B_VERT_LUMA_SCALING_INC_MSB 0xe1 177 + #define R_E2_B_VERT_CHROMA_SCALING_INC 0xe2 178 + #define R_E3_B_VERT_CHROMA_SCALING_INC_MSB 0xe3 179 + #define R_E4_B_VERT_SCALING_MODE_CNTL 0xe4 180 + #define R_E8_B_VERT_CHROMA_PHASE_OFF_00 0xe8 181 + #define R_E9_B_VERT_CHROMA_PHASE_OFF_01 0xe9 182 + #define R_EA_B_VERT_CHROMA_PHASE_OFF_10 0xea 183 + #define R_EB_B_VERT_CHROMA_PHASE_OFF_11 0xeb 184 + #define R_EC_B_VERT_LUMA_PHASE_OFF_00 0xec 185 + #define R_ED_B_VERT_LUMA_PHASE_OFF_01 0xed 186 + #define R_EE_B_VERT_LUMA_PHASE_OFF_10 0xee 187 + #define R_EF_B_VERT_LUMA_PHASE_OFF_11 0xef 188 + 189 + /* second PLL (PLL2) and Pulsegenerator Programming */ 190 + #define R_F0_LFCO_PER_LINE 0xf0 191 + #define R_F1_P_I_PARAM_SELECT 0xf1 192 + #define R_F2_NOMINAL_PLL2_DTO 0xf2 193 + #define R_F3_PLL_INCREMENT 0xf3 194 + #define R_F4_PLL2_STATUS 0xf4 195 + #define R_F5_PULSGEN_LINE_LENGTH 0xf5 196 + #define R_F6_PULSE_A_POS_LSB_AND_PULSEGEN_CONFIG 0xf6 197 + #define R_F7_PULSE_A_POS_MSB 0xf7 198 + #define R_F8_PULSE_B_POS 0xf8 199 + #define R_F9_PULSE_B_POS_MSB 0xf9 200 + #define R_FA_PULSE_C_POS 0xfa 201 + #define R_FB_PULSE_C_POS_MSB 0xfb 202 + #define R_FF_S_PLL_MAX_PHASE_ERR_THRESH_NUM_LINES 0xff 203 + 204 + #if 0 205 + /* Those structs will be used in the future for debug purposes */ 206 + struct saa711x_reg_descr { 207 + u8 reg; 208 + int count; 209 + char *name; 210 + }; 211 + 212 + struct saa711x_reg_descr saa711x_regs[] = { 213 + /* REG COUNT NAME */ 214 + {R_00_CHIP_VERSION,1, 215 + "Chip version"}, 216 + 217 + /* Video Decoder: R_01_INC_DELAY to R_1F_STATUS_BYTE_2_VD_DEC */ 218 + 219 + /* Video Decoder - Frontend part: R_01_INC_DELAY to R_05_INPUT_CNTL_4 */ 220 + {R_01_INC_DELAY,1, 221 + "Increment delay"}, 222 + {R_02_INPUT_CNTL_1,1, 223 + "Analog input control 1"}, 224 + {R_03_INPUT_CNTL_2,1, 225 + "Analog input control 2"}, 226 + {R_04_INPUT_CNTL_3,1, 227 + "Analog input control 3"}, 228 + {R_05_INPUT_CNTL_4,1, 229 + "Analog input control 4"}, 230 + 231 + /* Video Decoder - Decoder part: R_06_H_SYNC_START to R_1F_STATUS_BYTE_2_VD_DEC */ 232 + {R_06_H_SYNC_START,1, 233 + "Horizontal sync start"}, 234 + {R_07_H_SYNC_STOP,1, 235 + "Horizontal sync stop"}, 236 + {R_08_SYNC_CNTL,1, 237 + "Sync control"}, 238 + {R_09_LUMA_CNTL,1, 239 + "Luminance control"}, 240 + {R_0A_LUMA_BRIGHT_CNTL,1, 241 + "Luminance brightness control"}, 242 + {R_0B_LUMA_CONTRAST_CNTL,1, 243 + "Luminance contrast control"}, 244 + {R_0C_CHROMA_SAT_CNTL,1, 245 + "Chrominance saturation control"}, 246 + {R_0D_CHROMA_HUE_CNTL,1, 247 + "Chrominance hue control"}, 248 + {R_0E_CHROMA_CNTL_1,1, 249 + "Chrominance control 1"}, 250 + {R_0F_CHROMA_GAIN_CNTL,1, 251 + "Chrominance gain control"}, 252 + {R_10_CHROMA_CNTL_2,1, 253 + "Chrominance control 2"}, 254 + {R_11_MODE_DELAY_CNTL,1, 255 + "Mode/delay control"}, 256 + {R_12_RT_SIGNAL_CNTL,1, 257 + "RT signal control"}, 258 + {R_13_RT_X_PORT_OUT_CNTL,1, 259 + "RT/X port output control"}, 260 + {R_14_ANAL_ADC_COMPAT_CNTL,1, 261 + "Analog/ADC/compatibility control"}, 262 + {R_15_VGATE_START_FID_CHG, 1, 263 + "VGATE start FID change"}, 264 + {R_16_VGATE_STOP,1, 265 + "VGATE stop"}, 266 + {R_17_MISC_VGATE_CONF_AND_MSB, 1, 267 + "Miscellaneous VGATE configuration and MSBs"}, 268 + {R_18_RAW_DATA_GAIN_CNTL,1, 269 + "Raw data gain control",}, 270 + {R_19_RAW_DATA_OFF_CNTL,1, 271 + "Raw data offset control",}, 272 + {R_1A_COLOR_KILL_LVL_CNTL,1, 273 + "Color Killer Level Control"}, 274 + { R_1B_MISC_TVVCRDET, 1, 275 + "MISC /TVVCRDET"}, 276 + { R_1C_ENHAN_COMB_CTRL1, 1, 277 + "Enhanced comb ctrl1"}, 278 + { R_1D_ENHAN_COMB_CTRL2, 1, 279 + "Enhanced comb ctrl1"}, 280 + {R_1E_STATUS_BYTE_1_VD_DEC,1, 281 + "Status byte 1 video decoder"}, 282 + {R_1F_STATUS_BYTE_2_VD_DEC,1, 283 + "Status byte 2 video decoder"}, 284 + 285 + /* Component processing and interrupt masking part: 0x20h to R_2F_INTERRUPT_MASK_3 */ 286 + /* 0x20 to 0x22 - Reserved */ 287 + {R_23_INPUT_CNTL_5,1, 288 + "Analog input control 5"}, 289 + {R_24_INPUT_CNTL_6,1, 290 + "Analog input control 6"}, 291 + {R_25_INPUT_CNTL_7,1, 292 + "Analog input control 7"}, 293 + /* 0x26 to 0x28 - Reserved */ 294 + {R_29_COMP_DELAY,1, 295 + "Component delay"}, 296 + {R_2A_COMP_BRIGHT_CNTL,1, 297 + "Component brightness control"}, 298 + {R_2B_COMP_CONTRAST_CNTL,1, 299 + "Component contrast control"}, 300 + {R_2C_COMP_SAT_CNTL,1, 301 + "Component saturation control"}, 302 + {R_2D_INTERRUPT_MASK_1,1, 303 + "Interrupt mask 1"}, 304 + {R_2E_INTERRUPT_MASK_2,1, 305 + "Interrupt mask 2"}, 306 + {R_2F_INTERRUPT_MASK_3,1, 307 + "Interrupt mask 3"}, 308 + 309 + /* Audio clock generator part: R_30_AUD_MAST_CLK_CYCLES_PER_FIELD to 0x3f */ 310 + {R_30_AUD_MAST_CLK_CYCLES_PER_FIELD,3, 311 + "Audio master clock cycles per field"}, 312 + /* 0x33 - Reserved */ 313 + {R_34_AUD_MAST_CLK_NOMINAL_INC,3, 314 + "Audio master clock nominal increment"}, 315 + /* 0x37 - Reserved */ 316 + {R_38_CLK_RATIO_AMXCLK_TO_ASCLK,1, 317 + "Clock ratio AMXCLK to ASCLK"}, 318 + {R_39_CLK_RATIO_ASCLK_TO_ALRCLK,1, 319 + "Clock ratio ASCLK to ALRCLK"}, 320 + {R_3A_AUD_CLK_GEN_BASIC_SETUP,1, 321 + "Audio clock generator basic setup"}, 322 + /* 0x3b-0x3f - Reserved */ 323 + 324 + /* General purpose VBI data slicer part: R_40_SLICER_CNTL_1 to 0x7f */ 325 + {R_40_SLICER_CNTL_1,1, 326 + "Slicer control 1"}, 327 + {R_41_LCR,23, 328 + "R_41_LCR"}, 329 + {R_58_PROGRAM_FRAMING_CODE,1, 330 + "Programmable framing code"}, 331 + {R_59_H_OFF_FOR_SLICER,1, 332 + "Horizontal offset for slicer"}, 333 + {R_5A_V_OFF_FOR_SLICER,1, 334 + "Vertical offset for slicer"}, 335 + {R_5B_FLD_OFF_AND_MSB_FOR_H_AND_V_OFF,1, 336 + "Field offset and MSBs for horizontal and vertical offset"}, 337 + {R_5D_DID,1, 338 + "Header and data identification (R_5D_DID)"}, 339 + {R_5E_SDID,1, 340 + "Sliced data identification (R_5E_SDID) code"}, 341 + {R_60_SLICER_STATUS_BYTE_0,1, 342 + "Slicer status byte 0"}, 343 + {R_61_SLICER_STATUS_BYTE_1,1, 344 + "Slicer status byte 1"}, 345 + {R_62_SLICER_STATUS_BYTE_2,1, 346 + "Slicer status byte 2"}, 347 + /* 0x63-0x7f - Reserved */ 348 + 349 + /* X port, I port and the scaler part: R_80_GLOBAL_CNTL_1 to R_EF_B_VERT_LUMA_PHASE_OFF_11 */ 350 + /* Task independent global settings: R_80_GLOBAL_CNTL_1 to R_8F_STATUS_INFO_SCALER */ 351 + {R_80_GLOBAL_CNTL_1,1, 352 + "Global control 1"}, 353 + {R_81_V_SYNC_FLD_ID_SRC_SEL_AND_RETIMED_V_F,1, 354 + "Vertical sync and Field ID source selection, retimed V and F signals"}, 355 + /* 0x82 - Reserved */ 356 + {R_83_X_PORT_I_O_ENA_AND_OUT_CLK,1, 357 + "X port I/O enable and output clock"}, 358 + {R_84_I_PORT_SIGNAL_DEF,1, 359 + "I port signal definitions"}, 360 + {R_85_I_PORT_SIGNAL_POLAR,1, 361 + "I port signal polarities"}, 362 + {R_86_I_PORT_FIFO_FLAG_CNTL_AND_ARBIT,1, 363 + "I port FIFO flag control and arbitration"}, 364 + {R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 1, 365 + "I port I/O enable output clock and gated"}, 366 + {R_88_POWER_SAVE_ADC_PORT_CNTL,1, 367 + "Power save/ADC port control"}, 368 + /* 089-0x8e - Reserved */ 369 + {R_8F_STATUS_INFO_SCALER,1, 370 + "Status information scaler part"}, 371 + 372 + /* Task A definition: R_90_A_TASK_HANDLING_CNTL to R_BF_A_VERT_LUMA_PHASE_OFF_11 */ 373 + /* Task A: Basic settings and acquisition window definition */ 374 + {R_90_A_TASK_HANDLING_CNTL,1, 375 + "Task A: Task handling control"}, 376 + {R_91_A_X_PORT_FORMATS_AND_CONF,1, 377 + "Task A: X port formats and configuration"}, 378 + {R_92_A_X_PORT_INPUT_REFERENCE_SIGNAL,1, 379 + "Task A: X port input reference signal definition"}, 380 + {R_93_A_I_PORT_OUTPUT_FORMATS_AND_CONF,1, 381 + "Task A: I port output formats and configuration"}, 382 + {R_94_A_HORIZ_INPUT_WINDOW_START,2, 383 + "Task A: Horizontal input window start"}, 384 + {R_96_A_HORIZ_INPUT_WINDOW_LENGTH,2, 385 + "Task A: Horizontal input window length"}, 386 + {R_98_A_VERT_INPUT_WINDOW_START,2, 387 + "Task A: Vertical input window start"}, 388 + {R_9A_A_VERT_INPUT_WINDOW_LENGTH,2, 389 + "Task A: Vertical input window length"}, 390 + {R_9C_A_HORIZ_OUTPUT_WINDOW_LENGTH,2, 391 + "Task A: Horizontal output window length"}, 392 + {R_9E_A_VERT_OUTPUT_WINDOW_LENGTH,2, 393 + "Task A: Vertical output window length"}, 394 + 395 + /* Task A: FIR filtering and prescaling */ 396 + {R_A0_A_HORIZ_PRESCALING,1, 397 + "Task A: Horizontal prescaling"}, 398 + {R_A1_A_ACCUMULATION_LENGTH,1, 399 + "Task A: Accumulation length"}, 400 + {R_A2_A_PRESCALER_DC_GAIN_AND_FIR_PREFILTER,1, 401 + "Task A: Prescaler DC gain and FIR prefilter"}, 402 + /* 0xa3 - Reserved */ 403 + {R_A4_A_LUMA_BRIGHTNESS_CNTL,1, 404 + "Task A: Luminance brightness control"}, 405 + {R_A5_A_LUMA_CONTRAST_CNTL,1, 406 + "Task A: Luminance contrast control"}, 407 + {R_A6_A_CHROMA_SATURATION_CNTL,1, 408 + "Task A: Chrominance saturation control"}, 409 + /* 0xa7 - Reserved */ 410 + 411 + /* Task A: Horizontal phase scaling */ 412 + {R_A8_A_HORIZ_LUMA_SCALING_INC,2, 413 + "Task A: Horizontal luminance scaling increment"}, 414 + {R_AA_A_HORIZ_LUMA_PHASE_OFF,1, 415 + "Task A: Horizontal luminance phase offset"}, 416 + /* 0xab - Reserved */ 417 + {R_AC_A_HORIZ_CHROMA_SCALING_INC,2, 418 + "Task A: Horizontal chrominance scaling increment"}, 419 + {R_AE_A_HORIZ_CHROMA_PHASE_OFF,1, 420 + "Task A: Horizontal chrominance phase offset"}, 421 + /* 0xaf - Reserved */ 422 + 423 + /* Task A: Vertical scaling */ 424 + {R_B0_A_VERT_LUMA_SCALING_INC,2, 425 + "Task A: Vertical luminance scaling increment"}, 426 + {R_B2_A_VERT_CHROMA_SCALING_INC,2, 427 + "Task A: Vertical chrominance scaling increment"}, 428 + {R_B4_A_VERT_SCALING_MODE_CNTL,1, 429 + "Task A: Vertical scaling mode control"}, 430 + /* 0xb5-0xb7 - Reserved */ 431 + {R_B8_A_VERT_CHROMA_PHASE_OFF_00,1, 432 + "Task A: Vertical chrominance phase offset '00'"}, 433 + {R_B9_A_VERT_CHROMA_PHASE_OFF_01,1, 434 + "Task A: Vertical chrominance phase offset '01'"}, 435 + {R_BA_A_VERT_CHROMA_PHASE_OFF_10,1, 436 + "Task A: Vertical chrominance phase offset '10'"}, 437 + {R_BB_A_VERT_CHROMA_PHASE_OFF_11,1, 438 + "Task A: Vertical chrominance phase offset '11'"}, 439 + {R_BC_A_VERT_LUMA_PHASE_OFF_00,1, 440 + "Task A: Vertical luminance phase offset '00'"}, 441 + {R_BD_A_VERT_LUMA_PHASE_OFF_01,1, 442 + "Task A: Vertical luminance phase offset '01'"}, 443 + {R_BE_A_VERT_LUMA_PHASE_OFF_10,1, 444 + "Task A: Vertical luminance phase offset '10'"}, 445 + {R_BF_A_VERT_LUMA_PHASE_OFF_11,1, 446 + "Task A: Vertical luminance phase offset '11'"}, 447 + 448 + /* Task B definition: R_C0_B_TASK_HANDLING_CNTL to R_EF_B_VERT_LUMA_PHASE_OFF_11 */ 449 + /* Task B: Basic settings and acquisition window definition */ 450 + {R_C0_B_TASK_HANDLING_CNTL,1, 451 + "Task B: Task handling control"}, 452 + {R_C1_B_X_PORT_FORMATS_AND_CONF,1, 453 + "Task B: X port formats and configuration"}, 454 + {R_C2_B_INPUT_REFERENCE_SIGNAL_DEFINITION,1, 455 + "Task B: Input reference signal definition"}, 456 + {R_C3_B_I_PORT_FORMATS_AND_CONF,1, 457 + "Task B: I port formats and configuration"}, 458 + {R_C4_B_HORIZ_INPUT_WINDOW_START,2, 459 + "Task B: Horizontal input window start"}, 460 + {R_C6_B_HORIZ_INPUT_WINDOW_LENGTH,2, 461 + "Task B: Horizontal input window length"}, 462 + {R_C8_B_VERT_INPUT_WINDOW_START,2, 463 + "Task B: Vertical input window start"}, 464 + {R_CA_B_VERT_INPUT_WINDOW_LENGTH,2, 465 + "Task B: Vertical input window length"}, 466 + {R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH,2, 467 + "Task B: Horizontal output window length"}, 468 + {R_CE_B_VERT_OUTPUT_WINDOW_LENGTH,2, 469 + "Task B: Vertical output window length"}, 470 + 471 + /* Task B: FIR filtering and prescaling */ 472 + {R_D0_B_HORIZ_PRESCALING,1, 473 + "Task B: Horizontal prescaling"}, 474 + {R_D1_B_ACCUMULATION_LENGTH,1, 475 + "Task B: Accumulation length"}, 476 + {R_D2_B_PRESCALER_DC_GAIN_AND_FIR_PREFILTER,1, 477 + "Task B: Prescaler DC gain and FIR prefilter"}, 478 + /* 0xd3 - Reserved */ 479 + {R_D4_B_LUMA_BRIGHTNESS_CNTL,1, 480 + "Task B: Luminance brightness control"}, 481 + {R_D5_B_LUMA_CONTRAST_CNTL,1, 482 + "Task B: Luminance contrast control"}, 483 + {R_D6_B_CHROMA_SATURATION_CNTL,1, 484 + "Task B: Chrominance saturation control"}, 485 + /* 0xd7 - Reserved */ 486 + 487 + /* Task B: Horizontal phase scaling */ 488 + {R_D8_B_HORIZ_LUMA_SCALING_INC,2, 489 + "Task B: Horizontal luminance scaling increment"}, 490 + {R_DA_B_HORIZ_LUMA_PHASE_OFF,1, 491 + "Task B: Horizontal luminance phase offset"}, 492 + /* 0xdb - Reserved */ 493 + {R_DC_B_HORIZ_CHROMA_SCALING,2, 494 + "Task B: Horizontal chrominance scaling"}, 495 + {R_DE_B_HORIZ_PHASE_OFFSET_CRHOMA,1, 496 + "Task B: Horizontal Phase Offset Chroma"}, 497 + /* 0xdf - Reserved */ 498 + 499 + /* Task B: Vertical scaling */ 500 + {R_E0_B_VERT_LUMA_SCALING_INC,2, 501 + "Task B: Vertical luminance scaling increment"}, 502 + {R_E2_B_VERT_CHROMA_SCALING_INC,2, 503 + "Task B: Vertical chrominance scaling increment"}, 504 + {R_E4_B_VERT_SCALING_MODE_CNTL,1, 505 + "Task B: Vertical scaling mode control"}, 506 + /* 0xe5-0xe7 - Reserved */ 507 + {R_E8_B_VERT_CHROMA_PHASE_OFF_00,1, 508 + "Task B: Vertical chrominance phase offset '00'"}, 509 + {R_E9_B_VERT_CHROMA_PHASE_OFF_01,1, 510 + "Task B: Vertical chrominance phase offset '01'"}, 511 + {R_EA_B_VERT_CHROMA_PHASE_OFF_10,1, 512 + "Task B: Vertical chrominance phase offset '10'"}, 513 + {R_EB_B_VERT_CHROMA_PHASE_OFF_11,1, 514 + "Task B: Vertical chrominance phase offset '11'"}, 515 + {R_EC_B_VERT_LUMA_PHASE_OFF_00,1, 516 + "Task B: Vertical luminance phase offset '00'"}, 517 + {R_ED_B_VERT_LUMA_PHASE_OFF_01,1, 518 + "Task B: Vertical luminance phase offset '01'"}, 519 + {R_EE_B_VERT_LUMA_PHASE_OFF_10,1, 520 + "Task B: Vertical luminance phase offset '10'"}, 521 + {R_EF_B_VERT_LUMA_PHASE_OFF_11,1, 522 + "Task B: Vertical luminance phase offset '11'"}, 523 + 524 + /* second PLL (PLL2) and Pulsegenerator Programming */ 525 + { R_F0_LFCO_PER_LINE, 1, 526 + "LFCO's per line"}, 527 + { R_F1_P_I_PARAM_SELECT,1, 528 + "P-/I- Param. Select., PLL Mode, PLL H-Src., LFCO's per line"}, 529 + { R_F2_NOMINAL_PLL2_DTO,1, 530 + "Nominal PLL2 DTO"}, 531 + {R_F3_PLL_INCREMENT,1, 532 + "PLL2 Increment"}, 533 + {R_F4_PLL2_STATUS,1, 534 + "PLL2 Status"}, 535 + {R_F5_PULSGEN_LINE_LENGTH,1, 536 + "Pulsgen. line length"}, 537 + {R_F6_PULSE_A_POS_LSB_AND_PULSEGEN_CONFIG,1, 538 + "Pulse A Position, Pulsgen Resync., Pulsgen. H-Src., Pulsgen. line length"}, 539 + {R_F7_PULSE_A_POS_MSB,1, 540 + "Pulse A Position"}, 541 + {R_F8_PULSE_B_POS,2, 542 + "Pulse B Position"}, 543 + {R_FA_PULSE_C_POS,2, 544 + "Pulse C Position"}, 545 + /* 0xfc to 0xfe - Reserved */ 546 + {R_FF_S_PLL_MAX_PHASE_ERR_THRESH_NUM_LINES,1, 547 + "S_PLL max. phase, error threshold, PLL2 no. of lines, threshold"}, 548 + }; 549 + #endif