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linux
clk: imx: Add support for i.MX8MN clock driver
This patch adds i.MX8MN clock driver support.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
authored by
Anson Huang
and committed by
Shawn Guo
96d6392b
fd6ef285
+643
+6
drivers/clk/imx/Kconfig
+6
drivers/clk/imx/Kconfig
···
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help
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Build the driver for i.MX8MM CCM Clock Driver
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config CLK_IMX8MN
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bool "IMX8MN CCM Clock Driver"
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depends on ARCH_MXC && ARM64
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help
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Build the driver for i.MX8MN CCM Clock Driver
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config CLK_IMX8MQ
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bool "IMX8MQ CCM Clock Driver"
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depends on ARCH_MXC && ARM64
+1
drivers/clk/imx/Makefile
+1
drivers/clk/imx/Makefile
+636
drivers/clk/imx/clk-imx8mn.c
+636
drivers/clk/imx/clk-imx8mn.c
···
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright 2018-2019 NXP.
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*/
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#include <dt-bindings/clock/imx8mn-clock.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/platform_device.h>
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#include <linux/types.h>
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#include "clk.h"
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static u32 share_count_sai2;
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static u32 share_count_sai3;
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static u32 share_count_sai5;
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static u32 share_count_sai6;
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static u32 share_count_sai7;
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static u32 share_count_disp;
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static u32 share_count_pdm;
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static u32 share_count_nand;
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enum {
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ARM_PLL,
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GPU_PLL,
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VPU_PLL,
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SYS_PLL1,
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SYS_PLL2,
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SYS_PLL3,
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DRAM_PLL,
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AUDIO_PLL1,
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AUDIO_PLL2,
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VIDEO_PLL2,
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NR_PLLS,
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};
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static const struct imx_pll14xx_rate_table imx8mn_pll1416x_tbl[] = {
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PLL_1416X_RATE(1800000000U, 225, 3, 0),
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PLL_1416X_RATE(1600000000U, 200, 3, 0),
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PLL_1416X_RATE(1200000000U, 300, 3, 1),
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PLL_1416X_RATE(1000000000U, 250, 3, 1),
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PLL_1416X_RATE(800000000U, 200, 3, 1),
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PLL_1416X_RATE(750000000U, 250, 2, 2),
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PLL_1416X_RATE(700000000U, 350, 3, 2),
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PLL_1416X_RATE(600000000U, 300, 3, 2),
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};
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static const struct imx_pll14xx_rate_table imx8mn_audiopll_tbl[] = {
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PLL_1443X_RATE(786432000U, 655, 5, 2, 23593),
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PLL_1443X_RATE(722534400U, 301, 5, 1, 3670),
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};
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static const struct imx_pll14xx_rate_table imx8mn_videopll_tbl[] = {
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PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
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PLL_1443X_RATE(594000000U, 198, 2, 2, 0),
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};
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static const struct imx_pll14xx_rate_table imx8mn_drampll_tbl[] = {
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PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
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};
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static struct imx_pll14xx_clk imx8mn_audio_pll = {
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.type = PLL_1443X,
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.rate_table = imx8mn_audiopll_tbl,
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};
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static struct imx_pll14xx_clk imx8mn_video_pll = {
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.type = PLL_1443X,
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.rate_table = imx8mn_videopll_tbl,
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};
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static struct imx_pll14xx_clk imx8mn_dram_pll = {
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.type = PLL_1443X,
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.rate_table = imx8mn_drampll_tbl,
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};
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static struct imx_pll14xx_clk imx8mn_arm_pll = {
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.type = PLL_1416X,
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.rate_table = imx8mn_pll1416x_tbl,
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};
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static struct imx_pll14xx_clk imx8mn_gpu_pll = {
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.type = PLL_1416X,
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.rate_table = imx8mn_pll1416x_tbl,
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};
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static struct imx_pll14xx_clk imx8mn_vpu_pll = {
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.type = PLL_1416X,
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.rate_table = imx8mn_pll1416x_tbl,
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};
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static struct imx_pll14xx_clk imx8mn_sys_pll = {
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.type = PLL_1416X,
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.rate_table = imx8mn_pll1416x_tbl,
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};
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static const char * const pll_ref_sels[] = { "osc_24m", "dummy", "dummy", "dummy", };
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static const char * const audio_pll1_bypass_sels[] = {"audio_pll1", "audio_pll1_ref_sel", };
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static const char * const audio_pll2_bypass_sels[] = {"audio_pll2", "audio_pll2_ref_sel", };
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static const char * const video_pll1_bypass_sels[] = {"video_pll1", "video_pll1_ref_sel", };
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static const char * const dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", };
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static const char * const gpu_pll_bypass_sels[] = {"gpu_pll", "gpu_pll_ref_sel", };
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static const char * const vpu_pll_bypass_sels[] = {"vpu_pll", "vpu_pll_ref_sel", };
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static const char * const arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
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static const char * const sys_pll1_bypass_sels[] = {"sys_pll1", "sys_pll1_ref_sel", };
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static const char * const sys_pll2_bypass_sels[] = {"sys_pll2", "sys_pll2_ref_sel", };
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static const char * const sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", };
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static const char * const imx8mn_a53_sels[] = {"osc_24m", "arm_pll_out", "sys_pll2_500m",
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"sys_pll2_1000m", "sys_pll1_800m", "sys_pll1_400m",
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"audio_pll1_out", "sys_pll3_out", };
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static const char * const imx8mn_gpu_core_sels[] = {"osc_24m", "gpu_pll_out", "sys_pll1_800m",
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"sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out",
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"video_pll1_out", "audio_pll2_out", };
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static const char * const imx8mn_gpu_shader_sels[] = {"osc_24m", "gpu_pll_out", "sys_pll1_800m",
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"sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out",
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"video_pll1_out", "audio_pll2_out", };
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static const char * const imx8mn_main_axi_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll1_800m",
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"sys_pll2_250m", "sys_pll2_1000m", "audio_pll1_out",
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"video_pll1_out", "sys_pll1_100m",};
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static const char * const imx8mn_enet_axi_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll1_800m",
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"sys_pll2_250m", "sys_pll2_200m", "audio_pll1_out",
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"video_pll1_out", "sys_pll3_out", };
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static const char * const imx8mn_nand_usdhc_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll1_800m",
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"sys_pll2_200m", "sys_pll1_133m", "sys_pll3_out",
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"sys_pll2_250m", "audio_pll1_out", };
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static const char * const imx8mn_disp_axi_sels[] = {"osc_24m", "sys_pll2_1000m", "sys_pll1_800m",
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"sys_pll3_out", "sys_pll1_40m", "audio_pll2_out",
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"clk_ext1", "clk_ext4", };
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static const char * const imx8mn_disp_apb_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll1_800m",
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"sys_pll3_out", "sys1_pll_40m", "audio_pll2_out",
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"clk_ext1", "clk_ext3", };
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static const char * const imx8mn_usb_bus_sels[] = {"osc_24m", "sys_pll2_500m", "sys_pll1_800m",
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"sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
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"clk_ext4", "audio_pll2_out", };
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static const char * const imx8mn_gpu_axi_sels[] = {"osc_24m", "sys_pll1_800m", "gpu_pll_out",
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"sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out",
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"video_pll1_out", "audio_pll2_out", };
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static const char * const imx8mn_gpu_ahb_sels[] = {"osc_24m", "sys_pll1_800m", "gpu_pll_out",
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"sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out",
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"video_pll1_out", "audio_pll2_out", };
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static const char * const imx8mn_noc_sels[] = {"osc_24m", "sys_pll1_800m", "sys_pll3_out",
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"sys_pll2_1000m", "sys_pll2_500m", "audio_pll1_out",
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"video_pll1_out", "audio_pll2_out", };
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static const char * const imx8mn_ahb_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_800m",
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"sys_pll1_400m", "sys_pll2_125m", "sys_pll3_out",
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"audio_pll1_out", "video_pll1_out", };
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static const char * const imx8mn_audio_ahb_sels[] = {"osc_24m", "sys_pll2_500m", "sys_pll1_800m",
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"sys_pll2_1000m", "sys_pll2_166m", "sys_pll3_out",
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"audio_pll1_out", "video_pll1_out", };
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static const char * const imx8mn_dram_alt_sels[] = {"osc_24m", "sys_pll1_800m", "sys_pll1_100m",
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"sys_pll2_500m", "sys_pll2_1000m", "sys_pll3_out",
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"audio_pll1_out", "sys_pll1_266m", };
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static const char * const imx8mn_dram_apb_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
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"sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
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"sys_pll2_250m", "audio_pll2_out", };
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static const char * const imx8mn_disp_pixel_sels[] = {"osc_24m", "video_pll1_out", "audio_pll2_out",
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"audio_pll1_out", "sys_pll1_800m", "sys_pll2_1000m",
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"sys_pll3_out", "clk_ext4", };
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static const char * const imx8mn_sai2_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out",
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"video_pll1_out", "sys_pll1_133m", "osc_hdmi",
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"clk_ext3", "clk_ext4", };
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static const char * const imx8mn_sai3_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out",
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"video_pll1_out", "sys_pll1_133m", "osc_hdmi",
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"clk_ext3", "clk_ext4", };
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static const char * const imx8mn_sai5_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out",
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"video_pll1_out", "sys_pll1_133m", "osc_hdmi",
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"clk_ext2", "clk_ext3", };
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static const char * const imx8mn_sai6_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out",
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"video_pll1_out", "sys_pll1_133m", "osc_hdmi",
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"clk_ext3", "clk_ext4", };
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static const char * const imx8mn_sai7_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out",
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"video_pll1_out", "sys_pll1_133m", "osc_hdmi",
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"clk_ext3", "clk_ext4", };
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static const char * const imx8mn_spdif1_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out",
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"video_pll1_out", "sys_pll1_133m", "osc_hdmi",
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"clk_ext2", "clk_ext3", };
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static const char * const imx8mn_enet_ref_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll2_50m",
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"sys_pll2_100m", "sys_pll1_160m", "audio_pll1_out",
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"video_pll1_out", "clk_ext4", };
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static const char * const imx8mn_enet_timer_sels[] = {"osc_24m", "sys_pll2_100m", "audio_pll1_out",
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"clk_ext1", "clk_ext2", "clk_ext3",
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"clk_ext4", "video_pll1_out", };
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static const char * const imx8mn_enet_phy_sels[] = {"osc_24m", "sys_pll2_50m", "sys_pll2_125m",
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"sys_pll2_200m", "sys_pll2_500m", "video_pll1_out",
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"audio_pll2_out", };
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static const char * const imx8mn_nand_sels[] = {"osc_24m", "sys_pll2_500m", "audio_pll1_out",
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"sys_pll1_400m", "audio_pll2_out", "sys_pll3_out",
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"sys_pll2_250m", "video_pll1_out", };
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static const char * const imx8mn_qspi_sels[] = {"osc_24m", "sys1_pll_400m", "sys_pll1_800m",
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"sys2_pll_500m", "audio_pll2_out", "sys1_pll_266m",
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"sys3_pll2_out", "sys1_pll_100m", };
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static const char * const imx8mn_usdhc1_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m",
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"sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m",
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"audio_pll2_out", "sys_pll1_100m", };
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static const char * const imx8mn_usdhc2_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m",
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"sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m",
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"audio_pll2_out", "sys_pll1_100m", };
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static const char * const imx8mn_i2c1_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
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"sys_pll3_out", "audio_pll1_out", "video_pll1_out",
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"audio_pll2_out", "sys_pll1_133m", };
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static const char * const imx8mn_i2c2_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
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"sys_pll3_out", "audio_pll1_out", "video_pll1_out",
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"audio_pll2_out", "sys_pll1_133m", };
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static const char * const imx8mn_i2c3_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
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"sys_pll3_out", "audio_pll1_out", "video_pll1_out",
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"audio_pll2_out", "sys_pll1_133m", };
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static const char * const imx8mn_i2c4_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
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"sys_pll3_out", "audio_pll1_out", "video_pll1_out",
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"audio_pll2_out", "sys_pll1_133m", };
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static const char * const imx8mn_uart1_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m",
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"sys_pll2_100m", "sys_pll3_out", "clk_ext2",
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"clk_ext4", "audio_pll2_out", };
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static const char * const imx8mn_uart2_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m",
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"sys_pll2_100m", "sys_pll3_out", "clk_ext2",
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"clk_ext3", "audio_pll2_out", };
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static const char * const imx8mn_uart3_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m",
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"sys_pll2_100m", "sys_pll3_out", "clk_ext2",
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"clk_ext4", "audio_pll2_out", };
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static const char * const imx8mn_uart4_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m",
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"sys_pll2_100m", "sys_pll3_out", "clk_ext2",
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"clk_ext3", "audio_pll2_out", };
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static const char * const imx8mn_usb_core_sels[] = {"osc_24m", "sys_pll1_100m", "sys_pll1_40m",
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"sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
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"clk_ext3", "audio_pll2_out", };
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static const char * const imx8mn_usb_phy_sels[] = {"osc_24m", "sys_pll1_100m", "sys_pll1_40m",
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"sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
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"clk_ext3", "audio_pll2_out", };
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static const char * const imx8mn_ecspi1_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
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"sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
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"sys_pll2_250m", "audio_pll2_out", };
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static const char * const imx8mn_ecspi2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
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"sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
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"sys_pll2_250m", "audio_pll2_out", };
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static const char * const imx8mn_pwm1_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
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"sys_pll1_40m", "sys_pll3_out", "clk_ext1",
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"sys_pll1_80m", "video_pll1_out", };
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static const char * const imx8mn_pwm2_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
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"sys_pll1_40m", "sys_pll3_out", "clk_ext1",
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"sys_pll1_80m", "video_pll1_out", };
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static const char * const imx8mn_pwm3_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
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"sys_pll1_40m", "sys3_pll2_out", "clk_ext2",
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"sys_pll1_80m", "video_pll1_out", };
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static const char * const imx8mn_pwm4_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
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"sys_pll1_40m", "sys_pll3_out", "clk_ext2",
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"sys_pll1_80m", "video_pll1_out", };
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static const char * const imx8mn_wdog_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_160m",
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"vpu_pll_out", "sys_pll2_125m", "sys_pll3_out",
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"sys_pll1_80m", "sys_pll2_166m", };
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static const char * const imx8mn_wrclk_sels[] = {"osc_24m", "sys_pll1_40m", "vpu_pll_out",
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"sys_pll3_out", "sys_pll2_200m", "sys_pll1_266m",
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"sys_pll2_500m", "sys_pll1_100m", };
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+
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static const char * const imx8mn_dsi_core_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll2_250m",
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"sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out",
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"audio_pll2_out", "video_pll1_out", };
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+
310
+
static const char * const imx8mn_dsi_phy_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll2_100m",
311
+
"sys_pll1_800m", "sys_pll2_1000m", "clk_ext2",
312
+
"audio_pll2_out", "video_pll1_out", };
313
+
314
+
static const char * const imx8mn_dsi_dbi_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll2_100m",
315
+
"sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out",
316
+
"audio_pll2_out", "video_pll1_out", };
317
+
318
+
static const char * const imx8mn_usdhc3_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m",
319
+
"sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m",
320
+
"audio_pll2_clk", "sys_pll1_100m", };
321
+
322
+
static const char * const imx8mn_camera_pixel_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll2_250m",
323
+
"sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out",
324
+
"audio_pll2_out", "video_pll1_out", };
325
+
326
+
static const char * const imx8mn_csi1_phy_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll2_100m",
327
+
"sys_pll1_800m", "sys_pll2_1000m", "clk_ext2",
328
+
"audio_pll2_out", "video_pll1_out", };
329
+
330
+
static const char * const imx8mn_csi2_phy_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll2_100m",
331
+
"sys_pll1_800m", "sys_pll2_1000m", "clk_ext2",
332
+
"audio_pll2_out", "video_pll1_out", };
333
+
334
+
static const char * const imx8mn_csi2_esc_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_80m",
335
+
"sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out",
336
+
"clk_ext3", "audio_pll2_out", };
337
+
338
+
static const char * const imx8mn_ecspi3_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
339
+
"sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
340
+
"sys_pll2_250m", "audio_pll2_out", };
341
+
342
+
static const char * const imx8mn_pdm_sels[] = {"osc_24m", "sys_pll2_100m", "audio_pll1_out",
343
+
"sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out",
344
+
"clk_ext3", "audio_pll2_out", };
345
+
346
+
static const char * const imx8mn_dram_core_sels[] = {"dram_pll_out", "dram_alt_root", };
347
+
348
+
static const char * const imx8mn_clko1_sels[] = {"osc_24m", "sys_pll1_800m", "osc_27m",
349
+
"sys_pll1_200m", "audio_pll2_clk", "vpu_pll",
350
+
"sys_pll1_80m", };
351
+
static const char * const imx8mn_clko2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_400m",
352
+
"sys_pll2_166m", "sys_pll3_out", "audio_pll1_out",
353
+
"video_pll1_out", "osc_32k", };
354
+
355
+
static struct clk *clks[IMX8MN_CLK_END];
356
+
static struct clk_onecell_data clk_data;
357
+
358
+
static int imx8mn_clocks_probe(struct platform_device *pdev)
359
+
{
360
+
struct device *dev = &pdev->dev;
361
+
struct device_node *np = dev->of_node;
362
+
void __iomem *base;
363
+
int ret;
364
+
365
+
clks[IMX8MN_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
366
+
clks[IMX8MN_CLK_24M] = of_clk_get_by_name(np, "osc_24m");
367
+
clks[IMX8MN_CLK_32K] = of_clk_get_by_name(np, "osc_32k");
368
+
clks[IMX8MN_CLK_EXT1] = of_clk_get_by_name(np, "clk_ext1");
369
+
clks[IMX8MN_CLK_EXT2] = of_clk_get_by_name(np, "clk_ext2");
370
+
clks[IMX8MN_CLK_EXT3] = of_clk_get_by_name(np, "clk_ext3");
371
+
clks[IMX8MN_CLK_EXT4] = of_clk_get_by_name(np, "clk_ext4");
372
+
373
+
np = of_find_compatible_node(NULL, NULL, "fsl,imx8mn-anatop");
374
+
base = of_iomap(np, 0);
375
+
if (WARN_ON(!base)) {
376
+
ret = -ENOMEM;
377
+
goto unregister_clks;
378
+
}
379
+
380
+
clks[IMX8MN_AUDIO_PLL1_REF_SEL] = imx_clk_mux("audio_pll1_ref_sel", base + 0x0, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
381
+
clks[IMX8MN_AUDIO_PLL2_REF_SEL] = imx_clk_mux("audio_pll2_ref_sel", base + 0x14, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
382
+
clks[IMX8MN_VIDEO_PLL1_REF_SEL] = imx_clk_mux("video_pll1_ref_sel", base + 0x28, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
383
+
clks[IMX8MN_DRAM_PLL_REF_SEL] = imx_clk_mux("dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
384
+
clks[IMX8MN_GPU_PLL_REF_SEL] = imx_clk_mux("gpu_pll_ref_sel", base + 0x64, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
385
+
clks[IMX8MN_VPU_PLL_REF_SEL] = imx_clk_mux("vpu_pll_ref_sel", base + 0x74, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
386
+
clks[IMX8MN_ARM_PLL_REF_SEL] = imx_clk_mux("arm_pll_ref_sel", base + 0x84, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
387
+
clks[IMX8MN_SYS_PLL1_REF_SEL] = imx_clk_mux("sys_pll1_ref_sel", base + 0x94, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
388
+
clks[IMX8MN_SYS_PLL2_REF_SEL] = imx_clk_mux("sys_pll2_ref_sel", base + 0x104, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
389
+
clks[IMX8MN_SYS_PLL3_REF_SEL] = imx_clk_mux("sys_pll3_ref_sel", base + 0x114, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
390
+
391
+
clks[IMX8MN_AUDIO_PLL1] = imx_clk_pll14xx("audio_pll1", "audio_pll1_ref_sel", base, &imx8mn_audio_pll);
392
+
clks[IMX8MN_AUDIO_PLL2] = imx_clk_pll14xx("audio_pll2", "audio_pll2_ref_sel", base + 0x14, &imx8mn_audio_pll);
393
+
clks[IMX8MN_VIDEO_PLL1] = imx_clk_pll14xx("video_pll1", "video_pll1_ref_sel", base + 0x28, &imx8mn_video_pll);
394
+
clks[IMX8MN_DRAM_PLL] = imx_clk_pll14xx("dram_pll", "dram_pll_ref_sel", base + 0x50, &imx8mn_dram_pll);
395
+
clks[IMX8MN_GPU_PLL] = imx_clk_pll14xx("gpu_pll", "gpu_pll_ref_sel", base + 0x64, &imx8mn_gpu_pll);
396
+
clks[IMX8MN_VPU_PLL] = imx_clk_pll14xx("vpu_pll", "vpu_pll_ref_sel", base + 0x74, &imx8mn_vpu_pll);
397
+
clks[IMX8MN_ARM_PLL] = imx_clk_pll14xx("arm_pll", "arm_pll_ref_sel", base + 0x84, &imx8mn_arm_pll);
398
+
clks[IMX8MN_SYS_PLL1] = imx_clk_pll14xx("sys_pll1", "sys_pll1_ref_sel", base + 0x94, &imx8mn_sys_pll);
399
+
clks[IMX8MN_SYS_PLL2] = imx_clk_pll14xx("sys_pll2", "sys_pll2_ref_sel", base + 0x104, &imx8mn_sys_pll);
400
+
clks[IMX8MN_SYS_PLL3] = imx_clk_pll14xx("sys_pll3", "sys_pll3_ref_sel", base + 0x114, &imx8mn_sys_pll);
401
+
402
+
/* PLL bypass out */
403
+
clks[IMX8MN_AUDIO_PLL1_BYPASS] = imx_clk_mux_flags("audio_pll1_bypass", base, 4, 1, audio_pll1_bypass_sels, ARRAY_SIZE(audio_pll1_bypass_sels), CLK_SET_RATE_PARENT);
404
+
clks[IMX8MN_AUDIO_PLL2_BYPASS] = imx_clk_mux_flags("audio_pll2_bypass", base + 0x14, 4, 1, audio_pll2_bypass_sels, ARRAY_SIZE(audio_pll2_bypass_sels), CLK_SET_RATE_PARENT);
405
+
clks[IMX8MN_VIDEO_PLL1_BYPASS] = imx_clk_mux_flags("video_pll1_bypass", base + 0x28, 4, 1, video_pll1_bypass_sels, ARRAY_SIZE(video_pll1_bypass_sels), CLK_SET_RATE_PARENT);
406
+
clks[IMX8MN_DRAM_PLL_BYPASS] = imx_clk_mux_flags("dram_pll_bypass", base + 0x50, 4, 1, dram_pll_bypass_sels, ARRAY_SIZE(dram_pll_bypass_sels), CLK_SET_RATE_PARENT);
407
+
clks[IMX8MN_GPU_PLL_BYPASS] = imx_clk_mux_flags("gpu_pll_bypass", base + 0x64, 4, 1, gpu_pll_bypass_sels, ARRAY_SIZE(gpu_pll_bypass_sels), CLK_SET_RATE_PARENT);
408
+
clks[IMX8MN_VPU_PLL_BYPASS] = imx_clk_mux_flags("vpu_pll_bypass", base + 0x74, 4, 1, vpu_pll_bypass_sels, ARRAY_SIZE(vpu_pll_bypass_sels), CLK_SET_RATE_PARENT);
409
+
clks[IMX8MN_ARM_PLL_BYPASS] = imx_clk_mux_flags("arm_pll_bypass", base + 0x84, 4, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels), CLK_SET_RATE_PARENT);
410
+
clks[IMX8MN_SYS_PLL1_BYPASS] = imx_clk_mux_flags("sys_pll1_bypass", base + 0x94, 4, 1, sys_pll1_bypass_sels, ARRAY_SIZE(sys_pll1_bypass_sels), CLK_SET_RATE_PARENT);
411
+
clks[IMX8MN_SYS_PLL2_BYPASS] = imx_clk_mux_flags("sys_pll2_bypass", base + 0x104, 4, 1, sys_pll2_bypass_sels, ARRAY_SIZE(sys_pll2_bypass_sels), CLK_SET_RATE_PARENT);
412
+
clks[IMX8MN_SYS_PLL3_BYPASS] = imx_clk_mux_flags("sys_pll3_bypass", base + 0x114, 4, 1, sys_pll3_bypass_sels, ARRAY_SIZE(sys_pll3_bypass_sels), CLK_SET_RATE_PARENT);
413
+
414
+
/* unbypass all the plls */
415
+
clk_set_parent(clks[IMX8MN_AUDIO_PLL1_BYPASS], clks[IMX8MN_AUDIO_PLL1]);
416
+
clk_set_parent(clks[IMX8MN_AUDIO_PLL2_BYPASS], clks[IMX8MN_AUDIO_PLL2]);
417
+
clk_set_parent(clks[IMX8MN_VIDEO_PLL1_BYPASS], clks[IMX8MN_VIDEO_PLL1]);
418
+
clk_set_parent(clks[IMX8MN_DRAM_PLL_BYPASS], clks[IMX8MN_DRAM_PLL]);
419
+
clk_set_parent(clks[IMX8MN_GPU_PLL_BYPASS], clks[IMX8MN_GPU_PLL]);
420
+
clk_set_parent(clks[IMX8MN_VPU_PLL_BYPASS], clks[IMX8MN_VPU_PLL]);
421
+
clk_set_parent(clks[IMX8MN_ARM_PLL_BYPASS], clks[IMX8MN_ARM_PLL]);
422
+
clk_set_parent(clks[IMX8MN_SYS_PLL1_BYPASS], clks[IMX8MN_SYS_PLL1]);
423
+
clk_set_parent(clks[IMX8MN_SYS_PLL2_BYPASS], clks[IMX8MN_SYS_PLL2]);
424
+
clk_set_parent(clks[IMX8MN_SYS_PLL3_BYPASS], clks[IMX8MN_SYS_PLL3]);
425
+
426
+
/* PLL out gate */
427
+
clks[IMX8MN_AUDIO_PLL1_OUT] = imx_clk_gate("audio_pll1_out", "audio_pll1_bypass", base, 13);
428
+
clks[IMX8MN_AUDIO_PLL2_OUT] = imx_clk_gate("audio_pll2_out", "audio_pll2_bypass", base + 0x14, 13);
429
+
clks[IMX8MN_VIDEO_PLL1_OUT] = imx_clk_gate("video_pll1_out", "video_pll1_bypass", base + 0x28, 13);
430
+
clks[IMX8MN_DRAM_PLL_OUT] = imx_clk_gate("dram_pll_out", "dram_pll_bypass", base + 0x50, 13);
431
+
clks[IMX8MN_GPU_PLL_OUT] = imx_clk_gate("gpu_pll_out", "gpu_pll_bypass", base + 0x64, 13);
432
+
clks[IMX8MN_VPU_PLL_OUT] = imx_clk_gate("vpu_pll_out", "vpu_pll_bypass", base + 0x74, 13);
433
+
clks[IMX8MN_ARM_PLL_OUT] = imx_clk_gate("arm_pll_out", "arm_pll_bypass", base + 0x84, 13);
434
+
clks[IMX8MN_SYS_PLL1_OUT] = imx_clk_gate("sys_pll1_out", "sys_pll1_bypass", base + 0x94, 13);
435
+
clks[IMX8MN_SYS_PLL2_OUT] = imx_clk_gate("sys_pll2_out", "sys_pll2_bypass", base + 0x104, 13);
436
+
clks[IMX8MN_SYS_PLL3_OUT] = imx_clk_gate("sys_pll3_out", "sys_pll3_bypass", base + 0x114, 13);
437
+
438
+
/* SYS PLL fixed output */
439
+
clks[IMX8MN_SYS_PLL1_40M] = imx_clk_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20);
440
+
clks[IMX8MN_SYS_PLL1_80M] = imx_clk_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10);
441
+
clks[IMX8MN_SYS_PLL1_100M] = imx_clk_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8);
442
+
clks[IMX8MN_SYS_PLL1_133M] = imx_clk_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6);
443
+
clks[IMX8MN_SYS_PLL1_160M] = imx_clk_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5);
444
+
clks[IMX8MN_SYS_PLL1_200M] = imx_clk_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4);
445
+
clks[IMX8MN_SYS_PLL1_266M] = imx_clk_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3);
446
+
clks[IMX8MN_SYS_PLL1_400M] = imx_clk_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2);
447
+
clks[IMX8MN_SYS_PLL1_800M] = imx_clk_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1);
448
+
449
+
clks[IMX8MN_SYS_PLL2_50M] = imx_clk_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20);
450
+
clks[IMX8MN_SYS_PLL2_100M] = imx_clk_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10);
451
+
clks[IMX8MN_SYS_PLL2_125M] = imx_clk_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8);
452
+
clks[IMX8MN_SYS_PLL2_166M] = imx_clk_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6);
453
+
clks[IMX8MN_SYS_PLL2_200M] = imx_clk_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5);
454
+
clks[IMX8MN_SYS_PLL2_250M] = imx_clk_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4);
455
+
clks[IMX8MN_SYS_PLL2_333M] = imx_clk_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3);
456
+
clks[IMX8MN_SYS_PLL2_500M] = imx_clk_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2);
457
+
clks[IMX8MN_SYS_PLL2_1000M] = imx_clk_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1);
458
+
459
+
np = dev->of_node;
460
+
base = devm_platform_ioremap_resource(pdev, 0);
461
+
if (WARN_ON(IS_ERR(base))) {
462
+
ret = PTR_ERR(base);
463
+
goto unregister_clks;
464
+
}
465
+
466
+
/* CORE */
467
+
clks[IMX8MN_CLK_A53_SRC] = imx_clk_mux2("arm_a53_src", base + 0x8000, 24, 3, imx8mn_a53_sels, ARRAY_SIZE(imx8mn_a53_sels));
468
+
clks[IMX8MN_CLK_GPU_CORE_SRC] = imx_clk_mux2("gpu_core_src", base + 0x8180, 24, 3, imx8mn_gpu_core_sels, ARRAY_SIZE(imx8mn_gpu_core_sels));
469
+
clks[IMX8MN_CLK_GPU_SHADER_SRC] = imx_clk_mux2("gpu_shader_src", base + 0x8200, 24, 3, imx8mn_gpu_shader_sels, ARRAY_SIZE(imx8mn_gpu_shader_sels));
470
+
clks[IMX8MN_CLK_A53_CG] = imx_clk_gate3("arm_a53_cg", "arm_a53_src", base + 0x8000, 28);
471
+
clks[IMX8MN_CLK_GPU_CORE_CG] = imx_clk_gate3("gpu_core_cg", "gpu_core_src", base + 0x8180, 28);
472
+
clks[IMX8MN_CLK_GPU_SHADER_CG] = imx_clk_gate3("gpu_shader_cg", "gpu_shader_src", base + 0x8200, 28);
473
+
474
+
clks[IMX8MN_CLK_A53_DIV] = imx_clk_divider2("arm_a53_div", "arm_a53_cg", base + 0x8000, 0, 3);
475
+
clks[IMX8MN_CLK_GPU_CORE_DIV] = imx_clk_divider2("gpu_core_div", "gpu_core_cg", base + 0x8180, 0, 3);
476
+
clks[IMX8MN_CLK_GPU_SHADER_DIV] = imx_clk_divider2("gpu_shader_div", "gpu_shader_cg", base + 0x8200, 0, 3);
477
+
478
+
/* BUS */
479
+
clks[IMX8MN_CLK_MAIN_AXI] = imx8m_clk_composite_critical("main_axi", imx8mn_main_axi_sels, base + 0x8800);
480
+
clks[IMX8MN_CLK_ENET_AXI] = imx8m_clk_composite("enet_axi", imx8mn_enet_axi_sels, base + 0x8880);
481
+
clks[IMX8MN_CLK_NAND_USDHC_BUS] = imx8m_clk_composite("nand_usdhc_bus", imx8mn_nand_usdhc_sels, base + 0x8900);
482
+
clks[IMX8MN_CLK_DISP_AXI] = imx8m_clk_composite("disp_axi", imx8mn_disp_axi_sels, base + 0x8a00);
483
+
clks[IMX8MN_CLK_DISP_APB] = imx8m_clk_composite("disp_apb", imx8mn_disp_apb_sels, base + 0x8a80);
484
+
clks[IMX8MN_CLK_USB_BUS] = imx8m_clk_composite("usb_bus", imx8mn_usb_bus_sels, base + 0x8b80);
485
+
clks[IMX8MN_CLK_GPU_AXI] = imx8m_clk_composite("gpu_axi", imx8mn_gpu_axi_sels, base + 0x8c00);
486
+
clks[IMX8MN_CLK_GPU_AHB] = imx8m_clk_composite("gpu_ahb", imx8mn_gpu_ahb_sels, base + 0x8c80);
487
+
clks[IMX8MN_CLK_NOC] = imx8m_clk_composite_critical("noc", imx8mn_noc_sels, base + 0x8d00);
488
+
489
+
clks[IMX8MN_CLK_AHB] = imx8m_clk_composite_critical("ahb", imx8mn_ahb_sels, base + 0x9000);
490
+
clks[IMX8MN_CLK_AUDIO_AHB] = imx8m_clk_composite("audio_ahb", imx8mn_audio_ahb_sels, base + 0x9100);
491
+
clks[IMX8MN_CLK_IPG_ROOT] = imx_clk_divider2("ipg_root", "ahb", base + 0x9080, 0, 1);
492
+
clks[IMX8MN_CLK_IPG_AUDIO_ROOT] = imx_clk_divider2("ipg_audio_root", "audio_ahb", base + 0x9180, 0, 1);
493
+
clks[IMX8MN_CLK_DRAM_CORE] = imx_clk_mux2_flags("dram_core_clk", base + 0x9800, 24, 1, imx8mn_dram_core_sels, ARRAY_SIZE(imx8mn_dram_core_sels), CLK_IS_CRITICAL);
494
+
clks[IMX8MN_CLK_DRAM_ALT] = imx8m_clk_composite("dram_alt", imx8mn_dram_alt_sels, base + 0xa000);
495
+
clks[IMX8MN_CLK_DRAM_APB] = imx8m_clk_composite_critical("dram_apb", imx8mn_dram_apb_sels, base + 0xa080);
496
+
clks[IMX8MN_CLK_DISP_PIXEL] = imx8m_clk_composite("disp_pixel", imx8mn_disp_pixel_sels, base + 0xa500);
497
+
clks[IMX8MN_CLK_SAI2] = imx8m_clk_composite("sai2", imx8mn_sai2_sels, base + 0xa600);
498
+
clks[IMX8MN_CLK_SAI3] = imx8m_clk_composite("sai3", imx8mn_sai3_sels, base + 0xa680);
499
+
clks[IMX8MN_CLK_SAI5] = imx8m_clk_composite("sai5", imx8mn_sai5_sels, base + 0xa780);
500
+
clks[IMX8MN_CLK_SAI6] = imx8m_clk_composite("sai6", imx8mn_sai6_sels, base + 0xa800);
501
+
clks[IMX8MN_CLK_SPDIF1] = imx8m_clk_composite("spdif1", imx8mn_spdif1_sels, base + 0xa880);
502
+
clks[IMX8MN_CLK_ENET_REF] = imx8m_clk_composite("enet_ref", imx8mn_enet_ref_sels, base + 0xa980);
503
+
clks[IMX8MN_CLK_ENET_TIMER] = imx8m_clk_composite("enet_timer", imx8mn_enet_timer_sels, base + 0xaa00);
504
+
clks[IMX8MN_CLK_ENET_PHY_REF] = imx8m_clk_composite("enet_phy", imx8mn_enet_phy_sels, base + 0xaa80);
505
+
clks[IMX8MN_CLK_NAND] = imx8m_clk_composite("nand", imx8mn_nand_sels, base + 0xab00);
506
+
clks[IMX8MN_CLK_QSPI] = imx8m_clk_composite("qspi", imx8mn_qspi_sels, base + 0xab80);
507
+
clks[IMX8MN_CLK_USDHC1] = imx8m_clk_composite("usdhc1", imx8mn_usdhc1_sels, base + 0xac00);
508
+
clks[IMX8MN_CLK_USDHC2] = imx8m_clk_composite("usdhc2", imx8mn_usdhc2_sels, base + 0xac80);
509
+
clks[IMX8MN_CLK_I2C1] = imx8m_clk_composite("i2c1", imx8mn_i2c1_sels, base + 0xad00);
510
+
clks[IMX8MN_CLK_I2C2] = imx8m_clk_composite("i2c2", imx8mn_i2c2_sels, base + 0xad80);
511
+
clks[IMX8MN_CLK_I2C3] = imx8m_clk_composite("i2c3", imx8mn_i2c3_sels, base + 0xae00);
512
+
clks[IMX8MN_CLK_I2C4] = imx8m_clk_composite("i2c4", imx8mn_i2c4_sels, base + 0xae80);
513
+
clks[IMX8MN_CLK_UART1] = imx8m_clk_composite("uart1", imx8mn_uart1_sels, base + 0xaf00);
514
+
clks[IMX8MN_CLK_UART2] = imx8m_clk_composite("uart2", imx8mn_uart2_sels, base + 0xaf80);
515
+
clks[IMX8MN_CLK_UART3] = imx8m_clk_composite("uart3", imx8mn_uart3_sels, base + 0xb000);
516
+
clks[IMX8MN_CLK_UART4] = imx8m_clk_composite("uart4", imx8mn_uart4_sels, base + 0xb080);
517
+
clks[IMX8MN_CLK_USB_CORE_REF] = imx8m_clk_composite("usb_core_ref", imx8mn_usb_core_sels, base + 0xb100);
518
+
clks[IMX8MN_CLK_USB_PHY_REF] = imx8m_clk_composite("usb_phy_ref", imx8mn_usb_phy_sels, base + 0xb180);
519
+
clks[IMX8MN_CLK_ECSPI1] = imx8m_clk_composite("ecspi1", imx8mn_ecspi1_sels, base + 0xb280);
520
+
clks[IMX8MN_CLK_ECSPI2] = imx8m_clk_composite("ecspi2", imx8mn_ecspi2_sels, base + 0xb300);
521
+
clks[IMX8MN_CLK_PWM1] = imx8m_clk_composite("pwm1", imx8mn_pwm1_sels, base + 0xb380);
522
+
clks[IMX8MN_CLK_PWM2] = imx8m_clk_composite("pwm2", imx8mn_pwm2_sels, base + 0xb400);
523
+
clks[IMX8MN_CLK_PWM3] = imx8m_clk_composite("pwm3", imx8mn_pwm3_sels, base + 0xb480);
524
+
clks[IMX8MN_CLK_PWM4] = imx8m_clk_composite("pwm4", imx8mn_pwm4_sels, base + 0xb500);
525
+
clks[IMX8MN_CLK_WDOG] = imx8m_clk_composite("wdog", imx8mn_wdog_sels, base + 0xb900);
526
+
clks[IMX8MN_CLK_WRCLK] = imx8m_clk_composite("wrclk", imx8mn_wrclk_sels, base + 0xb980);
527
+
clks[IMX8MN_CLK_CLKO1] = imx8m_clk_composite("clko1", imx8mn_clko1_sels, base + 0xba00);
528
+
clks[IMX8MN_CLK_CLKO2] = imx8m_clk_composite("clko2", imx8mn_clko2_sels, base + 0xba80);
529
+
clks[IMX8MN_CLK_DSI_CORE] = imx8m_clk_composite("dsi_core", imx8mn_dsi_core_sels, base + 0xbb00);
530
+
clks[IMX8MN_CLK_DSI_PHY_REF] = imx8m_clk_composite("dsi_phy_ref", imx8mn_dsi_phy_sels, base + 0xbb80);
531
+
clks[IMX8MN_CLK_DSI_DBI] = imx8m_clk_composite("dsi_dbi", imx8mn_dsi_dbi_sels, base + 0xbc00);
532
+
clks[IMX8MN_CLK_USDHC3] = imx8m_clk_composite("usdhc3", imx8mn_usdhc3_sels, base + 0xbc80);
533
+
clks[IMX8MN_CLK_CAMERA_PIXEL] = imx8m_clk_composite("camera_pixel", imx8mn_camera_pixel_sels, base + 0xbd00);
534
+
clks[IMX8MN_CLK_CSI1_PHY_REF] = imx8m_clk_composite("csi1_phy_ref", imx8mn_csi1_phy_sels, base + 0xbd80);
535
+
clks[IMX8MN_CLK_CSI2_PHY_REF] = imx8m_clk_composite("csi2_phy_ref", imx8mn_csi2_phy_sels, base + 0xbf00);
536
+
clks[IMX8MN_CLK_CSI2_ESC] = imx8m_clk_composite("csi2_esc", imx8mn_csi2_esc_sels, base + 0xbf80);
537
+
clks[IMX8MN_CLK_ECSPI3] = imx8m_clk_composite("ecspi3", imx8mn_ecspi3_sels, base + 0xc180);
538
+
clks[IMX8MN_CLK_PDM] = imx8m_clk_composite("pdm", imx8mn_pdm_sels, base + 0xc200);
539
+
clks[IMX8MN_CLK_SAI7] = imx8m_clk_composite("sai7", imx8mn_sai7_sels, base + 0xc300);
540
+
541
+
clks[IMX8MN_CLK_ECSPI1_ROOT] = imx_clk_gate4("ecspi1_root_clk", "ecspi1", base + 0x4070, 0);
542
+
clks[IMX8MN_CLK_ECSPI2_ROOT] = imx_clk_gate4("ecspi2_root_clk", "ecspi2", base + 0x4080, 0);
543
+
clks[IMX8MN_CLK_ECSPI3_ROOT] = imx_clk_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, 0);
544
+
clks[IMX8MN_CLK_ENET1_ROOT] = imx_clk_gate4("enet1_root_clk", "enet_axi", base + 0x40a0, 0);
545
+
clks[IMX8MN_CLK_GPIO1_ROOT] = imx_clk_gate4("gpio1_root_clk", "ipg_root", base + 0x40b0, 0);
546
+
clks[IMX8MN_CLK_GPIO2_ROOT] = imx_clk_gate4("gpio2_root_clk", "ipg_root", base + 0x40c0, 0);
547
+
clks[IMX8MN_CLK_GPIO3_ROOT] = imx_clk_gate4("gpio3_root_clk", "ipg_root", base + 0x40d0, 0);
548
+
clks[IMX8MN_CLK_GPIO4_ROOT] = imx_clk_gate4("gpio4_root_clk", "ipg_root", base + 0x40e0, 0);
549
+
clks[IMX8MN_CLK_GPIO5_ROOT] = imx_clk_gate4("gpio5_root_clk", "ipg_root", base + 0x40f0, 0);
550
+
clks[IMX8MN_CLK_I2C1_ROOT] = imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0);
551
+
clks[IMX8MN_CLK_I2C2_ROOT] = imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0);
552
+
clks[IMX8MN_CLK_I2C3_ROOT] = imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0);
553
+
clks[IMX8MN_CLK_I2C4_ROOT] = imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0);
554
+
clks[IMX8MN_CLK_MU_ROOT] = imx_clk_gate4("mu_root_clk", "ipg_root", base + 0x4210, 0);
555
+
clks[IMX8MN_CLK_OCOTP_ROOT] = imx_clk_gate4("ocotp_root_clk", "ipg_root", base + 0x4220, 0);
556
+
clks[IMX8MN_CLK_PWM1_ROOT] = imx_clk_gate4("pwm1_root_clk", "pwm1", base + 0x4280, 0);
557
+
clks[IMX8MN_CLK_PWM2_ROOT] = imx_clk_gate4("pwm2_root_clk", "pwm2", base + 0x4290, 0);
558
+
clks[IMX8MN_CLK_PWM3_ROOT] = imx_clk_gate4("pwm3_root_clk", "pwm3", base + 0x42a0, 0);
559
+
clks[IMX8MN_CLK_PWM4_ROOT] = imx_clk_gate4("pwm4_root_clk", "pwm4", base + 0x42b0, 0);
560
+
clks[IMX8MN_CLK_QSPI_ROOT] = imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0);
561
+
clks[IMX8MN_CLK_NAND_ROOT] = imx_clk_gate2_shared2("nand_root_clk", "nand", base + 0x4300, 0, &share_count_nand);
562
+
clks[IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK] = imx_clk_gate2_shared2("nand_usdhc_rawnand_clk", "nand_usdhc_bus", base + 0x4300, 0, &share_count_nand);
563
+
clks[IMX8MN_CLK_SAI2_ROOT] = imx_clk_gate2_shared2("sai2_root_clk", "sai2", base + 0x4340, 0, &share_count_sai2);
564
+
clks[IMX8MN_CLK_SAI2_IPG] = imx_clk_gate2_shared2("sai2_ipg_clk", "ipg_audio_root", base + 0x4340, 0, &share_count_sai2);
565
+
clks[IMX8MN_CLK_SAI3_ROOT] = imx_clk_gate2_shared2("sai3_root_clk", "sai3", base + 0x4350, 0, &share_count_sai3);
566
+
clks[IMX8MN_CLK_SAI3_IPG] = imx_clk_gate2_shared2("sai3_ipg_clk", "ipg_audio_root", base + 0x4350, 0, &share_count_sai3);
567
+
clks[IMX8MN_CLK_SAI5_ROOT] = imx_clk_gate2_shared2("sai5_root_clk", "sai5", base + 0x4370, 0, &share_count_sai5);
568
+
clks[IMX8MN_CLK_SAI5_IPG] = imx_clk_gate2_shared2("sai5_ipg_clk", "ipg_audio_root", base + 0x4370, 0, &share_count_sai5);
569
+
clks[IMX8MN_CLK_SAI6_ROOT] = imx_clk_gate2_shared2("sai6_root_clk", "sai6", base + 0x4380, 0, &share_count_sai6);
570
+
clks[IMX8MN_CLK_SAI6_IPG] = imx_clk_gate2_shared2("sai6_ipg_clk", "ipg_audio_root", base + 0x4380, 0, &share_count_sai6);
571
+
clks[IMX8MN_CLK_UART1_ROOT] = imx_clk_gate4("uart1_root_clk", "uart1", base + 0x4490, 0);
572
+
clks[IMX8MN_CLK_UART2_ROOT] = imx_clk_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0);
573
+
clks[IMX8MN_CLK_UART3_ROOT] = imx_clk_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0);
574
+
clks[IMX8MN_CLK_UART4_ROOT] = imx_clk_gate4("uart4_root_clk", "uart4", base + 0x44c0, 0);
575
+
clks[IMX8MN_CLK_USB1_CTRL_ROOT] = imx_clk_gate4("usb1_ctrl_root_clk", "usb_core_ref", base + 0x44d0, 0);
576
+
clks[IMX8MN_CLK_GPU_CORE_ROOT] = imx_clk_gate4("gpu_core_root_clk", "gpu_core_div", base + 0x44f0, 0);
577
+
clks[IMX8MN_CLK_USDHC1_ROOT] = imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0);
578
+
clks[IMX8MN_CLK_USDHC2_ROOT] = imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0);
579
+
clks[IMX8MN_CLK_WDOG1_ROOT] = imx_clk_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0);
580
+
clks[IMX8MN_CLK_WDOG2_ROOT] = imx_clk_gate4("wdog2_root_clk", "wdog", base + 0x4540, 0);
581
+
clks[IMX8MN_CLK_WDOG3_ROOT] = imx_clk_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0);
582
+
clks[IMX8MN_CLK_GPU_BUS_ROOT] = imx_clk_gate4("gpu_root_clk", "gpu_axi", base + 0x4570, 0);
583
+
clks[IMX8MN_CLK_ASRC_ROOT] = imx_clk_gate4("asrc_root_clk", "audio_ahb", base + 0x4580, 0);
584
+
clks[IMX8MN_CLK_PDM_ROOT] = imx_clk_gate2_shared2("pdm_root_clk", "pdm", base + 0x45b0, 0, &share_count_pdm);
585
+
clks[IMX8MN_CLK_PDM_IPG] = imx_clk_gate2_shared2("pdm_ipg_clk", "ipg_audio_root", base + 0x45b0, 0, &share_count_pdm);
586
+
clks[IMX8MN_CLK_DISP_AXI_ROOT] = imx_clk_gate2_shared2("disp_axi_root_clk", "disp_axi", base + 0x45d0, 0, &share_count_disp);
587
+
clks[IMX8MN_CLK_DISP_APB_ROOT] = imx_clk_gate2_shared2("disp_apb_root_clk", "disp_apb", base + 0x45d0, 0, &share_count_disp);
588
+
clks[IMX8MN_CLK_CAMERA_PIXEL_ROOT] = imx_clk_gate2_shared2("camera_pixel_clk", "camera_pixel", base + 0x45d0, 0, &share_count_disp);
589
+
clks[IMX8MN_CLK_DISP_PIXEL_ROOT] = imx_clk_gate2_shared2("disp_pixel_clk", "disp_pixel", base + 0x45d0, 0, &share_count_disp);
590
+
clks[IMX8MN_CLK_USDHC3_ROOT] = imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0);
591
+
clks[IMX8MN_CLK_TMU_ROOT] = imx_clk_gate4("tmu_root_clk", "ipg_root", base + 0x4620, 0);
592
+
clks[IMX8MN_CLK_SDMA1_ROOT] = imx_clk_gate4("sdma1_clk", "ipg_root", base + 0x43a0, 0);
593
+
clks[IMX8MN_CLK_SDMA2_ROOT] = imx_clk_gate4("sdma2_clk", "ipg_audio_root", base + 0x43b0, 0);
594
+
clks[IMX8MN_CLK_SDMA3_ROOT] = imx_clk_gate4("sdma3_clk", "ipg_audio_root", base + 0x45f0, 0);
595
+
clks[IMX8MN_CLK_SAI7_ROOT] = imx_clk_gate2_shared2("sai7_root_clk", "sai7", base + 0x4650, 0, &share_count_sai7);
596
+
597
+
clks[IMX8MN_CLK_DRAM_ALT_ROOT] = imx_clk_fixed_factor("dram_alt_root", "dram_alt", 1, 4);
598
+
599
+
clks[IMX8MN_CLK_ARM] = imx_clk_cpu("arm", "arm_a53_div",
600
+
clks[IMX8MN_CLK_A53_DIV],
601
+
clks[IMX8MN_CLK_A53_SRC],
602
+
clks[IMX8MN_ARM_PLL_OUT],
603
+
clks[IMX8MN_CLK_24M]);
604
+
605
+
imx_check_clocks(clks, ARRAY_SIZE(clks));
606
+
607
+
clk_data.clks = clks;
608
+
clk_data.clk_num = ARRAY_SIZE(clks);
609
+
ret = of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
610
+
if (ret < 0) {
611
+
dev_err(dev, "failed to register clks for i.MX8MN\n");
612
+
goto unregister_clks;
613
+
}
614
+
615
+
return 0;
616
+
617
+
unregister_clks:
618
+
imx_unregister_clocks(clks, ARRAY_SIZE(clks));
619
+
620
+
return ret;
621
+
}
622
+
623
+
static const struct of_device_id imx8mn_clk_of_match[] = {
624
+
{ .compatible = "fsl,imx8mn-ccm" },
625
+
{ /* Sentinel */ },
626
+
};
627
+
MODULE_DEVICE_TABLE(of, imx8mn_clk_of_match);
628
+
629
+
static struct platform_driver imx8mn_clk_driver = {
630
+
.probe = imx8mn_clocks_probe,
631
+
.driver = {
632
+
.name = "imx8mn-ccm",
633
+
.of_match_table = of_match_ptr(imx8mn_clk_of_match),
634
+
},
635
+
};
636
+
module_platform_driver(imx8mn_clk_driver);