MIPS: MIPSxx SC: Avoid destructive invalidation on partial L2 cachelines.

This extends commit a8ca8b64e3fdfec17679cba0ca5ce6e3ffed092d to cover
MIPSxx-style board cache code.

Signed-off-by: Kevin Cernekee <[e-mail]>
Signed-off-by: Ralf Baechle <[e-mail]>

arch/mips/mm/sc-mips.c

···
  */
 static void mips_sc_inv(unsigned long addr, unsigned long size)
 {
+	unsigned long lsize = cpu_scache_line_size();
+	unsigned long almask = ~(lsize - 1);
+
+	cache_op(Hit_Writeback_Inv_SD, addr & almask);
+	cache_op(Hit_Writeback_Inv_SD, (addr + size - 1) & almask);
 	blast_inv_scache_range(addr, addr + size);
 }