tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

Merge branch 'pci/resource' into next

* pci/resource:
PCI: Allocate 64-bit BARs above 4G when possible
PCI: Enforce bus address limits in resource allocation
PCI: Split out bridge window override of minimum allocation address
agp/ati: Use PCI_COMMAND instead of hard-coded 4
agp/intel: Use CPU physical address, not bus address, for ioremap()
agp/intel: Use pci_bus_address() to get GTTADR bus address
agp/intel: Use pci_bus_address() to get MMADR bus address
agp/intel: Support 64-bit GMADR
agp/intel: Rename gtt_bus_addr to gtt_phys_addr
drm/i915: Rename gtt_bus_addr to gtt_phys_addr
agp: Use pci_resource_start() to get CPU physical address for BAR
agp: Support 64-bit APBASE
PCI: Add pci_bus_address() to get bus address of a BAR
PCI: Convert pcibios_resource_to_bus() to take a pci_bus, not a pci_dev
PCI: Change pci_bus_region addresses to dma_addr_t

Bjorn Helgaas 96702be5 04f982be

+244 -195
+2 -2
arch/alpha/kernel/pci-sysfs.c
··· 83 83 if (iomem_is_exclusive(res->start)) 84 84 return -EINVAL; 85 85 86 - pcibios_resource_to_bus(pdev, &bar, res); 86 + pcibios_resource_to_bus(pdev->bus, &bar, res); 87 87 vma->vm_pgoff += bar.start >> (PAGE_SHIFT - (sparse ? 5 : 0)); 88 88 mmap_type = res->flags & IORESOURCE_MEM ? pci_mmap_mem : pci_mmap_io; 89 89 ··· 139 139 long dense_offset; 140 140 unsigned long sparse_size; 141 141 142 - pcibios_resource_to_bus(pdev, &bar, &pdev->resource[num]); 142 + pcibios_resource_to_bus(pdev->bus, &bar, &pdev->resource[num]); 143 143 144 144 /* All core logic chips have 4G sparse address space, except 145 145 CIA which has 16G (see xxx_SPARSE_MEM and xxx_DENSE_MEM
+2 -2
arch/powerpc/kernel/pci-common.c
··· 835 835 * at 0 as unset as well, except if PCI_PROBE_ONLY is also set 836 836 * since in that case, we don't want to re-assign anything 837 837 */ 838 - pcibios_resource_to_bus(dev, &reg, res); 838 + pcibios_resource_to_bus(dev->bus, &reg, res); 839 839 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC) || 840 840 (reg.start == 0 && !pci_has_flag(PCI_PROBE_ONLY))) { 841 841 /* Only print message if not re-assigning */ ··· 886 886 887 887 /* Job is a bit different between memory and IO */ 888 888 if (res->flags & IORESOURCE_MEM) { 889 - pcibios_resource_to_bus(dev, &region, res); 889 + pcibios_resource_to_bus(dev->bus, &region, res); 890 890 891 891 /* If the BAR is non-0 then it's probably been initialized */ 892 892 if (region.start != 0)
+2 -2
arch/powerpc/kernel/pci_of_scan.c
··· 111 111 res->name = pci_name(dev); 112 112 region.start = base; 113 113 region.end = base + size - 1; 114 - pcibios_bus_to_resource(dev, res, &region); 114 + pcibios_bus_to_resource(dev->bus, res, &region); 115 115 } 116 116 } 117 117 ··· 280 280 res->flags = flags; 281 281 region.start = of_read_number(&ranges[1], 2); 282 282 region.end = region.start + size - 1; 283 - pcibios_bus_to_resource(dev, res, &region); 283 + pcibios_bus_to_resource(dev->bus, res, &region); 284 284 } 285 285 sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus), 286 286 bus->number);
+3 -3
arch/sparc/kernel/pci.c
··· 392 392 res->flags = IORESOURCE_IO; 393 393 region.start = (first << 21); 394 394 region.end = (last << 21) + ((1 << 21) - 1); 395 - pcibios_bus_to_resource(dev, res, &region); 395 + pcibios_bus_to_resource(dev->bus, res, &region); 396 396 397 397 pci_read_config_byte(dev, APB_MEM_ADDRESS_MAP, &map); 398 398 apb_calc_first_last(map, &first, &last); ··· 400 400 res->flags = IORESOURCE_MEM; 401 401 region.start = (first << 29); 402 402 region.end = (last << 29) + ((1 << 29) - 1); 403 - pcibios_bus_to_resource(dev, res, &region); 403 + pcibios_bus_to_resource(dev->bus, res, &region); 404 404 } 405 405 406 406 static void pci_of_scan_bus(struct pci_pbm_info *pbm, ··· 491 491 res->flags = flags; 492 492 region.start = GET_64BIT(ranges, 1); 493 493 region.end = region.start + size - 1; 494 - pcibios_bus_to_resource(dev, res, &region); 494 + pcibios_bus_to_resource(dev->bus, res, &region); 495 495 } 496 496 after_ranges: 497 497 sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
-1
arch/x86/include/asm/pci.h
··· 125 125 126 126 /* generic pci stuff */ 127 127 #include <asm-generic/pci.h> 128 - #define PCIBIOS_MAX_MEM_32 0xffffffff 129 128 130 129 #ifdef CONFIG_NUMA 131 130 /* Returns the node based on pci bus */
+1
drivers/char/agp/agp.h
··· 239 239 240 240 /* Chipset independent registers (from AGP Spec) */ 241 241 #define AGP_APBASE 0x10 242 + #define AGP_APERTURE_BAR 0 242 243 243 244 #define AGPSTAT 0x4 244 245 #define AGPCMD 0x8
+2 -2
drivers/char/agp/ali-agp.c
··· 85 85 pci_write_config_dword(agp_bridge->dev, ALI_TLBCTRL, ((temp & 0xffffff00) | 0x00000010)); 86 86 87 87 /* address to map to */ 88 - pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 89 - agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 88 + agp_bridge->gart_bus_addr = pci_bus_address(agp_bridge->dev, 89 + AGP_APERTURE_BAR); 90 90 91 91 #if 0 92 92 if (agp_bridge->type == ALI_M1541) {
+5 -7
drivers/char/agp/amd-k7-agp.c
··· 11 11 #include <linux/slab.h> 12 12 #include "agp.h" 13 13 14 - #define AMD_MMBASE 0x14 14 + #define AMD_MMBASE_BAR 1 15 15 #define AMD_APSIZE 0xac 16 16 #define AMD_MODECNTL 0xb0 17 17 #define AMD_MODECNTL2 0xb2 ··· 126 126 unsigned long __iomem *cur_gatt; 127 127 unsigned long addr; 128 128 int retval; 129 - u32 temp; 130 129 int i; 131 130 132 131 value = A_SIZE_LVL2(agp_bridge->current_size); ··· 148 149 * used to program the agp master not the cpu 149 150 */ 150 151 151 - pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 152 - addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 152 + addr = pci_bus_address(agp_bridge->dev, AGP_APERTURE_BAR); 153 153 agp_bridge->gart_bus_addr = addr; 154 154 155 155 /* Calculate the agp offset */ ··· 205 207 static int amd_irongate_configure(void) 206 208 { 207 209 struct aper_size_info_lvl2 *current_size; 210 + phys_addr_t reg; 208 211 u32 temp; 209 212 u16 enable_reg; 210 213 ··· 213 214 214 215 if (!amd_irongate_private.registers) { 215 216 /* Get the memory mapped registers */ 216 - pci_read_config_dword(agp_bridge->dev, AMD_MMBASE, &temp); 217 - temp = (temp & PCI_BASE_ADDRESS_MEM_MASK); 218 - amd_irongate_private.registers = (volatile u8 __iomem *) ioremap(temp, 4096); 217 + reg = pci_resource_start(agp_bridge->dev, AMD_MMBASE_BAR); 218 + amd_irongate_private.registers = (volatile u8 __iomem *) ioremap(reg, 4096); 219 219 if (!amd_irongate_private.registers) 220 220 return -ENOMEM; 221 221 }
+1 -4
drivers/char/agp/amd64-agp.c
··· 269 269 */ 270 270 static int fix_northbridge(struct pci_dev *nb, struct pci_dev *agp, u16 cap) 271 271 { 272 - u32 aper_low, aper_hi; 273 272 u64 aper, nb_aper; 274 273 int order = 0; 275 274 u32 nb_order, nb_base; ··· 294 295 apsize |= 0xf00; 295 296 order = 7 - hweight16(apsize); 296 297 297 - pci_read_config_dword(agp, 0x10, &aper_low); 298 - pci_read_config_dword(agp, 0x14, &aper_hi); 299 - aper = (aper_low & ~((1<<22)-1)) | ((u64)aper_hi << 32); 298 + aper = pci_bus_address(agp, AGP_APERTURE_BAR); 300 299 301 300 /* 302 301 * On some sick chips APSIZE is 0. This means it wants 4G
+10 -11
drivers/char/agp/ati-agp.c
··· 12 12 #include <asm/agp.h> 13 13 #include "agp.h" 14 14 15 - #define ATI_GART_MMBASE_ADDR 0x14 15 + #define ATI_GART_MMBASE_BAR 1 16 16 #define ATI_RS100_APSIZE 0xac 17 17 #define ATI_RS100_IG_AGPMODE 0xb0 18 18 #define ATI_RS300_APSIZE 0xf8 ··· 196 196 197 197 static int ati_configure(void) 198 198 { 199 + phys_addr_t reg; 199 200 u32 temp; 200 201 201 202 /* Get the memory mapped registers */ 202 - pci_read_config_dword(agp_bridge->dev, ATI_GART_MMBASE_ADDR, &temp); 203 - temp = (temp & 0xfffff000); 204 - ati_generic_private.registers = (volatile u8 __iomem *) ioremap(temp, 4096); 203 + reg = pci_resource_start(agp_bridge->dev, ATI_GART_MMBASE_BAR); 204 + ati_generic_private.registers = (volatile u8 __iomem *) ioremap(reg, 4096); 205 205 206 206 if (!ati_generic_private.registers) 207 207 return -ENOMEM; ··· 211 211 else 212 212 pci_write_config_dword(agp_bridge->dev, ATI_RS300_IG_AGPMODE, 0x20000); 213 213 214 - /* address to map too */ 214 + /* address to map to */ 215 215 /* 216 - pci_read_config_dword(agp_bridge.dev, AGP_APBASE, &temp); 217 - agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 216 + agp_bridge.gart_bus_addr = pci_bus_address(agp_bridge.dev, 217 + AGP_APERTURE_BAR); 218 218 printk(KERN_INFO PFX "IGP320 gart_bus_addr: %x\n", agp_bridge.gart_bus_addr); 219 219 */ 220 220 writel(0x60000, ati_generic_private.registers+ATI_GART_FEATURE_ID); 221 221 readl(ati_generic_private.registers+ATI_GART_FEATURE_ID); /* PCI Posting.*/ 222 222 223 223 /* SIGNALED_SYSTEM_ERROR @ NB_STATUS */ 224 - pci_read_config_dword(agp_bridge->dev, 4, &temp); 225 - pci_write_config_dword(agp_bridge->dev, 4, temp | (1<<14)); 224 + pci_read_config_dword(agp_bridge->dev, PCI_COMMAND, &temp); 225 + pci_write_config_dword(agp_bridge->dev, PCI_COMMAND, temp | (1<<14)); 226 226 227 227 /* Write out the address of the gatt table */ 228 228 writel(agp_bridge->gatt_bus_addr, ati_generic_private.registers+ATI_GART_BASE); ··· 385 385 * This is a bus address even on the alpha, b/c its 386 386 * used to program the agp master not the cpu 387 387 */ 388 - pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 389 - addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 388 + addr = pci_bus_address(agp_bridge->dev, AGP_APERTURE_BAR); 390 389 agp_bridge->gart_bus_addr = addr; 391 390 392 391 /* Calculate the agp offset */
+2 -3
drivers/char/agp/efficeon-agp.c
··· 128 128 129 129 static int efficeon_configure(void) 130 130 { 131 - u32 temp; 132 131 u16 temp2; 133 132 struct aper_size_info_lvl2 *current_size; 134 133 ··· 140 141 current_size->size_value); 141 142 142 143 /* address to map to */ 143 - pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 144 - agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 144 + agp_bridge->gart_bus_addr = pci_bus_address(agp_bridge->dev, 145 + AGP_APERTURE_BAR); 145 146 146 147 /* agpctrl */ 147 148 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
+2 -2
drivers/char/agp/generic.c
··· 1396 1396 1397 1397 current_size = A_SIZE_16(agp_bridge->current_size); 1398 1398 1399 - pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1400 - agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1399 + agp_bridge->gart_bus_addr = pci_bus_address(agp_bridge->dev, 1400 + AGP_APERTURE_BAR); 1401 1401 1402 1402 /* set aperture size */ 1403 1403 pci_write_config_word(agp_bridge->dev, agp_bridge->capndx+AGPAPSIZE, current_size->size_value);
+20 -28
drivers/char/agp/intel-agp.c
··· 118 118 119 119 static int intel_configure(void) 120 120 { 121 - u32 temp; 122 121 u16 temp2; 123 122 struct aper_size_info_16 *current_size; 124 123 ··· 127 128 pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 128 129 129 130 /* address to map to */ 130 - pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 131 - agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 131 + agp_bridge->gart_bus_addr = pci_bus_address(agp_bridge->dev, 132 + AGP_APERTURE_BAR); 132 133 133 134 /* attbase - aperture base */ 134 135 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); ··· 147 148 148 149 static int intel_815_configure(void) 149 150 { 150 - u32 temp, addr; 151 + u32 addr; 151 152 u8 temp2; 152 153 struct aper_size_info_8 *current_size; 153 154 ··· 166 167 current_size->size_value); 167 168 168 169 /* address to map to */ 169 - pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 170 - agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 170 + agp_bridge->gart_bus_addr = pci_bus_address(agp_bridge->dev, 171 + AGP_APERTURE_BAR); 171 172 172 173 pci_read_config_dword(agp_bridge->dev, INTEL_ATTBASE, &addr); 173 174 addr &= INTEL_815_ATTBASE_MASK; ··· 207 208 208 209 static int intel_820_configure(void) 209 210 { 210 - u32 temp; 211 211 u8 temp2; 212 212 struct aper_size_info_8 *current_size; 213 213 ··· 216 218 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 217 219 218 220 /* address to map to */ 219 - pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 220 - agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 221 + agp_bridge->gart_bus_addr = pci_bus_address(agp_bridge->dev, 222 + AGP_APERTURE_BAR); 221 223 222 224 /* attbase - aperture base */ 223 225 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); ··· 237 239 238 240 static int intel_840_configure(void) 239 241 { 240 - u32 temp; 241 242 u16 temp2; 242 243 struct aper_size_info_8 *current_size; 243 244 ··· 246 249 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 247 250 248 251 /* address to map to */ 249 - pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 250 - agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 252 + agp_bridge->gart_bus_addr = pci_bus_address(agp_bridge->dev, 253 + AGP_APERTURE_BAR); 251 254 252 255 /* attbase - aperture base */ 253 256 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); ··· 265 268 266 269 static int intel_845_configure(void) 267 270 { 268 - u32 temp; 269 271 u8 temp2; 270 272 struct aper_size_info_8 *current_size; 271 273 ··· 278 282 agp_bridge->apbase_config); 279 283 } else { 280 284 /* address to map to */ 281 - pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 282 - agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 283 - agp_bridge->apbase_config = temp; 285 + agp_bridge->gart_bus_addr = pci_bus_address(agp_bridge->dev, 286 + AGP_APERTURE_BAR); 287 + agp_bridge->apbase_config = agp_bridge->gart_bus_addr; 284 288 } 285 289 286 290 /* attbase - aperture base */ ··· 299 303 300 304 static int intel_850_configure(void) 301 305 { 302 - u32 temp; 303 306 u16 temp2; 304 307 struct aper_size_info_8 *current_size; 305 308 ··· 308 313 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 309 314 310 315 /* address to map to */ 311 - pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 312 - agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 316 + agp_bridge->gart_bus_addr = pci_bus_address(agp_bridge->dev, 317 + AGP_APERTURE_BAR); 313 318 314 319 /* attbase - aperture base */ 315 320 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); ··· 327 332 328 333 static int intel_860_configure(void) 329 334 { 330 - u32 temp; 331 335 u16 temp2; 332 336 struct aper_size_info_8 *current_size; 333 337 ··· 336 342 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 337 343 338 344 /* address to map to */ 339 - pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 340 - agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 345 + agp_bridge->gart_bus_addr = pci_bus_address(agp_bridge->dev, 346 + AGP_APERTURE_BAR); 341 347 342 348 /* attbase - aperture base */ 343 349 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); ··· 355 361 356 362 static int intel_830mp_configure(void) 357 363 { 358 - u32 temp; 359 364 u16 temp2; 360 365 struct aper_size_info_8 *current_size; 361 366 ··· 364 371 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 365 372 366 373 /* address to map to */ 367 - pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 368 - agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 374 + agp_bridge->gart_bus_addr = pci_bus_address(agp_bridge->dev, 375 + AGP_APERTURE_BAR); 369 376 370 377 /* attbase - aperture base */ 371 378 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); ··· 383 390 384 391 static int intel_7505_configure(void) 385 392 { 386 - u32 temp; 387 393 u16 temp2; 388 394 struct aper_size_info_8 *current_size; 389 395 ··· 392 400 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 393 401 394 402 /* address to map to */ 395 - pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 396 - agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 403 + agp_bridge->gart_bus_addr = pci_bus_address(agp_bridge->dev, 404 + AGP_APERTURE_BAR); 397 405 398 406 /* attbase - aperture base */ 399 407 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
+5 -5
drivers/char/agp/intel-agp.h
··· 55 55 #define INTEL_I860_ERRSTS 0xc8 56 56 57 57 /* Intel i810 registers */ 58 - #define I810_GMADDR 0x10 59 - #define I810_MMADDR 0x14 58 + #define I810_GMADR_BAR 0 59 + #define I810_MMADR_BAR 1 60 60 #define I810_PTE_BASE 0x10000 61 61 #define I810_PTE_MAIN_UNCACHED 0x00000000 62 62 #define I810_PTE_LOCAL 0x00000002 ··· 113 113 #define INTEL_I850_ERRSTS 0xc8 114 114 115 115 /* intel 915G registers */ 116 - #define I915_GMADDR 0x18 117 - #define I915_MMADDR 0x10 118 - #define I915_PTEADDR 0x1C 116 + #define I915_GMADR_BAR 2 117 + #define I915_MMADR_BAR 0 118 + #define I915_PTE_BAR 3 119 119 #define I915_GMCH_GMS_STOLEN_48M (0x6 << 4) 120 120 #define I915_GMCH_GMS_STOLEN_64M (0x7 << 4) 121 121 #define G33_GMCH_GMS_STOLEN_128M (0x8 << 4)
+19 -28
drivers/char/agp/intel-gtt.c
··· 64 64 struct pci_dev *pcidev; /* device one */ 65 65 struct pci_dev *bridge_dev; 66 66 u8 __iomem *registers; 67 - phys_addr_t gtt_bus_addr; 67 + phys_addr_t gtt_phys_addr; 68 68 u32 PGETBL_save; 69 69 u32 __iomem *gtt; /* I915G */ 70 70 bool clear_fake_agp; /* on first access via agp, fill with scratch */ ··· 172 172 #define I810_GTT_ORDER 4 173 173 static int i810_setup(void) 174 174 { 175 - u32 reg_addr; 175 + phys_addr_t reg_addr; 176 176 char *gtt_table; 177 177 178 178 /* i81x does not preallocate the gtt. It's always 64kb in size. */ ··· 181 181 return -ENOMEM; 182 182 intel_private.i81x_gtt_table = gtt_table; 183 183 184 - pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &reg_addr); 185 - reg_addr &= 0xfff80000; 184 + reg_addr = pci_resource_start(intel_private.pcidev, I810_MMADR_BAR); 186 185 187 186 intel_private.registers = ioremap(reg_addr, KB(64)); 188 187 if (!intel_private.registers) ··· 190 191 writel(virt_to_phys(gtt_table) | I810_PGETBL_ENABLED, 191 192 intel_private.registers+I810_PGETBL_CTL); 192 193 193 - intel_private.gtt_bus_addr = reg_addr + I810_PTE_BASE; 194 + intel_private.gtt_phys_addr = reg_addr + I810_PTE_BASE; 194 195 195 196 if ((readl(intel_private.registers+I810_DRAM_CTL) 196 197 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) { ··· 607 608 608 609 static int intel_gtt_init(void) 609 610 { 610 - u32 gma_addr; 611 611 u32 gtt_map_size; 612 - int ret; 612 + int ret, bar; 613 613 614 614 ret = intel_private.driver->setup(); 615 615 if (ret != 0) ··· 634 636 635 637 intel_private.gtt = NULL; 636 638 if (intel_gtt_can_wc()) 637 - intel_private.gtt = ioremap_wc(intel_private.gtt_bus_addr, 639 + intel_private.gtt = ioremap_wc(intel_private.gtt_phys_addr, 638 640 gtt_map_size); 639 641 if (intel_private.gtt == NULL) 640 - intel_private.gtt = ioremap(intel_private.gtt_bus_addr, 642 + intel_private.gtt = ioremap(intel_private.gtt_phys_addr, 641 643 gtt_map_size); 642 644 if (intel_private.gtt == NULL) { 643 645 intel_private.driver->cleanup(); ··· 658 660 } 659 661 660 662 if (INTEL_GTT_GEN <= 2) 661 - pci_read_config_dword(intel_private.pcidev, I810_GMADDR, 662 - &gma_addr); 663 + bar = I810_GMADR_BAR; 663 664 else 664 - pci_read_config_dword(intel_private.pcidev, I915_GMADDR, 665 - &gma_addr); 665 + bar = I915_GMADR_BAR; 666 666 667 - intel_private.gma_bus_addr = (gma_addr & PCI_BASE_ADDRESS_MEM_MASK); 668 - 667 + intel_private.gma_bus_addr = pci_bus_address(intel_private.pcidev, bar); 669 668 return 0; 670 669 } 671 670 ··· 782 787 783 788 static int i830_setup(void) 784 789 { 785 - u32 reg_addr; 790 + phys_addr_t reg_addr; 786 791 787 - pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &reg_addr); 788 - reg_addr &= 0xfff80000; 792 + reg_addr = pci_resource_start(intel_private.pcidev, I810_MMADR_BAR); 789 793 790 794 intel_private.registers = ioremap(reg_addr, KB(64)); 791 795 if (!intel_private.registers) 792 796 return -ENOMEM; 793 797 794 - intel_private.gtt_bus_addr = reg_addr + I810_PTE_BASE; 798 + intel_private.gtt_phys_addr = reg_addr + I810_PTE_BASE; 795 799 796 800 return 0; 797 801 } ··· 1102 1108 1103 1109 static int i9xx_setup(void) 1104 1110 { 1105 - u32 reg_addr, gtt_addr; 1111 + phys_addr_t reg_addr; 1106 1112 int size = KB(512); 1107 1113 1108 - pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &reg_addr); 1109 - 1110 - reg_addr &= 0xfff80000; 1114 + reg_addr = pci_resource_start(intel_private.pcidev, I915_MMADR_BAR); 1111 1115 1112 1116 intel_private.registers = ioremap(reg_addr, size); 1113 1117 if (!intel_private.registers) ··· 1113 1121 1114 1122 switch (INTEL_GTT_GEN) { 1115 1123 case 3: 1116 - pci_read_config_dword(intel_private.pcidev, 1117 - I915_PTEADDR, &gtt_addr); 1118 - intel_private.gtt_bus_addr = gtt_addr; 1124 + intel_private.gtt_phys_addr = 1125 + pci_resource_start(intel_private.pcidev, I915_PTE_BAR); 1119 1126 break; 1120 1127 case 5: 1121 - intel_private.gtt_bus_addr = reg_addr + MB(2); 1128 + intel_private.gtt_phys_addr = reg_addr + MB(2); 1122 1129 break; 1123 1130 default: 1124 - intel_private.gtt_bus_addr = reg_addr + KB(512); 1131 + intel_private.gtt_phys_addr = reg_addr + KB(512); 1125 1132 break; 1126 1133 } 1127 1134
+5 -4
drivers/char/agp/nvidia-agp.c
··· 106 106 { 107 107 int i, rc, num_dirs; 108 108 u32 apbase, aplimit; 109 + phys_addr_t apbase_phys; 109 110 struct aper_size_info_8 *current_size; 110 111 u32 temp; 111 112 ··· 116 115 pci_write_config_byte(agp_bridge->dev, NVIDIA_0_APSIZE, 117 116 current_size->size_value); 118 117 119 - /* address to map to */ 120 - pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &apbase); 121 - apbase &= PCI_BASE_ADDRESS_MEM_MASK; 118 + /* address to map to */ 119 + apbase = pci_bus_address(agp_bridge->dev, AGP_APERTURE_BAR); 122 120 agp_bridge->gart_bus_addr = apbase; 123 121 aplimit = apbase + (current_size->size * 1024 * 1024) - 1; 124 122 pci_write_config_dword(nvidia_private.dev_2, NVIDIA_2_APBASE, apbase); ··· 153 153 pci_write_config_dword(agp_bridge->dev, NVIDIA_0_APSIZE, temp | 0x100); 154 154 155 155 /* map aperture */ 156 + apbase_phys = pci_resource_start(agp_bridge->dev, AGP_APERTURE_BAR); 156 157 nvidia_private.aperture = 157 - (volatile u32 __iomem *) ioremap(apbase, 33 * PAGE_SIZE); 158 + (volatile u32 __iomem *) ioremap(apbase_phys, 33 * PAGE_SIZE); 158 159 159 160 if (!nvidia_private.aperture) 160 161 return -ENOMEM;
+2 -3
drivers/char/agp/sis-agp.c
··· 50 50 51 51 static int sis_configure(void) 52 52 { 53 - u32 temp; 54 53 struct aper_size_info_8 *current_size; 55 54 56 55 current_size = A_SIZE_8(agp_bridge->current_size); 57 56 pci_write_config_byte(agp_bridge->dev, SIS_TLBCNTRL, 0x05); 58 - pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 59 - agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 57 + agp_bridge->gart_bus_addr = pci_bus_address(agp_bridge->dev, 58 + AGP_APERTURE_BAR); 60 59 pci_write_config_dword(agp_bridge->dev, SIS_ATTBASE, 61 60 agp_bridge->gatt_bus_addr); 62 61 pci_write_config_byte(agp_bridge->dev, SIS_APSIZE,
+6 -7
drivers/char/agp/via-agp.c
··· 43 43 44 44 static int via_configure(void) 45 45 { 46 - u32 temp; 47 46 struct aper_size_info_8 *current_size; 48 47 49 48 current_size = A_SIZE_8(agp_bridge->current_size); 50 49 /* aperture size */ 51 50 pci_write_config_byte(agp_bridge->dev, VIA_APSIZE, 52 51 current_size->size_value); 53 - /* address to map too */ 54 - pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 55 - agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 52 + /* address to map to */ 53 + agp_bridge->gart_bus_addr = pci_bus_address(agp_bridge->dev, 54 + AGP_APERTURE_BAR); 56 55 57 56 /* GART control register */ 58 57 pci_write_config_dword(agp_bridge->dev, VIA_GARTCTRL, 0x0000000f); ··· 131 132 132 133 current_size = A_SIZE_16(agp_bridge->current_size); 133 134 134 - /* address to map too */ 135 - pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 136 - agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 135 + /* address to map to */ 136 + agp_bridge->gart_bus_addr = pci_bus_address(agp_bridge->dev, 137 + AGP_APERTURE_BAR); 137 138 138 139 /* attbase - aperture GATT base */ 139 140 pci_write_config_dword(agp_bridge->dev, VIA_AGP3_ATTBASE,
+3 -3
drivers/gpu/drm/i915/i915_gem_gtt.c
··· 1260 1260 size_t gtt_size) 1261 1261 { 1262 1262 struct drm_i915_private *dev_priv = dev->dev_private; 1263 - phys_addr_t gtt_bus_addr; 1263 + phys_addr_t gtt_phys_addr; 1264 1264 int ret; 1265 1265 1266 1266 /* For Modern GENs the PTEs and register space are split in the BAR */ 1267 - gtt_bus_addr = pci_resource_start(dev->pdev, 0) + 1267 + gtt_phys_addr = pci_resource_start(dev->pdev, 0) + 1268 1268 (pci_resource_len(dev->pdev, 0) / 2); 1269 1269 1270 - dev_priv->gtt.gsm = ioremap_wc(gtt_bus_addr, gtt_size); 1270 + dev_priv->gtt.gsm = ioremap_wc(gtt_phys_addr, gtt_size); 1271 1271 if (!dev_priv->gtt.gsm) { 1272 1272 DRM_ERROR("Failed to map the gtt page table\n"); 1273 1273 return -ENOMEM;
+102 -30
drivers/pci/bus.c
··· 98 98 } 99 99 } 100 100 101 - /** 102 - * pci_bus_alloc_resource - allocate a resource from a parent bus 103 - * @bus: PCI bus 104 - * @res: resource to allocate 105 - * @size: size of resource to allocate 106 - * @align: alignment of resource to allocate 107 - * @min: minimum /proc/iomem address to allocate 108 - * @type_mask: IORESOURCE_* type flags 109 - * @alignf: resource alignment function 110 - * @alignf_data: data argument for resource alignment function 111 - * 112 - * Given the PCI bus a device resides on, the size, minimum address, 113 - * alignment and type, try to find an acceptable resource allocation 114 - * for a specific device resource. 101 + static struct pci_bus_region pci_32_bit = {0, 0xffffffffULL}; 102 + #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 103 + static struct pci_bus_region pci_64_bit = {0, 104 + (dma_addr_t) 0xffffffffffffffffULL}; 105 + static struct pci_bus_region pci_high = {(dma_addr_t) 0x100000000ULL, 106 + (dma_addr_t) 0xffffffffffffffffULL}; 107 + #endif 108 + 109 + /* 110 + * @res contains CPU addresses. Clip it so the corresponding bus addresses 111 + * on @bus are entirely within @region. This is used to control the bus 112 + * addresses of resources we allocate, e.g., we may need a resource that 113 + * can be mapped by a 32-bit BAR. 115 114 */ 116 - int 117 - pci_bus_alloc_resource(struct pci_bus *bus, struct resource *res, 115 + static void pci_clip_resource_to_region(struct pci_bus *bus, 116 + struct resource *res, 117 + struct pci_bus_region *region) 118 + { 119 + struct pci_bus_region r; 120 + 121 + pcibios_resource_to_bus(bus, &r, res); 122 + if (r.start < region->start) 123 + r.start = region->start; 124 + if (r.end > region->end) 125 + r.end = region->end; 126 + 127 + if (r.end < r.start) 128 + res->end = res->start - 1; 129 + else 130 + pcibios_bus_to_resource(bus, res, &r); 131 + } 132 + 133 + static int pci_bus_alloc_from_region(struct pci_bus *bus, struct resource *res, 118 134 resource_size_t size, resource_size_t align, 119 135 resource_size_t min, unsigned int type_mask, 120 136 resource_size_t (*alignf)(void *, 121 137 const struct resource *, 122 138 resource_size_t, 123 139 resource_size_t), 124 - void *alignf_data) 140 + void *alignf_data, 141 + struct pci_bus_region *region) 125 142 { 126 - int i, ret = -ENOMEM; 127 - struct resource *r; 128 - resource_size_t max = -1; 143 + int i, ret; 144 + struct resource *r, avail; 145 + resource_size_t max; 129 146 130 147 type_mask |= IORESOURCE_IO | IORESOURCE_MEM; 131 - 132 - /* don't allocate too high if the pref mem doesn't support 64bit*/ 133 - if (!(res->flags & IORESOURCE_MEM_64)) 134 - max = PCIBIOS_MAX_MEM_32; 135 148 136 149 pci_bus_for_each_resource(bus, r, i) { 137 150 if (!r) ··· 160 147 !(res->flags & IORESOURCE_PREFETCH)) 161 148 continue; 162 149 150 + avail = *r; 151 + pci_clip_resource_to_region(bus, &avail, region); 152 + if (!resource_size(&avail)) 153 + continue; 154 + 155 + /* 156 + * "min" is typically PCIBIOS_MIN_IO or PCIBIOS_MIN_MEM to 157 + * protect badly documented motherboard resources, but if 158 + * this is an already-configured bridge window, its start 159 + * overrides "min". 160 + */ 161 + if (avail.start) 162 + min = avail.start; 163 + 164 + max = avail.end; 165 + 163 166 /* Ok, try it out.. */ 164 - ret = allocate_resource(r, res, size, 165 - r->start ? : min, 166 - max, align, 167 - alignf, alignf_data); 167 + ret = allocate_resource(r, res, size, min, max, 168 + align, alignf, alignf_data); 168 169 if (ret == 0) 169 - break; 170 + return 0; 170 171 } 171 - return ret; 172 + return -ENOMEM; 173 + } 174 + 175 + /** 176 + * pci_bus_alloc_resource - allocate a resource from a parent bus 177 + * @bus: PCI bus 178 + * @res: resource to allocate 179 + * @size: size of resource to allocate 180 + * @align: alignment of resource to allocate 181 + * @min: minimum /proc/iomem address to allocate 182 + * @type_mask: IORESOURCE_* type flags 183 + * @alignf: resource alignment function 184 + * @alignf_data: data argument for resource alignment function 185 + * 186 + * Given the PCI bus a device resides on, the size, minimum address, 187 + * alignment and type, try to find an acceptable resource allocation 188 + * for a specific device resource. 189 + */ 190 + int pci_bus_alloc_resource(struct pci_bus *bus, struct resource *res, 191 + resource_size_t size, resource_size_t align, 192 + resource_size_t min, unsigned int type_mask, 193 + resource_size_t (*alignf)(void *, 194 + const struct resource *, 195 + resource_size_t, 196 + resource_size_t), 197 + void *alignf_data) 198 + { 199 + #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 200 + int rc; 201 + 202 + if (res->flags & IORESOURCE_MEM_64) { 203 + rc = pci_bus_alloc_from_region(bus, res, size, align, min, 204 + type_mask, alignf, alignf_data, 205 + &pci_high); 206 + if (rc == 0) 207 + return 0; 208 + 209 + return pci_bus_alloc_from_region(bus, res, size, align, min, 210 + type_mask, alignf, alignf_data, 211 + &pci_64_bit); 212 + } 213 + #endif 214 + 215 + return pci_bus_alloc_from_region(bus, res, size, align, min, 216 + type_mask, alignf, alignf_data, 217 + &pci_32_bit); 172 218 } 173 219 174 220 void __weak pcibios_resource_survey_bus(struct pci_bus *bus) { }
+8 -11
drivers/pci/host-bridge.c
··· 9 9 10 10 #include "pci.h" 11 11 12 - static struct pci_bus *find_pci_root_bus(struct pci_dev *dev) 12 + static struct pci_bus *find_pci_root_bus(struct pci_bus *bus) 13 13 { 14 - struct pci_bus *bus; 15 - 16 - bus = dev->bus; 17 14 while (bus->parent) 18 15 bus = bus->parent; 19 16 20 17 return bus; 21 18 } 22 19 23 - static struct pci_host_bridge *find_pci_host_bridge(struct pci_dev *dev) 20 + static struct pci_host_bridge *find_pci_host_bridge(struct pci_bus *bus) 24 21 { 25 - struct pci_bus *bus = find_pci_root_bus(dev); 22 + struct pci_bus *root_bus = find_pci_root_bus(bus); 26 23 27 - return to_pci_host_bridge(bus->bridge); 24 + return to_pci_host_bridge(root_bus->bridge); 28 25 } 29 26 30 27 void pci_set_host_bridge_release(struct pci_host_bridge *bridge, ··· 37 40 return res1->start <= res2->start && res1->end >= res2->end; 38 41 } 39 42 40 - void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, 43 + void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region, 41 44 struct resource *res) 42 45 { 43 - struct pci_host_bridge *bridge = find_pci_host_bridge(dev); 46 + struct pci_host_bridge *bridge = find_pci_host_bridge(bus); 44 47 struct pci_host_bridge_window *window; 45 48 resource_size_t offset = 0; 46 49 ··· 65 68 return region1->start <= region2->start && region1->end >= region2->end; 66 69 } 67 70 68 - void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, 71 + void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res, 69 72 struct pci_bus_region *region) 70 73 { 71 - struct pci_host_bridge *bridge = find_pci_host_bridge(dev); 74 + struct pci_host_bridge *bridge = find_pci_host_bridge(bus); 72 75 struct pci_host_bridge_window *window; 73 76 resource_size_t offset = 0; 74 77
+9 -9
drivers/pci/probe.c
··· 269 269 region.end = l + sz; 270 270 } 271 271 272 - pcibios_bus_to_resource(dev, res, &region); 273 - pcibios_resource_to_bus(dev, &inverted_region, res); 272 + pcibios_bus_to_resource(dev->bus, res, &region); 273 + pcibios_resource_to_bus(dev->bus, &inverted_region, res); 274 274 275 275 /* 276 276 * If "A" is a BAR value (a bus address), "bus_to_resource(A)" is ··· 364 364 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO; 365 365 region.start = base; 366 366 region.end = limit + io_granularity - 1; 367 - pcibios_bus_to_resource(dev, res, &region); 367 + pcibios_bus_to_resource(dev->bus, res, &region); 368 368 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res); 369 369 } 370 370 } ··· 386 386 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM; 387 387 region.start = base; 388 388 region.end = limit + 0xfffff; 389 - pcibios_bus_to_resource(dev, res, &region); 389 + pcibios_bus_to_resource(dev->bus, res, &region); 390 390 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res); 391 391 } 392 392 } ··· 436 436 res->flags |= IORESOURCE_MEM_64; 437 437 region.start = base; 438 438 region.end = limit + 0xfffff; 439 - pcibios_bus_to_resource(dev, res, &region); 439 + pcibios_bus_to_resource(dev->bus, res, &region); 440 440 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res); 441 441 } 442 442 } ··· 1084 1084 region.end = 0x1F7; 1085 1085 res = &dev->resource[0]; 1086 1086 res->flags = LEGACY_IO_RESOURCE; 1087 - pcibios_bus_to_resource(dev, res, &region); 1087 + pcibios_bus_to_resource(dev->bus, res, &region); 1088 1088 region.start = 0x3F6; 1089 1089 region.end = 0x3F6; 1090 1090 res = &dev->resource[1]; 1091 1091 res->flags = LEGACY_IO_RESOURCE; 1092 - pcibios_bus_to_resource(dev, res, &region); 1092 + pcibios_bus_to_resource(dev->bus, res, &region); 1093 1093 } 1094 1094 if ((progif & 4) == 0) { 1095 1095 region.start = 0x170; 1096 1096 region.end = 0x177; 1097 1097 res = &dev->resource[2]; 1098 1098 res->flags = LEGACY_IO_RESOURCE; 1099 - pcibios_bus_to_resource(dev, res, &region); 1099 + pcibios_bus_to_resource(dev->bus, res, &region); 1100 1100 region.start = 0x376; 1101 1101 region.end = 0x376; 1102 1102 res = &dev->resource[3]; 1103 1103 res->flags = LEGACY_IO_RESOURCE; 1104 - pcibios_bus_to_resource(dev, res, &region); 1104 + pcibios_bus_to_resource(dev->bus, res, &region); 1105 1105 } 1106 1106 } 1107 1107 break;
+1 -1
drivers/pci/quirks.c
··· 343 343 /* Convert from PCI bus to resource space */ 344 344 bus_region.start = region; 345 345 bus_region.end = region + size - 1; 346 - pcibios_bus_to_resource(dev, res, &bus_region); 346 + pcibios_bus_to_resource(dev->bus, res, &bus_region); 347 347 348 348 if (!pci_claim_resource(dev, nr)) 349 349 dev_info(&dev->dev, "quirk: %pR claimed by %s\n", res, name);
+1 -1
drivers/pci/rom.c
··· 31 31 if (!res->flags) 32 32 return -1; 33 33 34 - pcibios_resource_to_bus(pdev, &region, res); 34 + pcibios_resource_to_bus(pdev->bus, &region, res); 35 35 pci_read_config_dword(pdev, pdev->rom_base_reg, &rom_addr); 36 36 rom_addr &= ~PCI_ROM_ADDRESS_MASK; 37 37 rom_addr |= region.start | PCI_ROM_ADDRESS_ENABLE;
+8 -8
drivers/pci/setup-bus.c
··· 475 475 &bus->busn_res); 476 476 477 477 res = bus->resource[0]; 478 - pcibios_resource_to_bus(bridge, &region, res); 478 + pcibios_resource_to_bus(bridge->bus, &region, res); 479 479 if (res->flags & IORESOURCE_IO) { 480 480 /* 481 481 * The IO resource is allocated a range twice as large as it ··· 489 489 } 490 490 491 491 res = bus->resource[1]; 492 - pcibios_resource_to_bus(bridge, &region, res); 492 + pcibios_resource_to_bus(bridge->bus, &region, res); 493 493 if (res->flags & IORESOURCE_IO) { 494 494 dev_info(&bridge->dev, " bridge window %pR\n", res); 495 495 pci_write_config_dword(bridge, PCI_CB_IO_BASE_1, ··· 499 499 } 500 500 501 501 res = bus->resource[2]; 502 - pcibios_resource_to_bus(bridge, &region, res); 502 + pcibios_resource_to_bus(bridge->bus, &region, res); 503 503 if (res->flags & IORESOURCE_MEM) { 504 504 dev_info(&bridge->dev, " bridge window %pR\n", res); 505 505 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0, ··· 509 509 } 510 510 511 511 res = bus->resource[3]; 512 - pcibios_resource_to_bus(bridge, &region, res); 512 + pcibios_resource_to_bus(bridge->bus, &region, res); 513 513 if (res->flags & IORESOURCE_MEM) { 514 514 dev_info(&bridge->dev, " bridge window %pR\n", res); 515 515 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1, ··· 547 547 548 548 /* Set up the top and bottom of the PCI I/O segment for this bus. */ 549 549 res = bus->resource[0]; 550 - pcibios_resource_to_bus(bridge, &region, res); 550 + pcibios_resource_to_bus(bridge->bus, &region, res); 551 551 if (res->flags & IORESOURCE_IO) { 552 552 pci_read_config_word(bridge, PCI_IO_BASE, &l); 553 553 io_base_lo = (region.start >> 8) & io_mask; ··· 578 578 579 579 /* Set up the top and bottom of the PCI Memory segment for this bus. */ 580 580 res = bus->resource[1]; 581 - pcibios_resource_to_bus(bridge, &region, res); 581 + pcibios_resource_to_bus(bridge->bus, &region, res); 582 582 if (res->flags & IORESOURCE_MEM) { 583 583 l = (region.start >> 16) & 0xfff0; 584 584 l |= region.end & 0xfff00000; ··· 604 604 /* Set up PREF base/limit. */ 605 605 bu = lu = 0; 606 606 res = bus->resource[2]; 607 - pcibios_resource_to_bus(bridge, &region, res); 607 + pcibios_resource_to_bus(bridge->bus, &region, res); 608 608 if (res->flags & IORESOURCE_PREFETCH) { 609 609 l = (region.start >> 16) & 0xfff0; 610 610 l |= region.end & 0xfff00000; ··· 1424 1424 if (!r->flags) 1425 1425 continue; 1426 1426 1427 - pcibios_resource_to_bus(dev, &region, r); 1427 + pcibios_resource_to_bus(dev->bus, &region, r); 1428 1428 if (!region.start) { 1429 1429 *unassigned = true; 1430 1430 return 1; /* return early from pci_walk_bus() */
+1 -1
drivers/pci/setup-res.c
··· 52 52 if (res->flags & IORESOURCE_PCI_FIXED) 53 53 return; 54 54 55 - pcibios_resource_to_bus(dev, &region, res); 55 + pcibios_resource_to_bus(dev->bus, &region, res); 56 56 57 57 new = region.start | (res->flags & PCI_REGION_FLAG_MASK); 58 58 if (res->flags & IORESOURCE_IO)
+1 -1
drivers/pcmcia/i82092.c
··· 608 608 609 609 enter("i82092aa_set_mem_map"); 610 610 611 - pcibios_resource_to_bus(sock_info->dev, &region, mem->res); 611 + pcibios_resource_to_bus(sock_info->dev->bus, &region, mem->res); 612 612 613 613 map = mem->map; 614 614 if (map > 4) {
+3 -3
drivers/pcmcia/yenta_socket.c
··· 445 445 unsigned int start, stop, card_start; 446 446 unsigned short word; 447 447 448 - pcibios_resource_to_bus(socket->dev, &region, mem->res); 448 + pcibios_resource_to_bus(socket->dev->bus, &region, mem->res); 449 449 450 450 map = mem->map; 451 451 start = region.start; ··· 709 709 region.start = config_readl(socket, addr_start) & mask; 710 710 region.end = config_readl(socket, addr_end) | ~mask; 711 711 if (region.start && region.end > region.start && !override_bios) { 712 - pcibios_bus_to_resource(dev, res, &region); 712 + pcibios_bus_to_resource(dev->bus, res, &region); 713 713 if (pci_claim_resource(dev, PCI_BRIDGE_RESOURCES + nr) == 0) 714 714 return 0; 715 715 dev_printk(KERN_INFO, &dev->dev, ··· 1033 1033 struct pci_dev *dev = socket->dev; 1034 1034 struct pci_bus_region region; 1035 1035 1036 - pcibios_resource_to_bus(socket->dev, &region, &dev->resource[0]); 1036 + pcibios_resource_to_bus(socket->dev->bus, &region, &dev->resource[0]); 1037 1037 1038 1038 config_writel(socket, CB_LEGACY_MODE_BASE, 0); 1039 1039 config_writel(socket, PCI_BASE_ADDRESS_0, region.start);
+3 -2
drivers/scsi/sym53c8xx_2/sym_glue.c
··· 1531 1531 struct pci_bus_region bus_addr; 1532 1532 int i = 2; 1533 1533 1534 - pcibios_resource_to_bus(pdev, &bus_addr, &pdev->resource[1]); 1534 + pcibios_resource_to_bus(pdev->bus, &bus_addr, &pdev->resource[1]); 1535 1535 device->mmio_base = bus_addr.start; 1536 1536 1537 1537 if (device->chip.features & FE_RAM) { ··· 1541 1541 */ 1542 1542 if (!pdev->resource[i].flags) 1543 1543 i++; 1544 - pcibios_resource_to_bus(pdev, &bus_addr, &pdev->resource[i]); 1544 + pcibios_resource_to_bus(pdev->bus, &bus_addr, 1545 + &pdev->resource[i]); 1545 1546 device->ram_base = bus_addr.start; 1546 1547 } 1547 1548
+1 -1
drivers/video/arkfb.c
··· 1014 1014 1015 1015 vga_res.flags = IORESOURCE_IO; 1016 1016 1017 - pcibios_bus_to_resource(dev, &vga_res, &bus_reg); 1017 + pcibios_bus_to_resource(dev->bus, &vga_res, &bus_reg); 1018 1018 1019 1019 par->state.vgabase = (void __iomem *) vga_res.start; 1020 1020
+1 -1
drivers/video/s3fb.c
··· 1180 1180 1181 1181 vga_res.flags = IORESOURCE_IO; 1182 1182 1183 - pcibios_bus_to_resource(dev, &vga_res, &bus_reg); 1183 + pcibios_bus_to_resource(dev->bus, &vga_res, &bus_reg); 1184 1184 1185 1185 par->state.vgabase = (void __iomem *) vga_res.start; 1186 1186
+1 -1
drivers/video/vt8623fb.c
··· 729 729 730 730 vga_res.flags = IORESOURCE_IO; 731 731 732 - pcibios_bus_to_resource(dev, &vga_res, &bus_reg); 732 + pcibios_bus_to_resource(dev->bus, &vga_res, &bus_reg); 733 733 734 734 par->state.vgabase = (void __iomem *) vga_res.start; 735 735
+12 -8
include/linux/pci.h
··· 552 552 int reg, int len, u32 val); 553 553 554 554 struct pci_bus_region { 555 - resource_size_t start; 556 - resource_size_t end; 555 + dma_addr_t start; 556 + dma_addr_t end; 557 557 }; 558 558 559 559 struct pci_dynids { ··· 737 737 738 738 /* Generic PCI functions used internally */ 739 739 740 - void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, 740 + void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region, 741 741 struct resource *res); 742 - void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, 742 + void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res, 743 743 struct pci_bus_region *region); 744 744 void pcibios_scan_specific_bus(int busn); 745 745 struct pci_bus *pci_find_bus(int domain, int busnr); ··· 1088 1088 resource_size_t, 1089 1089 resource_size_t), 1090 1090 void *alignf_data); 1091 + 1092 + static inline dma_addr_t pci_bus_address(struct pci_dev *pdev, int bar) 1093 + { 1094 + struct pci_bus_region region; 1095 + 1096 + pcibios_resource_to_bus(pdev->bus, &region, &pdev->resource[bar]); 1097 + return region.start; 1098 + } 1091 1099 1092 1100 /* Proper probing supporting hot-pluggable devices */ 1093 1101 int __must_check __pci_register_driver(struct pci_driver *, struct module *, ··· 1517 1509 /* Include architecture-dependent settings and functions */ 1518 1510 1519 1511 #include <asm/pci.h> 1520 - 1521 - #ifndef PCIBIOS_MAX_MEM_32 1522 - #define PCIBIOS_MAX_MEM_32 (-1) 1523 - #endif 1524 1512 1525 1513 /* these helpers provide future and backwards compatibility 1526 1514 * for accessing popular PCI BAR info */