Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

Merge tag 'spi-fix-v6.15-merge-window' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi

Pull spi fixes from Mark Brown:
"A small collection of fixes that came in during the merge window,
everything is driver specific with nothing standing out particularly"

* tag 'spi-fix-v6.15-merge-window' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi:
spi: bcm2835: Restore native CS probing when pinctrl-bcm2835 is absent
spi: bcm2835: Do not call gpiod_put() on invalid descriptor
spi: cadence-qspi: revert "Improve spi memory performance"
spi: cadence: Fix out-of-bounds array access in cdns_mrvl_xspi_setup_clock()
spi: fsl-qspi: use devm function instead of driver remove
spi: SPI_QPIC_SNAND should be tristate and depend on MTD
spi-rockchip: Fix register out of bounds access

+39 -22
+2 -2
drivers/spi/Kconfig
··· 937 937 QSPI(Quad SPI) driver for Qualcomm QSPI controller. 938 938 939 939 config SPI_QPIC_SNAND 940 - bool "QPIC SNAND controller" 940 + tristate "QPIC SNAND controller" 941 941 depends on ARCH_QCOM || COMPILE_TEST 942 - select MTD 942 + depends on MTD 943 943 help 944 944 QPIC_SNAND (QPIC SPI NAND) driver for Qualcomm QPIC controller. 945 945 QPIC controller supports both parallel nand and serial nand.
+16 -2
drivers/spi/spi-bcm2835.c
··· 1162 1162 sizeof(u32), 1163 1163 DMA_TO_DEVICE); 1164 1164 1165 - gpiod_put(bs->cs_gpio); 1165 + if (!IS_ERR(bs->cs_gpio)) 1166 + gpiod_put(bs->cs_gpio); 1166 1167 spi_set_csgpiod(spi, 0, NULL); 1167 1168 1168 1169 kfree(target); ··· 1226 1225 struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr); 1227 1226 struct bcm2835_spidev *target = spi_get_ctldata(spi); 1228 1227 struct gpiod_lookup_table *lookup __free(kfree) = NULL; 1229 - int ret; 1228 + const char *pinctrl_compats[] = { 1229 + "brcm,bcm2835-gpio", 1230 + "brcm,bcm2711-gpio", 1231 + "brcm,bcm7211-gpio", 1232 + }; 1233 + int ret, i; 1230 1234 u32 cs; 1231 1235 1232 1236 if (!target) { ··· 1295 1289 ret = -EINVAL; 1296 1290 goto err_cleanup; 1297 1291 } 1292 + 1293 + for (i = 0; i < ARRAY_SIZE(pinctrl_compats); i++) { 1294 + if (of_find_compatible_node(NULL, NULL, pinctrl_compats[i])) 1295 + break; 1296 + } 1297 + 1298 + if (i == ARRAY_SIZE(pinctrl_compats)) 1299 + return 0; 1298 1300 1299 1301 /* 1300 1302 * TODO: The code below is a slightly better alternative to the utter
+1 -1
drivers/spi/spi-cadence-quadspi.c
··· 2073 2073 2074 2074 static const struct cqspi_driver_platdata am654_ospi = { 2075 2075 .hwcaps_mask = CQSPI_SUPPORTS_OCTAL | CQSPI_SUPPORTS_QUAD, 2076 - .quirks = CQSPI_DISABLE_DAC_MODE | CQSPI_NEEDS_WR_DELAY, 2076 + .quirks = CQSPI_NEEDS_WR_DELAY, 2077 2077 }; 2078 2078 2079 2079 static const struct cqspi_driver_platdata intel_lgm_qspi = {
+1 -1
drivers/spi/spi-cadence-xspi.c
··· 432 432 u32 clk_reg; 433 433 bool update_clk = false; 434 434 435 - while (i < ARRAY_SIZE(cdns_mrvl_xspi_clk_div_list)) { 435 + while (i < (ARRAY_SIZE(cdns_mrvl_xspi_clk_div_list) - 1)) { 436 436 clk_val = MRVL_XSPI_CLOCK_DIVIDED( 437 437 cdns_mrvl_xspi_clk_div_list[i]); 438 438 if (clk_val <= requested_clk)
+17 -14
drivers/spi/spi-fsl-qspi.c
··· 844 844 .per_op_freq = true, 845 845 }; 846 846 847 + static void fsl_qspi_cleanup(void *data) 848 + { 849 + struct fsl_qspi *q = data; 850 + 851 + /* disable the hardware */ 852 + qspi_writel(q, QUADSPI_MCR_MDIS_MASK, q->iobase + QUADSPI_MCR); 853 + qspi_writel(q, 0x0, q->iobase + QUADSPI_RSER); 854 + 855 + fsl_qspi_clk_disable_unprep(q); 856 + 857 + mutex_destroy(&q->lock); 858 + } 859 + 847 860 static int fsl_qspi_probe(struct platform_device *pdev) 848 861 { 849 862 struct spi_controller *ctlr; ··· 947 934 948 935 ctlr->dev.of_node = np; 949 936 937 + ret = devm_add_action_or_reset(dev, fsl_qspi_cleanup, q); 938 + if (ret) 939 + goto err_destroy_mutex; 940 + 950 941 ret = devm_spi_register_controller(dev, ctlr); 951 942 if (ret) 952 943 goto err_destroy_mutex; ··· 968 951 969 952 dev_err(dev, "Freescale QuadSPI probe failed\n"); 970 953 return ret; 971 - } 972 - 973 - static void fsl_qspi_remove(struct platform_device *pdev) 974 - { 975 - struct fsl_qspi *q = platform_get_drvdata(pdev); 976 - 977 - /* disable the hardware */ 978 - qspi_writel(q, QUADSPI_MCR_MDIS_MASK, q->iobase + QUADSPI_MCR); 979 - qspi_writel(q, 0x0, q->iobase + QUADSPI_RSER); 980 - 981 - fsl_qspi_clk_disable_unprep(q); 982 - 983 - mutex_destroy(&q->lock); 984 954 } 985 955 986 956 static int fsl_qspi_suspend(struct device *dev) ··· 1007 1003 .pm = &fsl_qspi_pm_ops, 1008 1004 }, 1009 1005 .probe = fsl_qspi_probe, 1010 - .remove = fsl_qspi_remove, 1011 1006 }; 1012 1007 module_platform_driver(fsl_qspi_driver); 1013 1008
+1 -1
drivers/spi/spi-qpic-snand.c
··· 1614 1614 .data = &ipq9574_snandc_props, 1615 1615 }, 1616 1616 {} 1617 - } 1617 + }; 1618 1618 MODULE_DEVICE_TABLE(of, qcom_snandc_of_match); 1619 1619 1620 1620 static struct platform_driver qcom_spi_driver = {
+1 -1
drivers/spi/spi-rockchip.c
··· 547 547 cr0 |= (spi->mode & 0x3U) << CR0_SCPH_OFFSET; 548 548 if (spi->mode & SPI_LSB_FIRST) 549 549 cr0 |= CR0_FBM_LSB << CR0_FBM_OFFSET; 550 - if (spi->mode & SPI_CS_HIGH) 550 + if ((spi->mode & SPI_CS_HIGH) && !(spi_get_csgpiod(spi, 0))) 551 551 cr0 |= BIT(spi_get_chipselect(spi, 0)) << CR0_SOI_OFFSET; 552 552 553 553 if (xfer->rx_buf && xfer->tx_buf)