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[MIPS] All MIPS32 processors support64-bit physical addresses.

Still, only the 4K may actually implement it.

Signed-off-by: Chris Dearman <chris@mips.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

authored by

Chris Dearman and committed by
Ralf Baechle 962f480e 0bfa130e

+10 -10
+1 -1
arch/mips/mm/init.c
··· 142 142 #endif 143 143 vaddr = __fix_to_virt(FIX_CMAP_END - idx); 144 144 pte = mk_pte(page, PAGE_KERNEL); 145 - #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1) 145 + #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) 146 146 entrylo = pte.pte_high; 147 147 #else 148 148 entrylo = pte_val(pte) >> 6;
+1 -1
arch/mips/mm/tlb-r4k.c
··· 299 299 idx = read_c0_index(); 300 300 ptep = pte_offset_map(pmdp, address); 301 301 302 - #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1) 302 + #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) 303 303 write_c0_entrylo0(ptep->pte_high); 304 304 ptep++; 305 305 write_c0_entrylo1(ptep->pte_high);
+2 -2
include/asm-mips/pgtable-32.h
··· 107 107 pmd_val(*pmdp) = ((unsigned long) invalid_pte_table); 108 108 } 109 109 110 - #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1) 110 + #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) 111 111 #define pte_page(x) pfn_to_page(pte_pfn(x)) 112 112 #define pte_pfn(x) ((unsigned long)((x).pte_high >> 6)) 113 113 static inline pte_t ··· 130 130 #define pte_pfn(x) ((unsigned long)((x).pte >> PAGE_SHIFT)) 131 131 #define pfn_pte(pfn, prot) __pte(((unsigned long long)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 132 132 #endif 133 - #endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1) */ 133 + #endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) */ 134 134 135 135 #define __pgd_offset(address) pgd_index(address) 136 136 #define __pud_offset(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
+3 -3
include/asm-mips/pgtable-bits.h
··· 32 32 * unpredictable things. The code (when it is written) to deal with 33 33 * this problem will be in the update_mmu_cache() code for the r4k. 34 34 */ 35 - #if defined(CONFIG_CPU_MIPS32_R1) && defined(CONFIG_64BIT_PHYS_ADDR) 35 + #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) 36 36 37 37 #define _PAGE_PRESENT (1<<6) /* implemented in software */ 38 38 #define _PAGE_READ (1<<7) /* implemented in software */ ··· 122 122 123 123 #endif 124 124 #endif 125 - #endif /* defined(CONFIG_CPU_MIPS32_R1) && defined(CONFIG_64BIT_PHYS_ADDR) */ 125 + #endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) */ 126 126 127 127 #define __READABLE (_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED) 128 128 #define __WRITEABLE (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED) ··· 139 139 #define PAGE_CACHABLE_DEFAULT _CACHE_CACHABLE_COW 140 140 #endif 141 141 142 - #if defined(CONFIG_CPU_MIPS32_R1) && defined(CONFIG_64BIT_PHYS_ADDR) 142 + #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) 143 143 #define CONF_CM_DEFAULT (PAGE_CACHABLE_DEFAULT >> 3) 144 144 #else 145 145 #define CONF_CM_DEFAULT (PAGE_CACHABLE_DEFAULT >> 9)
+3 -3
include/asm-mips/pgtable.h
··· 79 79 #define pmd_page(pmd) (pfn_to_page(pmd_phys(pmd) >> PAGE_SHIFT)) 80 80 #define pmd_page_vaddr(pmd) pmd_val(pmd) 81 81 82 - #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1) 82 + #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) 83 83 84 84 #define pte_none(pte) (!(((pte).pte_low | (pte).pte_high) & ~_PAGE_GLOBAL)) 85 85 #define pte_present(pte) ((pte).pte_low & _PAGE_PRESENT) ··· 182 182 * The following only work if pte_present() is true. 183 183 * Undefined behaviour if not.. 184 184 */ 185 - #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1) 185 + #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) 186 186 static inline int pte_write(pte_t pte) { return pte.pte_low & _PAGE_WRITE; } 187 187 static inline int pte_dirty(pte_t pte) { return pte.pte_low & _PAGE_MODIFIED; } 188 188 static inline int pte_young(pte_t pte) { return pte.pte_low & _PAGE_ACCESSED; } ··· 309 309 */ 310 310 #define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot)) 311 311 312 - #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1) 312 + #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) 313 313 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 314 314 { 315 315 pte.pte_low &= _PAGE_CHG_MASK;