···11/* hardirq.h: PA-RISC hard IRQ support.22 *33 * Copyright (C) 2001 Matthew Wilcox <matthew@wil.cx>44- *55- * The locking is really quite interesting. There's a cpu-local66- * count of how many interrupts are being handled, and a global77- * lock. An interrupt can only be serviced if the global lock88- * is free. You can't be sure no more interrupts are being99- * serviced until you've acquired the lock and then checked1010- * all the per-cpu interrupt counts are all zero. It's a specialised1111- * br_lock, and that's exactly how Sparc does it. We don't because1212- * it's more locking for us. This way is lock-free in the interrupt path.134 */145156#ifndef _PARISC_HARDIRQ_H167#define _PARISC_HARDIRQ_H1781818-#include <linux/threads.h>1919-#include <linux/irq.h>2020-2121-typedef struct {2222- unsigned long __softirq_pending; /* set_bit is used on this */2323-} ____cacheline_aligned irq_cpustat_t;2424-2525-#include <linux/irq_cpustat.h> /* Standard mappings for irq_cpustat_t above */2626-2727-void ack_bad_irq(unsigned int irq);99+#include <asm-generic/hardirq.h>28102911#endif /* _PARISC_HARDIRQ_H */
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arch/parisc/kernel/irq.c
···423423 set_eiem(cpu_eiem); /* EIEM : enable all external intr */424424425425}426426-427427-void ack_bad_irq(unsigned int irq)428428-{429429- printk(KERN_WARNING "unexpected IRQ %d\n", irq);430430-}