davinci-mcasp: use bitfield definitions for PDIR

The current driver creates value for set/clr of PDIR using (x<<26) instead
of the #defines that are convieniently made available.

Update the driver to use the bitfield definitions of PDIR. There is no
functional change introduced by this patch.

Signed-off-by: Ben Gardiner <bengardiner@nanometrics.ca>
Reviewed-by: James Nuss <jamesnuss@nanometrics.ca>
Acked-by: Liam Girdwood <lrg@ti.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>

authored by Ben Gardiner and committed by Mark Brown 9595c8f0 049cfaaa

+6 -3
+6 -3
sound/soc/davinci/davinci-mcasp.c
··· 434 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); 435 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE); 436 437 - mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG, (0x7 << 26)); 438 break; 439 case SND_SOC_DAIFMT_CBM_CFS: 440 /* codec is clock master and frame slave */ ··· 445 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); 446 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE); 447 448 - mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG, (0x2d << 26)); 449 break; 450 case SND_SOC_DAIFMT_CBM_CFM: 451 /* codec is clock and frame master */ ··· 456 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); 457 mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE); 458 459 - mcasp_clr_bits(base + DAVINCI_MCASP_PDIR_REG, (0x3f << 26)); 460 break; 461 462 default:
··· 434 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); 435 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE); 436 437 + mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG, 438 + ACLKX | AHCLKX | AFSX); 439 break; 440 case SND_SOC_DAIFMT_CBM_CFS: 441 /* codec is clock master and frame slave */ ··· 444 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); 445 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE); 446 447 + mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG, 448 + ACLKX | AFSX | ACLKR | AFSR); 449 break; 450 case SND_SOC_DAIFMT_CBM_CFM: 451 /* codec is clock and frame master */ ··· 454 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); 455 mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE); 456 457 + mcasp_clr_bits(base + DAVINCI_MCASP_PDIR_REG, 458 + ACLKX | AHCLKX | AFSX | ACLKR | AHCLKR | AFSR); 459 break; 460 461 default: