Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

clk: amlogic: add composite clock helpers

Device composite clocks tend to reproduce the usual sel/div/gate
arrangement.

Add macros to help define simple composite clocks in the system.

The idea is _not_ to replace all instances of mux, div or gate with those
macros. It is rather to use it for recurring and/or simple composite
clocks, reducing controller verbosity where it makes sense. This should
help reviews focus on the tricky parts.

Link: https://lore.kernel.org/r/20250825-meson-clk-cleanup-24-v2-10-0f402f01e117@baylibre.com
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

+57
+57
drivers/clk/meson/meson-clkc-utils.h
··· 48 48 #define MESON_PCLK_RO(_name, _reg, _bit, _pdata, _flags) \ 49 49 __MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ro_ops, _pdata, _flags) 50 50 51 + /* Helpers for the usual sel/div/gate composite clocks */ 52 + #define MESON_COMP_SEL(_prefix, _name, _reg, _shift, _mask, _pdata, \ 53 + _table, _dflags, _iflags) \ 54 + struct clk_regmap _prefix##_name##_sel = { \ 55 + .data = &(struct clk_regmap_mux_data) { \ 56 + .offset = (_reg), \ 57 + .mask = (_mask), \ 58 + .shift = (_shift), \ 59 + .flags = (_dflags), \ 60 + .table = (_table), \ 61 + }, \ 62 + .hw.init = &(struct clk_init_data){ \ 63 + .name = #_name "_sel", \ 64 + .ops = &clk_regmap_mux_ops, \ 65 + .parent_data = _pdata, \ 66 + .num_parents = ARRAY_SIZE(_pdata), \ 67 + .flags = (_iflags), \ 68 + }, \ 69 + } 70 + 71 + #define MESON_COMP_DIV(_prefix, _name, _reg, _shift, _width, \ 72 + _dflags, _iflags) \ 73 + struct clk_regmap _prefix##_name##_div = { \ 74 + .data = &(struct clk_regmap_div_data) { \ 75 + .offset = (_reg), \ 76 + .shift = (_shift), \ 77 + .width = (_width), \ 78 + .flags = (_dflags), \ 79 + }, \ 80 + .hw.init = &(struct clk_init_data) { \ 81 + .name = #_name "_div", \ 82 + .ops = &clk_regmap_divider_ops, \ 83 + .parent_hws = (const struct clk_hw *[]) { \ 84 + &_prefix##_name##_sel.hw \ 85 + }, \ 86 + .num_parents = 1, \ 87 + .flags = (_iflags), \ 88 + }, \ 89 + } 90 + 91 + #define MESON_COMP_GATE(_prefix, _name, _reg, _bit, _iflags) \ 92 + struct clk_regmap _prefix##_name = { \ 93 + .data = &(struct clk_regmap_gate_data) { \ 94 + .offset = (_reg), \ 95 + .bit_idx = (_bit), \ 96 + }, \ 97 + .hw.init = &(struct clk_init_data) { \ 98 + .name = #_name, \ 99 + .ops = &clk_regmap_gate_ops, \ 100 + .parent_hws = (const struct clk_hw *[]) { \ 101 + &_prefix##_name##_div.hw \ 102 + }, \ 103 + .num_parents = 1, \ 104 + .flags = (_iflags), \ 105 + }, \ 106 + } 107 + 51 108 #endif