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dt-bindings: ufs: mediatek,ufs: convert to dtschema

Convert the Mediatek Universal Flash Storage (UFS) Controller to DT
schema format.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220306111125.116455-8-krzysztof.kozlowski@canonical.com

authored by

Krzysztof Kozlowski and committed by
Rob Herring
954c6010 516075a2

+67 -45
+67
Documentation/devicetree/bindings/ufs/mediatek,ufs.yaml
··· 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/ufs/mediatek,ufs.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Mediatek Universal Flash Storage (UFS) Controller 8 + 9 + maintainers: 10 + - Stanley Chu <stanley.chu@mediatek.com> 11 + 12 + allOf: 13 + - $ref: ufs-common.yaml 14 + 15 + properties: 16 + compatible: 17 + enum: 18 + - mediatek,mt8183-ufshci 19 + - mediatek,mt8192-ufshci 20 + 21 + clocks: 22 + maxItems: 1 23 + 24 + clock-names: 25 + items: 26 + - const: ufs 27 + 28 + phys: 29 + maxItems: 1 30 + 31 + reg: 32 + maxItems: 1 33 + 34 + vcc-supply: true 35 + 36 + required: 37 + - compatible 38 + - clocks 39 + - clock-names 40 + - phys 41 + - reg 42 + - vcc-supply 43 + 44 + unevaluatedProperties: false 45 + 46 + examples: 47 + - | 48 + #include <dt-bindings/clock/mt8183-clk.h> 49 + #include <dt-bindings/interrupt-controller/arm-gic.h> 50 + 51 + soc { 52 + #address-cells = <2>; 53 + #size-cells = <2>; 54 + 55 + ufs@ff3c0000 { 56 + compatible = "mediatek,mt8183-ufshci"; 57 + reg = <0 0x11270000 0 0x2300>; 58 + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>; 59 + phys = <&ufsphy>; 60 + 61 + clocks = <&infracfg_ao CLK_INFRA_UFS>; 62 + clock-names = "ufs"; 63 + freq-table-hz = <0 0>; 64 + 65 + vcc-supply = <&mt_pmic_vemc_ldo_reg>; 66 + }; 67 + };
-45
Documentation/devicetree/bindings/ufs/ufs-mediatek.txt
··· 1 - * Mediatek Universal Flash Storage (UFS) Host Controller 2 - 3 - UFS nodes are defined to describe on-chip UFS hardware macro. 4 - Each UFS Host Controller should have its own node. 5 - 6 - To bind UFS PHY with UFS host controller, the controller node should 7 - contain a phandle reference to UFS M-PHY node. 8 - 9 - Required properties for UFS nodes: 10 - - compatible : Compatible list, contains the following controller: 11 - "mediatek,mt8183-ufshci" for MediaTek UFS host controller 12 - present on MT8183 chipsets. 13 - "mediatek,mt8192-ufshci" for MediaTek UFS host controller 14 - present on MT8192 chipsets. 15 - - reg : Address and length of the UFS register set. 16 - - phys : phandle to m-phy. 17 - - clocks : List of phandle and clock specifier pairs. 18 - - clock-names : List of clock input name strings sorted in the same 19 - order as the clocks property. "ufs" is mandatory. 20 - "ufs": ufshci core control clock. 21 - - freq-table-hz : Array of <min max> operating frequencies stored in the same 22 - order as the clocks property. If this property is not 23 - defined or a value in the array is "0" then it is assumed 24 - that the frequency is set by the parent clock or a 25 - fixed rate clock source. 26 - - vcc-supply : phandle to VCC supply regulator node. 27 - 28 - Example: 29 - 30 - ufsphy: phy@11fa0000 { 31 - ... 32 - }; 33 - 34 - ufshci@11270000 { 35 - compatible = "mediatek,mt8183-ufshci"; 36 - reg = <0 0x11270000 0 0x2300>; 37 - interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>; 38 - phys = <&ufsphy>; 39 - 40 - clocks = <&infracfg_ao INFRACFG_AO_UFS_CG>; 41 - clock-names = "ufs"; 42 - freq-table-hz = <0 0>; 43 - 44 - vcc-supply = <&mt_pmic_vemc_ldo_reg>; 45 - };